JPS63120345A - Microprocessor - Google Patents

Abstract

PURPOSE:To effectively utilize an instruction storing area by holding the address starting position of an internal data group with addition of hardware and therefore eliminating a fact that the starting address of the data group depends on the program capacity. CONSTITUTION:A programmable logic array PLA 100 of a microprocessor stores a data group as well as a program containing instruction groups which are successively carried out. These program and data group are read out by a RAM 200 and applied to a register file 250. At the same time, a 1st computing element 300 carries out the digital data and logic arithmetic. A timing generator 500 controls the actions of the RAM 200, the file 250, the element 300 and a 2nd computing element 350 based on an instruction given from the PLA 100. Then the specific instructions stored in the PLA 100 are selected by a programmable counter 600 based on the output of the generator 500. While the specific data is selected by a data address register 650.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a microprocessor with high data processing efficiency.

2. Description of the Related Art In recent years, von Neumann microprocessors have been widely used in various fields, and they consist of a program storage means for storing a program consisting of a group of instructions to be executed sequentially, and a data storage means for reading and writing digital data. a data bus connecting the input/output terminals of the data storage means and the input/output terminals of the calculation means; a control means for controlling the operations of the data storage means and the arithmetic means; a timing generator for generating an instruction execution timing signal; and a specific instruction stored in the program storage means based on the output of the timing generator. It is characterized by having a command selection means.

Further, a typical structure thereof is shown in Japanese Patent Publication No. 58-33584.

Problems to be Solved by the Invention By the way, when a program and a data group are stored in a common instruction storage area, the starting address of the data group becomes a problem. In other words, if the instruction storage area is divided into two parts, it is essentially the same as having two separate instruction storage areas, so there is no problem with the start address, but on the other hand, the problem of the start address does not occur. Unless the capacity of each of the
The method of sequentially allocating addresses and then storing data groups allows efficient use of the instruction storage area, but on the other hand,
Since the start address of a data group depends on the capacity of the program, it was necessary to internally hold information on the start position of the data group.

Means for Solving the Problems In order to solve the above-mentioned problems, the microprocessor of the present invention has a program consisting of a group of instructions that are consecutively arranged from a low-order address to a high-order address and executed sequentially. Identification of the program stored in the program storage means based on the output of a program storage means for storing data that is consecutively arranged from an address to a low address and sequentially referenced, and a timing generator that generates an instruction execution timing signal. and a data reference means for referring to specific data of a data group stored in a data storage area of the program storage means.

Effects of the Invention With the above-described configuration, the present invention can provide a microprocessor with high expandability and high memory utilization efficiency.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration diagram of a microprocessor according to an embodiment of the present invention, and shows a programmable logic array (a read-only array for storing instructions) in which a program consisting of a group of instructions to be executed sequentially and a group of data are stored. Memory forms the centerpiece and is designated in the figure by the abbreviation PLA.

Hereinafter, it will be abbreviated as PLA. ) 100, a random access memory (indicated by the abbreviation RAM in the figure, hereinafter abbreviated as RAM) 200 for reading and writing digital data, and a register file 250.
The first one that performs arithmetic and logical operations on digital data.
arithmetic unit (generally indicated by the abbreviation ALU) 3
00 and the second arithmetic unit 350, a data bus 400 connecting the common input/output terminals of the RAM 200 and the register file 250, and the input/output terminals of the arithmetic units 300 and 350, and instructions sent from the PLA 100. Based on the RAM 200° register file 250
, a control bus 450 that controls the M operation of the arithmetic units 300 and 350, and an external clock input terminal lo.
A timing generator (indicated by the abbreviation TG in the figure) that generates an instruction execution timing signal based on a clock signal supplied to SOO and the P
A programmable counter (indicated by the abbreviation PC in the figure) 600 that selects a specific instruction stored in the LA 100, and the timing generator 50.
It is provided with a data address register (indicated by the abbreviation DR in the figure) 650 that selects specific data of the PLA 100 based on the output of 0.

Further, a 16-bit counter 8 is supplied with the output signal of the timing generator 500 as a clock signal.
00, a switch circuit 900 for sending the counter value of the counter 800 to the data bus 400, a specific bit output signal of the counter 8oo, and an output signal indicating a specific counter value of the programmable counter 600 (for example, A frequency comparator 1000 is provided which compares the frequencies of the output signals ((000...00)) and resets the programmable counter 600 when the program enters an infinite loop. Furthermore, the timing generator 50
The output signal of 0 is used as a clock signal, and the external signal input terminal 2
A timer 1100 that operates when the edge of a signal applied to 0 arrives or is started by a program, and a master-slave format in which data in the master latch section is transferred to the slave latch section by the output signal of the timer 1100. Output boat 1200
and a D-A converter 1300 that takes in the data sent to the data bus 400 and converts it into an analog voltage.
and the RAM 200 and the register file 25.
0 (the RAM 200 and the register file 250 are arranged at different addresses). Note that when the edge of the input signal applied to the external signal input terminals 30, 40, 50, 60, 70° 80 arrives, the input controller 1500 stores the round l-value of the counter 800 at that time in the register file 250. (If the edges of multiple input signals arrive at the same time, multiple registers are selected.) In addition, the input signal receiver (not shown) has the function of setting a flag. have.

Regarding the microprocessor configured as above,
The operation will be explained with reference to the configuration diagram shown in FIG. 1 and the timing chart of the main parts shown in FIG.

First, Figure 2 fa) is the external clock input terminal 1 in Figure 1.
0 shows the clock signal waveform supplied to
(in FIG. 2) also shows the clock signal waveform supplied to the counter 800, timer 1ioo, and input controller 1500 via the timing generator 500, and FIG. The clock signal waveform supplied to the programmable counter 600 is shown in FIG.
represents the execution cycle of instructions sent to

Furthermore, FIG. 2 fdl represents a switching cycle of data sent to the data bus 400.

In other words, the programmable counter 600
loo is selected, and the instruction is sent to the control bus 450 at the timing shown in FIG. 2 (C1).The switching period of the data bus 400 shown in FIG. (The reason why the control bus 450 shown in C1 is half that of the control bus 450 shown in FIG.
This is because the count value is allocated to transfer to the register file 250. Note that the count value of the programmer file counter is updated at the edge marked with an arrow in FIG. 2 (01), but in FIG. This is because the delay margin in PLAloo is considered.

In this way, programs stored in PLAloo can be executed in a time-sharing manner.

Figure 3 shows PLAloo and programmable counter 600.
This is a configuration diagram showing the arrangement of programs and data groups in the internal program storage section of PLAloo.
The inverted output of each bit of the up-count type programmable counter 600 of bits (assuming a program area of 1024 bytes for n dogs) is transmitted through 3-state inverters 601 to 610 to 7PLA100 (7)? )
' is supplied to the response decoder 110. Also, PLA
Loo's program storage unit 120 is divided into two areas: area A where programs executed by the programmable counter 600 are stored and area B where data referenced by the data address register 650 is stored. The instruction code is supplied to an instruction decoder 140 via an instruction bus 130, converted into a control code, and then sent to a control bus 450.

Incidentally, in area A of the program storage section 120, consecutive instructions in the direction a in FIG. 3 are arranged, while in area B, continuous data in the direction b is arranged. That is, in the program selected and executed by the programmable counter 600, the instruction group is arranged consecutively from the low address to the high address, the starting address is address [00...000], and the data address register The data group referenced by 650 is arranged consecutively from a high address to a low address, and its starting address is [11...111].

Therefore, at the time of system reset, etc., the program can be executed from its starting address by simply resetting the programmable counter 600, and there is no restriction on the ending address of the program and the data group other than overlapping. Therefore, the area of the program storage unit 120 can be used efficiently as long as the memory capacity allows.

Effects of the Invention As is clear from the above description, the microprocessor of the present invention has a program consisting of a group of instructions arranged consecutively from a low address to a high address and executed sequentially, and a program consisting of a group of instructions consecutively arranged from a low address to a high address and executed sequentially from a high address to a low address. A program storage means (PLAloo) that stores a data group that is arranged and referred to sequentially, a data storage means (RAM 200) capable of reading and writing digital data, and an arithmetic means (arithmetic unit 300) that executes arithmetic operations on digital data.
．． 350), a data bus 400 connecting the input/output terminals of the data storage means and the input/output terminals of the calculation means;
control means (control bus 450) that controls the operations of the data storage means and the arithmetic means based on instructions sent from the program storage means; and a timing generator 500 that generates instruction execution timing signals. instruction selection means (programmable counter 600) for selecting a specific instruction of the program stored in the program storage means; data reference means (data address) for referencing specific data of the data group stored in the program storage means; 650), it is possible to obtain a microprocessor that is highly compatible with higher-end models, has high expandability, and has high memory utilization efficiency.
It has a great effect.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a microprocessor in an embodiment of the present invention, FIG. 2 is a timing chart of the main parts of FIG. 1, and FIG. 3 is a connection relationship between the PLA and programmable counter in FIG. FIG. 2 is a configuration diagram showing the arrangement of programs and data groups in the program storage unit of FIG. 100...PLA, 200...RAM
, 300... Arithmetic unit, 350... Arithmetic unit, 400... Data bus, 450...
- Control bus, 500...timing generator, 600...programmable counter, 650...data address register.

Claims (1)

[Claims] A program storage means for storing a program consisting of a group of instructions arranged consecutively from a low address to a high address and executed sequentially and a group of data arranged consecutively from a high address to a low address, and capable of reading and writing digital data. a data storage means, an arithmetic means for executing an arithmetic operation on digital data, a data bus connecting an input/output terminal of the data storage means and an input/output terminal of the arithmetic means, and a command sent from the program storage means. control means for controlling the operations of the data storage means and the calculation means based on the timing generator; and a timing generator for generating an instruction execution timing signal.
instruction selection means for selecting a specific instruction of the program stored in the program storage means based on the output of the timing generator; and data stored in the data storage area of the program storage means based on the output of the timing generator. A microprocessor comprising data reference means for referencing specific data of a group.