JPS63118875A - Array processor - Google Patents

Abstract

PURPOSE:To obtain an array processor of simple constitution that can carry out double DO loop processing at a high speed, by applying the pipeline control to carry out each inside loop processing of the double DO loop processing and at the same time carrying out these DO loop processings in parallel with each other. CONSTITUTION:A central vector processing unit VPC fetches and decodes a vector instruction or an array instruction. Then the vector instruction if decoded is carried out. While the vector processing units PE1-PEM are started when the array instruction is decoded. Each of these units PE1-PEM decodes the instruction fetched by the unit VPC when it is started by the VPC (in array instruction mode) and carries out an arithmetic operation designated by an instruction to a single vector array of the array data designated by the decoded instruction and to undergo an arithmetic operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a digital electronic computer suitable for array processing (hereinafter referred to as an array processor) capable of executing array operations at high speed.

[Background technology]

In scientific and technical calculations, there is a demand for faster two-dimensional array calculations as shown in the Fortran program shown in FIG. Hereinafter, one-dimensional and two-dimensional arrays will be referred to as vectors and arrays, respectively, for simplicity. To date, the following two approaches have been taken to speed up array calculations. The first is to arrange many processors in parallel in two dimensions,
This is an array processor method that simultaneously executes parallel processing on a large number of array elements. With this approach, by increasing the number of processors, performance can be expected to improve in principle in proportion to the number of processors. However, in cases where the number of array elements to be processed is smaller than the number of installed processors, the utilization rate of the processors is low and it is not economically advantageous. The second method is a vector processor method that uses vector registers and pipeline-controlled arithmetic units to speed up vector processing.

A representative example thereof is described in US Pat. No. 4,128,880. A vector processor can speed up processing related to a single Do loop, but there is a limit to speeding up double loop processing.

The program in Figure 1 is usually divided into single loop processing A1 to AM as shown in Figure 2, and these loop processing A1 to
This is because AM has no choice but to be executed in chronological order.

[Purpose of the invention]

The present invention executes each of the inner loop processes of the double Do loop process under pipeline control, and.

By executing these Do loop processes in parallel, the double Do loop process can be executed at high speed. The purpose of the present invention is to provide an array processor with a simple configuration.

[Summary of the invention]

For this reason, the present invention provides a central vector processing unit that has a plurality of vector registers and a pipeline-controlled arithmetic unit and executes an instruction (vector instruction) that requests vector processing, and a central vector processing unit that has a plurality of vector registers and a pipeline-controlled arithmetic unit; It has a control calculator.

An array processor is configured as a plurality of vector processing units for executing instructions that require array processing (array instructions). The central vector processing unit fetches and decodes vector instructions or array instructions, executes the decoded instruction when it is a vector instruction, and activates these vector processing units when the decoded instruction is an array instruction. Each vector processing unit, when activated by the central vector processing unit (in the case of an array instruction), decodes the instruction fetched by the central vector processing unit and generates one vector of array data to be subjected to the operation specified by the instruction. Performs the operation specified by the instruction on the data. When the operation result specified by the array instruction is vector data, each vector processing unit calculates one element of this result vector,
It is stored in an internal scalar register and sent to the central vector processing unit for storage in a vector register within the central vector processing unit. When the operation result specified by the array instruction is array data, each vector and processing unit calculates one vector data of the resulting array data and stores it in a built-in vector register.

[Embodiments of the invention]

As shown in FIG. 3, the array processor according to the present invention includes a scalar processing unit SP, a central vector processing unit VPC, M vector processing units PE to PEM,
Main memory device (MS) C51 provided in common to these,
It has a main storage control unit (SCU) C52. The main memory C51 is divided into a vector array instruction string consisting of a scalar instruction string, a vector instruction, that is, an instruction that does not request array processing but requests vector processing, and an array instruction, that is, an instruction that requests array processing. In addition, scalar, vector, and array data are stored and accessed by the main storage control unit C52. Hereinafter, both vector instructions and array instructions may be simply referred to as vector array instructions.

The scalar processing unit SP has a scalar instruction register (SI
R) MS1. It has a general-purpose register (GR) MS2, a scalar arithmetic unit C53, and a control unit SC○ that controls these, and executes a scalar instruction string in the main memory C51. This scalar instruction string includes general scalar instructions, such as the manual r system/
370Principles of 0perat
ionJ (GC-22-7000). The scalar processing unit SP performs a scalar operation on the scalar data in the general-purpose register M52 or the main memory C5l according to these instructions,
The result is stored in general-purpose register M52 or main memory C5.
Store in 1. In addition to these scalar instructions, the scalar processing unit SP also has a central vector processing unit vP.
A scalar instruction and a central vector processing unit v for reading data necessary for the operation of C and vector processing units PE1 to PEM from a general-purpose register M52 and providing it to the central vector processing unit PC through a line 37.
Executes a scalar instruction that instructs PC startup (details will be described later).

The central vector processing unit PC is activated by the scalar processing unit SP, fetches a vector array instruction sequence from the main memory C51, executes it when the fetched instruction is a vector instruction, and stores the fetched instruction in the array. In the case of an instruction, vector processing units PE1 to
Start PEM. Furthermore, the central vector processing unit v
Pc sets up vector data necessary for array processing in the vector processing units PE1 to PEM via the search line 44 in these units PE1 to PEM by vector processing.

The vector processing units PE1 to PEM are combined to execute one array instruction, and each vector processing unit PE performs one column vector or one row vector of array data specified by a certain array instruction. The operation specified by the array instruction is executed by another vector processing unit P.
Execute in parallel with E.

In this embodiment, the vector processing units PE, ~PEM are configured to execute only array instructions whose operation result is array data or vector data, and not to execute array instructions whose operation result is scalar data. . As a result, array processing in which the result of an operation is scalar data is different from an array instruction in which the result of an operation is vector data.
This result vector is used to execute a vector instruction to obtain scalar data. These array instructions and vector instructions are processed by the vector processing unit PE.
It is implemented by PEM and central vector processing unit vPC. For this purpose, in order for the central vector processing unit vPC to utilize the result vectors of the array processing in the vector processing units PE1 to PEM, the calculation result vectors are transferred from the vector processing units PE1 to PEM to the lines 471 to 471.
It is configured to receive via M.

Furthermore, among array processing, array processing using array data and scalar data is performed by vector processing units PE1 to
When performing such array processing, which is not performed by PEM, the central vector processing unit VPC executes a vector instruction that creates vector data from this scalar data as an element of the same scalar data number, and then performs vector processing on this vector data. Unit PE1~PEM
An array instruction is executed that directs an operation on the array data and this vector data. For this purpose, the central vector processing unit vPC is configured to transfer the vector data obtained by the vector operations to the vector processing units PE1 to PEM via the line 44.

In this embodiment, the scalar processing unit SP uses the main memory control device C51 to fetch scalar instructions, scalar data, or store scalar data in the main memory device C51.
52 to issue an access request.

The central vector processing unit vPC also issues an access request to the main memory controller C52 in order to perform a vector array command, fetch vector data, or store vector data in the main memory C51. On the other hand, each of the vector processing units PE1 to PEM issues an access request to the main memory controller C52 to fetch or store one row or column vector in the array data.

Vector array instructions fetched based on an instruction fetch request from the central vector processing unit vPC are shown on line 6.
3, it is also input to the central vector processing unit vPC and vector processing units PE to PEM, and this fetched instruction is taken into the vector processing units PE1 to PEM only when it is an array instruction. (Details will be explained later).

The main memory control unit C52 includes scalar processing units 1 to S.
In response to a read request for scalar data or a scalar instruction from the control unit SCO of P, the scalar processing unit SP
The scalar data or scalar instruction specified by the address given from the control unit SCO is read from the main memory C51, the scalar data is sent to the general-purpose register M52 of the scalar processing unit SP or the scalar arithmetic unit C53, and the scalar instruction is sent to the scalar processing unit SP. It is sent to the instruction register M51. Also,
The main memory control unit C52 includes a scalar processing unit SP
In response to a data write request from the control unit SCO,
The general-purpose register M52 or scalar arithmetic unit C5 of that unit SP is stored at the location in the main memory C51 specified by the address given from the control unit SCO of that unit SP.
Stores the scalar data given from 3.

Similarly, main memory control unit C52, in response to a read request for data or vector array instructions from central vector processing unit vPC,
The data or vector array instructions specified by the data or instruction addresses provided from C on lines 64 or 71, respectively, are read from the main memory bag [C51 and sent on lines 43 or 63, respectively, to the central vector processing unit VPC. Vector array instructions on line 63 are also input to vector processing units PE1-PEM. In addition, in response to a data write request from the central vector processing unit vPC, the main memory control unit C52 writes data to the location in the main memory C51 specified by the address given by the line 64 from the unit PC. , line 40
Store the above data.

Similarly, main memory control unit C52 reads data specified by address line 1301 from main memory device C51 in response to a data read request from vector processing unit PEi (+=1 to M), and ．． The data is sent to the vector processing unit PE1 through the vector processing unit PE1. In addition, the main memory control unit C52 responds to a data write request from the vector processing unit PE, and the address line 1301
A line 118 is placed at the location in the main storage device C51 specified by
Store the data on 1.

In this way, the storage control unit C52 according to the present invention:
Scalar processing unit SP, central vector processing unit v
PC1 and M vector processing units PE□~PE
In response to an access request from M.

configured to respond separately.

As shown in FIG. 4(a), the central vector processing unit vPC has L vector registers VC of vector length M.
It has I to VCL and Z scalar registers SCI to SCZ. Each vector processing unit PEi also has vector registers V, 1 to VIK, of vector length N,
L scalar registers S = l −8i, the same number as the vector registers of the central vector processing unit vPC
It has L. These register groups are shown in Figure 4(b) to (
By reconfiguring as in d), a conceptual scalar register SR that handles scalar data, a conceptual vector register VR1 that handles vector data, and a conceptual array register AR that handles array data are defined. That is, the scalar register S of the central vector processing unit vPC
CI to SC2 and vector registers VC1 to VCL are converted into conceptual scalar registers SRI to SRZ, respectively.
.

Vector registers VTjl to VRL are defined. Also,
As shown in FIG. 4(c), the same number scalar registers of each vector processing unit PE1 to PEM, for example S
The sequential arrangement of 01 to SM1 is also defined as the conceptual first vector register VRI. Similarly, conceptual vector registers VR2 to VRL numbered 2 to L are defined. In this embodiment, the vector register VCJ of the central vector processing unit VPC and the vector processing units PE1 to PEM
Since the same conceptual vector register VR, , is defined by all of the scalar registers 84 to SM,
As will be described in detail later, the contents of vector register vCj and scalar registers 5iJ-3 and AJ are controlled to be the same. Also, vector processing units l-P E , ~P
Same number vector register of EM, e.g. Vil~vM
1 arranged in order as shown in Figure 4(d) is conceptually 1.
The number array register ARI is defined as the number array register ARI. Similarly, conceptual array registers AR2-ARK are defined.

As a result, this embodiment uses NXM as a conceptual register.
It has two array registers AR, five vector registers VR of vector length M, and Z scalar registers.

In this embodiment, the conceptual registers that can be accessed by the central vector processing unit vPC and the vector processing units PE, -PEM are different. In other words, the central vector processing unit PC has five conceptual vector registers VRJ.
(j = 1 to L) and two conceptual scalar registers SR
(i=1 to 2), but cannot conceptually handle 2 array registers ARk (k=1 to K). In addition, vector processing units PE, ~PEM can handle conceptual array register ARk (k = 1 ~ K) and conceptual vector register VRa (j = l ~ K), and can handle scalar register SR1 (i = 1 ~ Z). can't handle it. For this reason, in this system, operations on array data and scalar data cannot be directly executed by the vector processing units PE1 to PEM.

After transferring the contents of the conceptual scalar register SR1 to the conceptual vector register VRj, the processing is executed by the vector processing units PE1 to PEM using the conceptual vector register VR,j and the conceptual array register ARk. Ru. In other words, the conceptual vector register VR,
serves as an interface between the central vector processing unit vPC and the vector processing units PE1 to PEM.

Conversely, when performing vector operations with other scalar data using vector data obtained as a result of operations on array data executed by the vector processing units PE1 to PEM, the central vector processing unit A vector operation is performed using the above-mentioned result vector data in register vRJ. For this reason, the contents of the vector register vCJ and the space register group S I J """ S M j that constitute the conceptual vector register VRJ are controlled to be the same. That is, the vector processing units PE1 to PEM process the array data. When vector data is obtained as a result of the calculation for , this vector data is stored in the square register group S1.j to SMJ and also stored in the vector register V CJ.On the contrary, the central vector processing unit When vPC performs an operation on vector data, when solid data is obtained, this vector data is stored in the vector register VCI and also in the blank register group Sx=~SM□. In the following, for the sake of simplicity, conceptual scalar registers, vector registers, and array registers will simply be referred to as scalar registers SR.

They are called vector register VR and array register AR. Further, the first conceptual scalar register is simply referred to as a scalar register SR. The same holds true for conceptual vector registers and array registers. Note that in the following, scalar registers SCI to SCZ, S t 1 to S I L,
S 2 l-82L, 7...=-8M1~SML
are collectively stored in scalar registers sc, s, , s2 .
...It is sometimes called tsM. Similarly, vector registers VCI to VCL.

V11-Vt K, V21-V2, □..., V
MI to vMK are collectively stored in vector register VC.
, V t -V 2-... Sometimes called eVM.

FIG. 5 shows the format of instruction words describing vector instructions and array instructions used in the play processor of the present invention. The OP field specifies the instruction code, the R1 field basically specifies the number of the register where the result of the operation is stored, and the R2 and R3 fields basically specify the number of the register that will be the input of the operation. A, ■1 bit indicates that the register specified by the R1 field is the array register AR/
It is used to identify whether it is a vector register VR or a scalar register SR, and as shown in FIG. 6, when these are 711178, the array register AR is reo.
When lrr, vector register VR, and '''00
'' indicates the scalar register SR.

Similarly A2. ■2 bit and A3. The V3 bit indicates the type of register specified by the R2 and R3 fields, respectively. By separating the instruction code, register number, and register type in this way, operations regarding various registers can be specified uniformly with the same instruction code as shown in FIG.

FIGS. 7(a) to 7(d) show instruction words according to the invention for executing the program portions described in the respective left-hand portions. Here, MtJLT represents the instruction code for multiplication.

In the case of FIG. 7(a), array registers AR2, AR
Array data B (I, J) respectively stored in 3
The program of FIG. 7(a) is executed by storing the product of C(I, J) in array register A(I, J). Execution of this product can be instructed by an instruction word containing only the array register number.

Similarly, in the program of FIG. 7(b), the array register Δ
Day'lr3 (■t J) in R2 (r=1~
The product A (I, J) of vector data X (J) in the vector register VRL is stored in the array register AR,1. The instruction word specifying this product includes an array register number and a vector register number as shown.

In FIG. 7(c), vector data Y (J) respectively located in vector registers VR2 and VR3.

The program shown in the figure is executed by storing the product X (J) of Z(J) (J=1 to M) in the vector register VRI. The instruction word specifying the execution of this product consists only of vector register numbers as shown in the figure.

In FIG. 7(d), the program shown in the figure is executed by calculating the product X (J) of vector data Y (J) in vector register VR2 and scalar data S in scalar register SRI and storing it in vector register VRL. be done. The instruction word specifying the execution of this product includes a scalar register number and a vector register number. In this way, the same instruction code and instruction format can be used for multiplication between array registers, multiplication between array registers and vector registers, multiplication between vector registers, and multiplication between vector registers and spacing registers. The difference in the type of register used is only reflected in the difference in the value of the A i rBi bit.

An instruction that specifies an array register in any of the R1, R2, and R3 fields of the instruction is hereinafter referred to as an array instruction. An instruction in which no array register is specified and a vector register is specified is defined as a vector instruction.

In addition, an operation or process using an array instruction is hereinafter referred to as an array operation or an array process, respectively. Similarly, operations or processing using vector instructions are called vector operations or vector processing, respectively.

8 and 9 show details of the central vector processing unit vpc and vector processing unit I-PEL, respectively. The details of the operation of these devices are shown below in Figure 11(a).
The explanation will be based on the array operation program.

Now, as an assumption, array data A, B, and C are all 1
It consists of 00x100 elements, and each element is 8 bytes long. Furthermore, each element of array data A is stored in the main memory C51.
As shown in FIG. 13 above, it is assumed that elements having the same control variable J are successively stored in order of the size of the control variable J. It is assumed that the arrangement of each element of array data B and C is also similar.

In the program shown in FIG. 11(a), the control variable J is sequentially set to 1.
to M, and for each value of J, the control variable ■
is sequentially changed from 1 to J+1, and for each combination of ■ and J, array element B(I.

Find the sum A (I, J) of J) and C (1, J).

Statements specifying the value of M are not shown for simplicity. When the control variable J has a certain value, the data obtained by changing the control variable I, that is, the data A(T) processed by the inner loop.

J), l3(I, J), and C(1, J) become one vector data. Therefore, array data, for example A, is a collection of vector data each corresponding to a different value of J.

In this embodiment, the vector processing unit PE processes the vector data processed in the inner loop, that is, one column pect/L/data A (1
, i) (I = 1 to i, +I) in a pipeline manner, and each backup processing unit PE1
〜Betta 1〜 processing in PEM is executed in parallel with each other.

In this way, processing of array data is performed at high speed. In this case, although the vector length of each column vector is different, in this embodiment, each vector processing unit PEl is configured to be able to perform calculations for any necessary vector length.

In this embodiment, Ig! In order to prepare, the following setup processing is required. In addition,
Among the following setup processes, scalar processing is executed by the scalar processing unit SP, and vector processing is executed by the central vector processing unit vpc.

Setup 1: Calculate the number of possible values of control variables I and J of a double Do loop indicating array operation. Do sideways
The number of possible values of the control variable J of the loop is defined as the vector length V
I'll call it L. This calculation is performed by the scalar processing unit S
Perform this using P (scalar processing). In the present example, the vector length VL is M from the range of J. Further, the number of possible values of the control variable I of the inner Do loop is called vector length AL.

Since the vector θ torque length AL is generally a function of the control variable J of the outer DO loop and is a vector quantity, it is hereinafter expressed as AL(J). This vector length AL (J) indicates the vector length to be processed by each vector processing unit PE. This calculation is performed by scalar processing and vector processing. In the present example, the vector length ΔL (J) from the range of ■ is 2I for each J=1.2°...1M
3. ...9M+1.

Note that when the program to be executed consists of a single loop, that is, when vector operations are required, this -
The possible range of the control variable of the heavy Do loop is calculated as the vector length VL to be processed (scalar processing).

Setup 2: Calculate the start address VADR of the storage location in the main memory of vector or array data to be subjected to vector or array processing (scalar processing). In the present example, the addresses A(1,1), B(1,1), and C(1,1) are obtained as the start addresses of array data A, B, and C, respectively.

Setup 3 Calculate the address increment value INCV between adjacent elements such as A (I, j) and A (I, j+1) with respect to the control variable J of the outer DO loop of each of near array data A, B, C (scalar process). For any of the array data A, B, and C in the current example, the address increment value INCV regarding the control variable J is 7L/I data A is 1.
Because it is an array of 00x100 and one word is 8 bytes.

It becomes 800. Also, the adjacent elements regarding the control variable ■ of the inner Do loop of the array data, for example, A (i, J)
Incremental value INCA of address between and A (i+1.J)
is calculated as a function of the control variable J.

Since this increment value INCA (J) is generally vector data, it is obtained by scalar processing and vector processing. In this example, it is array data A.

Regarding B and C, the increment value INCA (J) between adjacent elements regarding the control variable ■ is 8 regardless of the value of the control variable J because each element is 8 by 1-.

Note that if the program to be executed is a single Do loop that requires vector operations, the increment value of the address between adjacent data using the control variable of the DO loop is calculated, and this is
NCV (scalar processing).

Start address VADR and address increment value INC for each of set-up 4 near array data A, B, and C
Inside the double DO loop from V.

Vector data A (
I, J), B (I, JL, C(I, J), (1=l
-J+1) address of the first element A A D RA(J
) (vector processing).

In the current example, the start address of array data A is AADRA (
J) (J=1-M) is A (1,1).

A(1,2)...This is the address of A(1,M).

The same applies to array data B and C. Note that when a program consists of a single DO loop, the address A of the first element of the data processed in that Do loop is
D Rn (J), A A D Rc (J)
is required.

Setup 5: Vector files on main memory C51
Calculates the first instruction address of the array instruction string (scalar processing).

FIG. 11(b) shows an instruction sequence for executing the program shown in FIG. 11(a). In starting the vector array instruction sequence v1 to Vll in the central vector processing unit vPC and the vector processing units PE1 to PEM.

The scalar processing unit SP executes a scalar instruction sequence S1 and a scalar instruction S2.

(Scalar Instruction Sequence St) The instruction sequence S1 executes a process indicated as a scalar process among the aforementioned set-up processes. The scalar processing unit SP uses a simplified version of the scalar processing unit shown in Japanese Patent Application No. 56-42314. That is, the above application has a configuration in which the following six instructions can be executed in addition to general scalar instructions. (1) 5tart Vector
Processor (S V P ) instruction (2) S
et Vector Address RefXist
er (SVAR) instruction (3) Set Vector
AddressIcrement Register
r (SV A I R) instruction (4) Set 5c
alar Register (SSR) instruction (5
) Read 5calar Register (R
S R) Instruction (6) Te5t, Vector Pr
ocessor (T V P ) instruction. □In the scalar processing unit SP of the array processor of the present invention,
Among these, svp instruction and SSR instruction.

The configuration is such that it can execute TVP instructions. Namely.

From the scalar processing unit of the above application, 5 VAR instructions, 5
A flip-flop and its output line where the decoding results of the VATR and R5R instructions are set, and the R8R
The configuration does not include data lines for executing instructions.

The instruction sequence S1 calculates the aforementioned scalar data necessary for executing the vector array instruction as a set-up process, and among these data, data other than the vector length VL and the first instruction address are sent to the central vector processing unit vPC. Set in scalar register Sc.

For this processing, the necessary data is calculated using a normal scalar instruction and stored in the general-purpose register GR (Figure 3).
The SSR instruction sets the scalar data in the general-purpose register GR to the scalar register SC.6 When the SSR instruction is decoded by the scalar processing unit l-SP, the central vector processing unit ■PC (Fig. 8) receives data from line 37. The data in the (selected) general-purpose register OR is input from line 35 to the register number of the scalar register SC specified by this instruction. Selector L24
．． L25 is 1101t on the output line 36 of the flip-flop (hereinafter abbreviated as FF) F5 which is in the reset state at this time.
Select the register number and scalar data on lines 35 and 37, respectively, corresponding to the signal. The scalar register SC is connected via line 70 from the scalar processing unit hSP to the SSR register SC.
Write No. 18 obtained by decoding the instruction is given. The multiplexer r, 26 is one scalar register SC corresponding to the register number output from the selector L24.
The scalar data output from selector L25 is sent to i.

Thus, the scalar register SC specified by the SSR instruction
Scalar data is written to 8. In addition, FF and F5 are
When the scalar processing unit SP is in operation, "o" is set, and when the central vector processing unit vPc or vector processing unit PEi is in operation, 111 II is set. The next scalar data is stored in the scalar register SC by the above processing. can be set.

The start address VADR(A) of array data A is stored in the scalar register SC1. Similarly, the scalar register SC2 contains the start address VADR (
B) The scalar register SC3 contains the start address VADR(C) of the array data C, and the scalar register SC4 contains the address increment value I regarding the control variable J to the array data.
NCV (address increment value t N of array data B, C
CV is also the same value in this program), and SC5 contains the address increment value INC regarding control variable I of array data A.
A (INCA of array data B and C are also the same value in this case), scalar data "'2" necessary for calculating the vector length ΔL is stored in the scalar register SC6.

(Instruction S2) When the setup using the SSR instruction sequence is completed, an SvP instruction is executed to instruct the central vector processing unit vPC to start executing the vector array instruction. When the SVP instruction is executed, the vector length VL and the first instruction address of the vector array instruction sequence are read from the general-purpose register GR specified by this instruction, and are sent to the central back 1 via lines 60 and 37, respectively.
- sent to the file processing unit vPC. Furthermore, an SvP instruction decode signal is output to a line 57 from the scalar processing unit SP. In response to this signal, vector length VL on line 60 is stored in VLR register M4.

Furthermore, in response to the SvP instruction decode signal on line 57, selector L35 selects the first instruction address of the vector array instruction string placed on line 37, and stores it in instruction address register (IAR) M5. and line 5
The signal above 7 is FF.

The set output is input to the vector instruction control circuit (1) C1 via line 36 to instruct the start of execution of vector array processing. After starting the central vector processing unit vPC in this way,
The scalar processing unit sp executes instruction S3 (FIG. 11). (Instruction S3) This instruction is a TVP instruction.

The TVP instruction changes the operating status of the central vector processing unit vPC and vector processing unit PE to FF, F5.
This is an instruction that tests based on the output signal of and sets a condition code. The condition code is set to 1 when the central vector processing unit vPC or vector processing unit PE is in operation, and 0 otherwise. The condition code is.

Manual published by IBM SystemStem/37
0PrincipleSof 0operation (
G C-22-7000) J is used for conditional branch instructions, and when condition code l, TV
The P instruction and the conditional branch instruction are repeated, and when the condition code becomes 0, execution moves to the first scalar instruction.

Next, the operations of the central vector processing unit VPC (FIG. 8) and vector processing unit PE1 (FIG. 9) will be explained.

When the vector command control circuit (1) C1 of the central vector processing unit vPC is activated.

The instruction is sent to the main memory control unit C52 via the instruction address line 71 set in the instruction address register M5, and based on this address, the first instruction of the vector array instruction string in the main memory C51 is read out. Main memory control unit I" C52 and instruction register M1 via line 63.
is set to

In the example of FIG. 11(a), the first vector array instruction v1 is set in register M1.

When an instruction is set in register M1, its fields M71-M73 . M75. M76°M78. Instruction code OP for each M79.

AI, Vl bit, A2. The V2 bit and the A3°3 bit are input via line 1 to the vector instruction control circuit (1), C1. The circuit C1 controls the vector arithmetic unit C3 and other circuits based on the instruction code OP, and controls At, Vl, A
2. V2. Based on the A3°■3 bits, reads and writes to the scalar register SC and vector register VC. Note that the number of the scalar register SC1 or vector register ■C1 to which writing is to be performed is determined by the selector L24, which will be described later.
and from AND gate L14, respectively.

Also, Kono instruction (7) At, Vx, A2. The A3 bit is further connected to the OR gate L via lines 2, 3, and 4.6, respectively.
4. AND gate L8. The vector array instruction is input to a circuit consisting of F9°LIO and Lll, and as a result, the vector array instruction is classified into four, and one of the corresponding FFs, Fl-F4, is set. FF.

Fl is an array instruction, and the operation result is stored in array register A.
It is set by an instruction to write to R, that is, A1=1, FF and F2 are array instructions, and an instruction to write the operation result to vector register VR, that is, 80=0.
and set by an instruction with A2 or A3 = 1, and the FF
, F3 is a vector instruction and an instruction to write the operation result to the vector register VR, that is, "A" A 2 =
Set by the instruction A 3 = 01vt=i,
FF and F4 are vector instructions and instructions to write the operation result to the scalar register SR, that is, A l =A 2
=A 3=O, V, =O is set by the command.

Further, in order to send the register number specified by the instruction to the corresponding register of the central vector processing unit vPC, the instruction (7) V t (M 73), V 2 (M 76
) + V a (M79) FiJL/do and register numbers R1 (M74), R2 (M77), R3' (M2
O) are lines 3, 5.7 and 14°15.16 respectively
via AND gate L13. R14゜R15, R16
, R17, and R18.

AND gate L13. R15 and R17 are R1, respectively
When R2 or R3 is the number of the scalar register SC, that is, when Vl, V2 or v3 are 0, the line 22
．． 24 or 26 and outputs register number R1, R2 or R3 on AND gate L14. R16, R18 are respectively Vl, V2 . When V3 is 1, register numbers R1 and R1 are placed on lines 23 and 25.27, respectively.
Output R2 and R3.

Below, vector array instruction vt-vtt (Figure 11)
Explain. Instruction v1 has vector length AL(J), instruction v
2-v5 are 7L/ideta A, B.

Each start address of C A A D RA (J) ~ A
ADRc (J), instruction v6 is array data A.

An address increment value INCA (J) common to B and C is calculated. The above is the setup using Pectro processing. Array data B with instructions v7 to v8.

C is read from the main memory device C51, array data B and C are added with an instruction v9, and the operation result is written into the main memory device C51 with an instruction vlO. Vector
Notifies that the array instruction sequence has ended. In addition, the instruction V
Conceptual scalar register SR1~ specified by l-V6
As already mentioned, the necessary scalar data is set in the scalar registers SCI to SCI-6 that implement 6.

In addition, registers 1 to M of the vector register VC that embody the conceptual vector register VR2 and scalar registers S12 to M of the vector processing units PE1 to PEM
0 for SM2. (2) Assume that constant vectors of M-1, . . . , are stored in advance. (Instruction Vt) Since the instruction Vl is a vector instruction that writes to the conceptual vector register VRI, FF and F3 are set to 1-,
On lines 23, 25, and 26 are register numbers # 1 u,
II 21+ and 1157+ are respectively set.

The selector L27 selects the contents of the scalar registers designated by the register numbers input from the lines 22, 24, 26, respectively, to the selectors L3, 1, 32, . It is designed to be output to R31.

In this case, the contents of the scalar register SC6 ``'2'''' are output to the selector L31.The selector L28 is connected to the line 23,
25. The vector registers specified by the register numbers input from 27 are selected respectively, and the respective selectors L3. It is designed to connect to L32°R31. In this case.

Beta register vC2 is selected and selector L32
connected to. Selector L31 selects reselector L27 depending on whether bit v2 of the instruction input via line 5 is 0 or 1.
Or select the output of R28.

Selectors 1 and 32 select the output of selector L27 or L28 depending on whether bit v3 of the instruction input via line 7 is 0 or 1. In this case, note that V2=1°v3=0, -t! Rector L32. R31 respectively selector L27. L28 is selected. Therefore, the outputs of the scalar register SC6 and vector register VC2 are input to the vector arithmetic unit C3.

The instruction Vl is an instruction to add the constant 2 in the square register SR6 and the vector consisting of the constants 0 to M-1 in the vector register VR2, and store the vector consisting of the constants 2 to M+1 in the vector register VRI. . This result vector represents the vector length AL (J) processed in the inner Do loop.

The vector instruction control circuit (1) CI decodes the instruction code OP and controls its execution.

In the case of the ADD instruction, it commands the vector register VC and scalar register SC to read one element at a time,
And the vector calculator C3 is activated.

Vector arithmetic unit C3 performs addition in a well-known pipeline mode for each element of constant 2 input from scalar register SC2 and constant vector input from vector register VC2, and obtains a vector consisting of constants 2 to M+1. The vector command control circuit H)ct sends a store command to the scalar register SC or vector register VR designated by the command as soon as the result of the beta 1-al operation is output on the line 54. Selector L24. L25 selects the write scalar register number (line 22) and data C line 54) designated by the vector instruction when the output of FF and F5 on line 36 is 11171, respectively. In addition, the selector L40 controls the vector instruction control circuit (
1) The signal issued by CI (line 55) causes line 7 to
7, otherwise select line 54. Therefore, in the case of the ADD instruction, selector L40 selects 5 on the line.
4 is selected and read out on line 44. Further, the selector L30 is selected by the signal on the line 19 indicating whether or not the signal line 55 and FF and F2 are set. If FF and F2 are set, line 45
When the data on the line 43 is a LOAD command, the data on the line 44 is selected, and in other cases, the data on the line 44 is selected. Therefore, in this case, the operation result vector on line 44 is selected and input to the vector register vC1 of the write register number on line 23 by multiplexer L29, and each element of the operation result vector is stored in sequence.

The calculation for a certain element i of vector data and the storage of the calculation result for the previous element (i-1) are performed in parallel.

Furthermore, in an instruction in which II"F and F3 are set, the same operation result is applied to both the vector register VC2 that realizes the same conceptual vector register VR2 and the scalar registers S and 2 to SM2 in the vector processing units PE1 to PEM. Therefore, it is necessary to send the calculation results on line 44 to each vector processing unit PE1 to PEM in order.
F.

When F3 is set, its output is sent via line 20 to the calculation result sending signal circuit C4. The calculation result sending signal circuit C4 has a counter (not shown) and a decoder (not shown). , and sends a sending signal to one of the signal lines 521 to 52M connected to each of the vector processing units PE1 to PEM, which corresponds to this count value. Also V L R
Vector length ■L set in register M4 is line 5
0, and compares it with the count value to determine the completion of the calculation. If the calculation is completed, the data is read from FF and F via the line 48.
Reset 3. During this time, the calculation result is sent to selector L40.
from the line 44 to the flat processing units PE1 to P
Sent to EM. Further, the outputs of FF and F3 are sent via line 20 to vector processing units PE1 to PEM.

Instructs to import data on m44. Further, write register numbers 1 to 1 are sent from line 23 to these units.

On the other hand, in each vector processing unit PE1 (FIG. 9),
Select 1 by output signal 1 of FF, F3 on line 20
08 selects the data on line 44, and selector L107 selects the register number (number 1 in this case) on line 23 from the central solid processing unit vPC. The scalar register Sl of this number is selected by multiplexer L109.
The data on the line 44 is input to 1, and is stored when the calculation result sending signal is input from the line 52□. Thus, the processing of instruction v1 ends.

Further, the calculation result sending circuit C4 outputs FF.

When F3 is reset, the output of NOR gate L21 to which the output signals of FF and Fl to F4 are input becomes 1,
This output is transmitted via line 32 to the vector instruction control circuit (1).
Input to CI. When a vector array instruction is executed, one of the FFs, Fl to F4, is set, and when the operation is completed, the FFs set from Sera1 to F4 are reset, so when the operation is completed, the signal on line 32 is n. 171
becomes.

The vector instruction control circuit (1) C1, in synchronization with this G number, stores the next instruction address given from the +1 addition circuit C6 via the selector L35 into the instruction address register M5. This set next instruction address is
The next vector array instruction is sent to the main memory controller C52 via line 71 from the main memory controller C51.
Sera 1~ are stored in the array instruction register M1. (Instruction V2
~V6) Instructions v2 to v6 use the same type of register as instruction v1, and FF and F3 are set to cell l-, and instruction v1
is processed in the same way. Here, the instruction code M of instruction v2
ULT means multiplication, and instruction code MOVE of instruction v6 means transfer. Note that the MOVE instruction does not have the R3 field M80. Instruction v2 includes the outer loop processing address increment value INCV stored in scalar register SR4 (i.e., scalar register 5C4), and constants stored in vector register VR2, that is, vector register VC2 and scalar register group 8□2 to SM2. Find the product of vectors 0 to M-1 and set the vector register VR
3 (ie, vector register VC3 and scalar registers 313 to 5M3). moreover,
Instruction 3 writes the sum of the start address VADR of array data A stored in scalar register SRI and vector data O~(M-1)XINCV stored in vector register VR3 by instruction v2 to vector register VR4. This is an instruction to store. Therefore, 5-vector register VR4 contains column vector A of array data A for different J, which is processed in the inner loop by instruction v3.
First element A of (I, J) (I=1 to J+1) (1, J
) is stored.

Instruction v4 reads array data B in scalar register SR2.
instruction v3 using the start address VADRn (J) of
Similarly, the address A A D Re of the first element B (1, J) of the column vector B (I, J) (I=l-J+1) processed in the inner loop of array data B
(J) is stored in vector register VR5.

Similarly, instruction v5 stores a vector consisting of start addresses A A D Rc (J) for different J of array data C in vector register VR6.

Instruction v6 is an instruction for writing the address increment value INCV, which is common to array data A, B, and C in scalar register SR5, into each element register of vector register VR7 as it is. This instruction passes the increment value INCV in the scalar register SC5 through the vector arithmetic unit C3 to the vector register VC7 and the scalar registers 817 to 817.
This is executed by writing to sM7. In this way, the beta 1-ball, each element of which is equal to the address increment value INCV, is stored in the beta 1-ball register VR7.

(Instruction V7) This instruction sets each element of the vector with the start address AAD Rn (J) in the vector register VR5 as the start address, and each element of the vector with the increment value INCV in the vector register VR7 as the increment value. This is an instruction to refetch a plurality of vector data from the main memory C51 and store it in the array register ARI.

When instruction v7 is set in instruction register Ml.

FF and Fl are activated. FF on line 18.

The output signal of F"1 is input to L22 to Or(gate 1), and its output is connected to the vector instruction control circuit (
1) Input to C1 and the vector instruction control circuit of each vector processing unit PE1 (2) C1ot (FIG. 9).

The outputs of the FFs, Fl to F2 are input to the OR gate L22, and the output becomes rt I IF in the case of an array command. Vector command control circuit (1) C1 receives signal B' manually through R30.

Stop decoding. In addition, the vector instruction control circuit (2
) C1ot is when the signal B' is inputted via line 30,
The array instruction on line 63 is stored in the array instruction register MIO.
Set I to Sera 1.

Field M1 of the instruction set in register MIOI
71~M+73, M175, MI7
6.

The command codes in R178 and M79 are OP,
At, Vl, A2. V2. A3. V3 is input via line 102 to vector instruction control circuit (2) Cl0I.

The circuit C101 controls the vector arithmetic unit ClO3 and other circuits based on the instruction code ○P to execute instructions, and also executes the instructions in the scan registers S1. Write to vector register Vi.

Control reading. Note that the number j of the scalar register SiJ or vector register Vi,+ to which writing is to be performed
are selector L107 and AND gate ■, 10 respectively.
Given from 2.

A to send the register numbers R1 to R3 specified by the instruction to the corresponding registers of the vector processing unit PE.
Engineering, A2. A3 field and register number R1 (M17
4), R2 (M177).

R3 (M2B5) connects AND gates LIOI, LiO2, LiO2°LiO2, Li2S,
It is input to L106.

AND gates LLOL, LiO2, and Li2S have register numbers R1, R2, and R3, respectively, as vector registers VR.
, that is, A1=O, A2=, respectively.
When O, A3=O, register numbers R1, R2, and R3 are sent to lines 109, 111, and 113, respectively. AN
D gate L102. LiO2 and LloG are each R1
゜When R2 and R3 are for array registers, that is, AI=1. When Δ2=l and A3=1, register numbers R1 and R are applied to lines 110, 112, and 114, respectively.
2, output R3. In the case of instruction ■7, lines 110, 11
On 1,113 is register number 1111, LI5
H, 11711 are respectively set to Sera 1~.

When instruction v7 is decoded, vector instruction control circuit (2)
C1ot is the i-th element A of the vector length AL in the first scalar register Sll input by line 163.
Applying L (i) to the vector reference control circuit ClO2,
Start this. 5. A scalar register S in which the i-th element of the array address A D D Rn (i) specified by this instruction and the increment value INCA are stored, respectively; Numbers 5 and 7 of Si7 are lines 111.11 respectively
3 to the selector L110, and the selector LI
IO connects AADRo(i) and INCA to line 115 respectively.
．． liG to the read vector reference control circuit ClO2.

The start address A AD Re (i) and the increment rNVA (i) of array data B are equal to B (1, i) and 8, respectively. Based on these read data, the circuit ClO2 reads the i-th column of array data B. To read the vector i+1), start address AADRu (
generates an address in which the i-th element of i) is sequentially updated by an increment value INCA, and sends it via line 130□ to SCU,
Input C 5 2 sequentially.

As a result, the elements of the i-th column vector of array data B are sequentially read out on line 1191. - direction, line 119
□The read data above is selected by the selector L113 with the L O A D instruction decode signal on the line 120 from the vector instruction control circuit (2) C101, and is sent to the line 110.
The selector 112 controlled by the write register number located above selects the first solid register Vi.
1. When the data of the required vector length AL (i) is read and the operation is completed, the vector instruction control circuit (2) CIOI reports it to the central vector processing unit vPC via the line 61t. The above processing is performed in parallel by each vector processing unit l-PEi, and all necessary column vectors of array data B are stored in array register ARI.

On the other hand, in the central vector processing unit vPC.

The completion report is sent to FF via line 61-61M.

It is received from F6t to F6M (Fig. 8). Then, the output is input to the AND gate 1.88, and when all the vector processing units PE have completed their calculations, the signal 11 1
Output I+ on line 56. As in the case of this command,
When FF and Fl are set to 1~, AND gate L
23, FF and Fl are reset via line 34.

Further, FF, F6z to F6M are decoded via line 62 by solid 1 hell instruction control circuit (1) CI at the time of next instruction decoding.

(Instructions v8 to v10) Instructions v8 to v10 are also FFs like instruction v7.

This is an instruction to which Fl is set, and is executed by the vector processing unit PEi.

By instruction v8, main memory C is stored in array register AR2.
Array data C on 51 is stored.

The processing of ADD instruction (2) 9 is performed as follows.

In the vector processing unit l-P E l, the line 112°1
14 and AND gate L104. Register number 1.2 is output from LiO2, and vector registers vi t, V, and 2 are set to selector L115 by selector Lllll.
．． Connected to LI14. Selector Ll 15. Ll
14 are connected to the instruction register M on lines 107 and 105, respectively.
A3. output from 101. Selector L 111 is selected when the A2 bit is 1. Thus, vector registers V, 1 . Vi2 is connected to vector operator ClO3.

Vector instruction control circuit (2) CIOI responds to the instruction code of instruction v9 by registering vector register V1 e V
12 to i-th column vector B of array data B, C
(1,i)~R(i+1+i) and C(1,i)~C
(i+L, i) is read out one element at a time.

The vector arithmetic unit ClO3 performs an operation specified by an instruction on each element of input data under the control of a vector instruction control circuit (2) ctol in a known pipeline mode. In the case of instruction v9, addition is performed and the i-th column vector A(1,i) to A(i+l
, i) are sequentially output. The calculation result is sent via line 117 to selector LL13. It is input to L108. Selector L1
13. For L10B, the signals on lines 20 and 120 are 0, respectively.
Therefore, line 117 is selected together.

However, the register number is not input from the selector 107 to the multiplexer 109 to which the output of the selector 108 is input. Selector L107 is Antogame-1-L
101 is selected, but from AND gate L101,
This is because the A1 bit of instruction v9 is 1, so the register number is not output.

On the other hand, register number 3 is inputted from the AND gate L102 to the multiplexer L112 to which the output of the selector LL13 is inputted. Thus, vector register V t
The calculation result is transferred to vector instruction control circuit (2).
Stored under control of C1ot.

In this way, the i-th column vectors 1 to A(1,i) to A(i+l,t) of array data A are stored in vector register V3.
is stored. Solid 1~le processing unit PE1~PE
Since M executes this process in parallel, array data A is stored in array register AR3.

5 When the TORE instruction VIO is executed, the R of this instruction is
2. The start address AADRA of the i-th column vector of array data A specified in the R3 field and the increment value IN
Scalar register with CA S > 4 r S > 7
The contents of are selected by selector L110 and input to vector reference control circuit ClO2.

Vector instruction control circuit (2) CIOI receives the i-th element A(i) of vector length vector 1-AL in scalar register S1, and further sends it to vector reference control circuit ClO2. , launch this. circuit ClO
2 stores the il-th column vectors A(1,i) to A(i+1) of array data A on the main memory C51 from these data.
．． Addresses to store each element of i) are sequentially generated and sent to the SCU, C52 via line 130□. Also, the i-th column vector A(i, i
)~A (i+l,i) is stored in the selector L register V□3 that responds to this instruction R1 field.
Ill and the selector L130 responsive to the At field of this instruction, these data are sequentially read out onto the line 1181 one element at a time, and are stored in the main memory C51 based on the address output from the vector reference control circuit ClO2. is read.

(Instruction V11) The EAP instruction Vll is an instruction that does not have R1, R2, R37, or r-old, but only has instruction codes OP and M71. When this instruction is set in the vector array instruction register Ml, the vector instruction control circuit (1) CI
8, it resets the FF, F5, and notifies the scalar processing unit SP that the vector array processing has ended.

This concludes the explanation of the operation using the program shown in Figure 11, but FF, F2, or F
The instruction to set 4 will be explained below.

FIG. 12(a) shows an example program and part of the latter half of its vector array instruction sequence.

(Instruction VIOI) Since the instruction VIOI is an instruction to store the operation result in the vector register VR, FF and F2 are set, and FF and F2 are set.
By the signal on gland 30 from or gate L22, as if l were set.

The array instruction on line 63 is set in instruction register MIOI of vector processing unit PE.

Instruction control unit I-(2) C1ot is instruction code section OP
, decipher M171. The PROD instruction means an inner product instruction.

In each vector processing unit PE, the first column vectors A(1,i) to A(N,i
) and B (1, i) to R (N, i) is taken and the result S (i) is stored in the scalar register 3.3.

Then, a report on the completion of the calculation is sent to the central vector processing unit tv.
The vector command control circuit (2) ctot performs the command for pc via the line 61t. Further, the operation result S (+) is also stored in the vector register VC3 in the central vector processing unit PC as follows.

When FF and F2 are set, their outputs are sent via line 19 to the calculation result sending request circuit C5.

Details of circuit C5 are shown in FIG. Referring to FIG. 10, first, when setting FF and F2, the output line 19
FF, F2011~F201M, FF, F202
□ to F202M are reset. The FF is activated by the operation end signal on line 611 from each vector processing unit PE1.
.

FjOlt is set. FF, F202□ sends a request signal to the vector processing unit PEl to the encoder C20 via the line 2021 when the encoder C201 outputs the calculation result sending request signal on I@51l as described below.
It is set by the signal output from 1. FF, F2
01, output and FF.

The inverted signal of the output of F202t and the output of FF2021-0 are connected to lines 2041, 203. .

2031-1 through AND gate L300. and its output is input to encoder C201 through line 2011. When the encoder C201 receives the signal 1, it outputs a calculation result sending request to the line 511.

As a result, the encoder C201 can send a calculation result sending request from the vector sequential processing units PE to PEM via the lines 51□ to 51M, respectively. At this time, this request to the processing units 1-PE1 is not sent until after the calculations in the processing units I-PE are completed. Then, the encoder C201 compares the vector length VL of the VLR register M4 inputted via the line 50 with the number of transmission requests, and after all the transmission requests are completed, the encoder
FF and F2 are reset via 9.

On the other hand, the vector processing unit PE engineer calculates the calculation result S (
i) is set to FF and FIOI under the control of the vector instruction control circuit (2) and C101, and the line 51. When a transmission request signal is sent via the AND gate L116, the calculation result is outputted to the line 47.

Further, the central vector processing unit vPC sends the data sent from each vector processing unit PE□ via the lines 471 to 47M to the selector L30 via the line 45 via the OR game L33.

Selector L30 selects line 45 by the output of FF, F2, and multiplexer L29 selects write vector register number 3 input from AND gate L14 via line 23.
writes to the i element port of the flat register VC3.

(Instructions v102 to V103) Instruction V102. V103 is the previously mentioned LOAD, A
Both are DD commands, which set 4:FF and F3.

In the central processing unit vPC, the LOAD command v
102, the start address VADR and address increment value INCV of the vector D are read out onto lines 39 and 38 from the scalar registers SCI and SC2 specified by the R2 and R3 fields, respectively, and input to the vector reference control circuit C2. . Based on these data, the circuit C2 reads out the storage addresses of elements D(1) to D(M) of the vector length V specified by the vector length register M4 among the elements of the vector D. Through gland 64,
Sequentially input to SCU and C52. As a result, the vector elements D (1) to D (M) are sequentially read out on the line 43, and the It I H signal and the FF are sent from the vector instruction control circuit (1) to the line 55.

Based on the 0'' output of F2 and the register number ``4'' from the AND gate L14, the selector L29°F30 is controlled and stored in the vector 1 register VC4.

Instruction 103 performs addition between data 5(1) to S(M) in vector register VC3 and data D(1) to D(M) in vector register VC4, resulting in C.
(t) to C(M) are written to vector register VC5.

FIG. 12 shows an example of a program including an instruction to set FF and F4, and an instruction for executing the program.

(Instruction V104) Instruction Vl 04 is an example of an instruction to set FF and F4.

Here, for simplicity, vector registers VR7 and VR
It is assumed that backup data x and y have been stored in 8 and 8 respectively. Instruction v104 is an instruction to obtain the inner product S of these vector data and write it to the scalar register SR7.

When this instruction Vl 04 is set in the instruction register Ml, the vector register VC7 and VO2 are set in the vector operator C3 under the control of the vector instruction control circuit (1) and C1.
Day 9X (1) ~X (M) ToY (+) ~Y
The inner product of (M) is calculated and the result S is sent to the selector r-25
, scalar register SC via multiplexer I426
7 is written.

Note that in the above embodiment, the vector processing unit l-
Although we have explained the outer Do loop that performs operations on the same number of elements as the number M of P E 1 to PEM, the outer Do
When the number of calculation elements in the loop is larger than M, solid 1
- processing units PE□ to pr> may be used repeatedly. Furthermore, when the calculation element of the outer Do loop has a value M' smaller than M, the apparent processing units PE1 to P
All EMs are operated, and the processing units PEM' and ~
Control may be performed so that the PEM calculation results are not used.

The array processor shown in the above embodiment has the following effects.

(1) Veg1-array operations are divided into a central vector processing unit that performs vector operations and multiple vector processing units that perform array operations, but by using a configuration in which the vector register and scalar register of each unit are used as interfaces, Not only calculations between array data and array data, backup data and vector data,
Array data and vector data, vector! - Operations on scalar data and scalar data can be processed at high speed.

(2) Because a vector processor with vector registers is used for array processing, intermediate values of calculations can be kept in vector registers, reducing the load on main memory, which is the bottleneck of conventional parallel processing. .

(3) Since each of the plurality of vector processing units for array calculations is provided with a scalar register for specifying the vector length A, array calculations can be performed on arbitrary areas, including rectangular areas.

(4) Since the instruction specifications that define the operation of the array processor of the present invention are divided into an instruction code section that instructs operations and a section that indicates the data format of the operands, a simple decoding circuit for the section that indicates the data format can be used. , combinations of arithmetic data formats such as array data and array data, array data and vector data, etc. can be easily determined.

Furthermore, the same instruction code can be used for different combinations of calculation data formats.

(5) The processor of the vector array calculation section has a hierarchical structure consisting of a central vector processing unit and multiple vector processing units 1-1, so the setup process for multiple vector processing units for array calculation is performed by vector calculation. This will speed up the process. In a configuration without a central vector processing unit, setup processing is performed in a time-series manner by a scalar processing unit, which becomes a major hindrance in terms of performance.

Further, in the above embodiment, for simplicity, the vector register VC□ of the central vector processing unit vPC and the scalar register Sli-3 of the vector processing units PE1 to PEM are
Although the identity of the contents of Mi is guaranteed, register writes that do not need to be transferred to the other unit (for example, creating an intermediate value) can be controlled so that no transfer is performed, or register numbers that do not transfer can be set. This can be easily achieved by making a decision.

As described above, according to the present invention, relay calculations can be executed at high speed due to the effect of speeding up vector processing by a vector processor using vector registers and parallelization of the processing.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a FORTRAN program for calculations that are processed in an array, and FIG.
FORTR in Figure 1 in a conventional vector processor
The figure which shows the execution procedure of AN program. FIG. 3 is an overall configuration diagram of an array processor according to the present invention, FIG. 4(a) is an explanatory diagram of registers used in the array processor of FIG. 3, and FIGS. 4(b) to (d) are conceptual diagrams. 5 is a diagram showing the format of a vector instruction or an array instruction for operating the array processor of FIG. 3, and FIG. 6 is a diagram showing the format of the instruction of FIG. 5. 7 is a diagram showing different usage examples of instructions in the device of FIG. 3, and FIG. 8 is a diagram showing the configuration of the central vector processing unit used in the device of FIG. 3. 9 are diagrams showing the configuration of a vector processing unit used in the apparatus of FIG. 3,
FIG. 10 is a diagram showing the configuration of the arithmetic result sending request circuit used in the device of FIG. 3, and FIG.
An example of an ORTRAN program and its vector
A diagram showing the array instruction sequence, FIG. 12, is the FO of array processing.
FIG. 13 is a diagram showing another example of the RT"RAN program and a corresponding example of a vector array instruction sequence, and FIG. 13 is a diagram showing the arrangement of array data on the memory. DOZOI = 7.N A (1, J) = 6 (r, :J) t C (I,
'f) 20 C0NTI7JuE 1o ONT/HUE 2nd Prisoner 2nd Evening Prisoner Figure 7 7th (L:L) (b) -f)0 7θ J=7. Fl (ko) (d-9'E)0 70, f-7,? −4 X(J)=γ(,T)6S )4υLT
VB2. VB25; R77θ C0NT/NU and 77th (L) (b) Scarano'Iklli tri 7tor array supplement 9 or multi IJ 72nd (ku) (b) DO70J MeIJ bar 5 = SfX (J) ”Y(J)
PROD SK'7. l/R7, VRI~V
llf170 CO? J7'/h/L/E No. 3 B

Claims (1)

[Claims] 1. A first means for obtaining one-dimensional array data or scalar data by executing a vector instruction that instructs an operation on one-dimensional array data; and an array that instructs an operation on two-dimensional array data. a plurality of second means for executing the instruction, each of which executes an operation instructed by the array instruction on one one-dimensional array data constituting the two-dimensional array data; When the command requests one-dimensional array data as result data, one element of the resultant one-dimensional array data is obtained, and when the array instruction requests two-dimensional array data as result data, it obtains one element of the resultant one-dimensional array data. The first means includes a plurality of first vector registers, a plurality of first scalar registers, and a first pipe. a line arithmetic unit, a means for fetching a vector instruction or an array instruction, a means for decoding whether the fetched instruction is a vector instruction or an array instruction, and when the decoded instruction is a vector instruction, the first vector register and the first means for controlling the scalar register and the first pipeline arithmetic unit to execute the decoded vector instruction; and when the operation result of the fetched vector instruction is one-dimensional array data, the one-dimensional array data is means for sending each element to a corresponding one of the plurality of second means, and storing the element of the one-dimensional array data calculated by each of the plurality of means in one of the first vector registers; each of the second means comprises a plurality of second vector registers, a plurality of second scalar registers, a second pipeline arithmetic unit, and an array in which the fetched instructions are arranged. At the time of the instruction, the second vector register, the second scalar register, and the second pipeline arithmetic unit are controlled to fetch one dimension of the two-dimensional array data specified by the fetched instruction. means for executing the fetched array instruction on array data; and when the execution result data is one element of one-dimensional array data, means for sending the one element to the first means; means for storing one of the elements sent by the first means into one of the second scalar registers. 2. A main memory that stores scalar data, vector data, and array data, and stores scalar instruction sequences and vector/array instruction sequences separately; scalar instruction execution means for reading scalar data, decoding and executing the read scalar instruction, and storing the scalar data obtained by the execution in the main storage device; A vector array instruction execution means reads an instruction sequence, vector data, or array data and stores the vector or array data obtained by the execution in the main storage device, and the scalar instruction execution means executes the vector array instruction sequence. an array processor having means for generating data necessary for the scalar instruction in response to the scalar instruction. 3. The vector array instruction execution means reads the vector array instruction from the main memory, and if the vector instruction is distinguished from the array instruction and the vector array instruction is a vector instruction, the vector array instruction is read from the main memory. main vector instruction execution means for reading and executing vector data, and storing vector data obtained by the execution in the main storage device;
If the vector array instruction is an array instruction, a second item comprising array instruction execution means for reading array data from the main memory, executing it, and storing array data obtained by the execution in the main memory. array processor. 4. The array instruction execution means decodes the array instruction as a vector instruction, divides the array data into a plurality of vector data from the main memory, reads them in parallel, executes them in parallel, and reads the array data into a plurality of vector data obtained by the execution. 4. The array processor according to claim 3, comprising a plurality of vector instruction execution means for storing data in parallel as array data in the main memory. 5. The main vector instruction execution means is an array according to item 4, having means for transferring data necessary for execution of the plurality of vector instruction execution means and vector data necessary for the array instruction to the plurality of instruction execution means. processor. 6. The array processor according to item 3, wherein the plurality of vector instruction execution means includes means for transferring vector data necessary for vector instruction execution performed by the main vector instruction execution means to the main vector instruction execution means. 7. Each vector instruction execution means constituting the array instruction execution means transfers the length of the vector to be processed independently by each vector instruction execution means and the vector data on the main memory to be processed, which is transferred by the transfer means. 4. The array processor according to item 4, having means for holding a start address and an address increment value of the vector data, and for use in control.