JPS63118595U - - Google Patents

Info

Publication number
JPS63118595U
JPS63118595U JP923387U JP923387U JPS63118595U JP S63118595 U JPS63118595 U JP S63118595U JP 923387 U JP923387 U JP 923387U JP 923387 U JP923387 U JP 923387U JP S63118595 U JPS63118595 U JP S63118595U
Authority
JP
Japan
Prior art keywords
display
data storage
control means
display control
displays
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP923387U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP923387U priority Critical patent/JPS63118595U/ja
Publication of JPS63118595U publication Critical patent/JPS63118595U/ja
Pending legal-status Critical Current

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  • Electric Clocks (AREA)
  • Calculators And Similar Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案の一実施例のブロツク回路図
、第2図は、第1図におけるRAMの主要構成を
示す図、第3図は上記実施例の動作を示すフロー
チヤート、第4図は、第3図のフローチヤートに
おける読出し処理を詳細に示すフローチヤート、
第5図は、上記実施例におけるモードおよび表示
の変遷を示す図である。 1……ROM、2……アドレス制御部、3……
RAM、4……インストラクシヨンデコーダ、5
……演算部、6……ラツチ部、7……発振回路、
8……タイミングジエネレータ、9……キー入力
部、10……分周回路、11……表示部、12…
…ブザー回路、T……計時レジスタ、DS……表
示バツフア、MD……電話データ記憶領域、MF
……表示済フラグエリア、MN……氏名エリア、
MT……電話番号エリア。
FIG. 1 is a block circuit diagram of an embodiment of the present invention, FIG. 2 is a diagram showing the main configuration of the RAM in FIG. 1, FIG. 3 is a flowchart showing the operation of the above embodiment, and FIG. 4 is a flowchart showing details of the read processing in the flowchart of FIG. 3;
FIG. 5 is a diagram showing changes in modes and displays in the above embodiment. 1...ROM, 2...address control section, 3...
RAM, 4...Instruction decoder, 5
... Arithmetic section, 6... Latch section, 7... Oscillation circuit,
8... Timing generator, 9... Key input section, 10... Frequency dividing circuit, 11... Display section, 12...
...Buzzer circuit, T...Time register, DS...Display buffer, MD...Telephone data storage area, MF
...Displayed flag area, MN...Name area,
MT...Telephone number area.

Claims (1)

【実用新案登録請求の範囲】 少なくとも電話番号を記憶させることができる
データ記憶手段と、 表示手段と、 上記データ記憶手段に記憶されているデータを
一定の順序で、順次、一定時間ずつ上記表示手段
に表示していく第1表示制御手段と、 キー操作により動作し、該操作時に、上記第1
表示制御手段により上記表示手段に表示されてい
るデータを該表示手段に固定表示せしめる第2表
示制御手段とを備えていることを特徴とするデー
タ記憶機能付電子時計。
[Scope of Claim for Utility Model Registration] A data storage means capable of storing at least a telephone number, a display means, and the display means which sequentially displays data stored in the data storage means in a certain order for a certain period of time. a first display control means that displays a display on the first display;
An electronic timepiece with a data storage function, comprising: second display control means for causing data displayed on the display means to be fixedly displayed on the display means by the display control means.
JP923387U 1987-01-27 1987-01-27 Pending JPS63118595U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP923387U JPS63118595U (en) 1987-01-27 1987-01-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP923387U JPS63118595U (en) 1987-01-27 1987-01-27

Publications (1)

Publication Number Publication Date
JPS63118595U true JPS63118595U (en) 1988-08-01

Family

ID=30794356

Family Applications (1)

Application Number Title Priority Date Filing Date
JP923387U Pending JPS63118595U (en) 1987-01-27 1987-01-27

Country Status (1)

Country Link
JP (1) JPS63118595U (en)

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