JPS6311770Y2 - - Google Patents

Description

[Detailed explanation of the invention] This invention uses a local oscillation circuit as a phase-locked loop PLL.
Concerning a receiver that is configured with and that performs electronic tuning,
In particular, the purpose is to improve muting circuits. A receiver in which the local oscillation circuit is configured with a PLL is generally configured as shown in FIG. Tuning is performed by generating a predetermined local oscillation frequency fo from the oscillator 4, and by setting the oscillation frequency of the reference frequency oscillator 5 to the inter-station frequency, the local oscillation frequency can be adjusted.
fo is obtained by interstation frequency steps, and channel selection is performed digitally. By the way, in such a PLL 1 , when the frequency division ratio N of the programmable frequency divider 2 is changed and a new frequency is generated from the voltage controlled oscillator 4, the second
After passing through the transient response state shown in the figure, PLL 1
is locked and a new frequency is stably generated. However, from the point of view of shortening the channel selection time, it is better to shorten the transient response time, and the transient response time depends on the time constant of the reduction filter 6. Therefore, if the time constant of the reducing filter 6 is made small to shorten the transient response time, the stability when the PLL 1 is locked will deteriorate, and the receiving performance will be deteriorated, which is not preferable. Therefore, conventionally, as shown in Fig. 3, the time constant of the reduction filter 6 is made small to shorten the transient response time until PLL 1 is locked, and when PLL 1 is locked, the reduction filter 6 is activated upon lock detection. The time constant of the reduction filter 6 is switched to increase the time constant of the filter 6. In addition, during the period when PLL 1 is not locked, that is, in the transient response state, broadcasting is not received, so a muting circuit 8 is provided to cut off the audio path to prevent noise from being generated from the speaker 7 during this period. It is configured to release muting upon lock detection. Therefore, it has been found that if the time constant of the reduction filter 6 is switched and the muting is canceled at the same time when the PLL 1 locks as described above, a failure occurs due to the time constant switch. In other words, by switching the time constant, PLL 1 is unlocked.
The output voltage of the reduction filter 6 fluctuates, and a small second transient response _T2 occurs as shown in FIG. 4, and since muting has already been released at this time, noise during the transient response is generated from the speaker 7. It was hard to hear. Therefore, the present invention has been developed in view of this point, and provides a receiver characterized in that mutating is canceled after the time constant of the reduction filter is switched, thereby eliminating the disturbance accompanying the time constant switching. It is something. Hereinafter, embodiments of the present invention will be described based on the drawings. Note that the same components as in FIG. 1 are indicated by the same symbols. Figure 5 is a diagram showing the main parts of the receiver of the present invention.
is a well-known digital phase comparator to which the divided output fv of the voltage controlled oscillator 4 and the reference frequency fs of the reference frequency oscillator 5 are applied to the inputs, and output signals corresponding to the phase difference of the input signals are generated at the outputs U and D. So, PLL 1
When the lock is locked, both outputs go to H level, and when the lock is released, one output goes to L level. 10 receives the output of the phase comparator 9 as an input, and operates a reduction filter 6 according to the output of the phase comparator 9.
This is a charge pump whose output is connected to a reduction filter 6 to control it, and is composed of C-MOS.
The reduction filter 6 is configured as an active type, and the PLL
A relay contact 11 is provided so that the time constant can be changed depending on whether the lock is locked or not, and the output is led to the voltage controlled oscillator 4. 12 is PLL 1
This lock detection circuit consists of a NAND gate 13 that receives the output of the phase comparator 9 as an input, an integrating circuit 14, and a transistor 15 whose conduction is controlled by the output of the integrating circuit 14, and the PLL 1 is unlocked. When one of the outputs U and D of the phase comparator 9 becomes L level, the output of the NAND gate 13 becomes H level and the transistor 15 becomes conductive, and the collector is at L level, but PLL 1 is locked and the phase comparison is performed. When the outputs U and D of the device 9 both go to H level, the output of the NAND gate 13 goes to L level, so that the transistor 15 becomes non-conductive and generates an H level lock signal at the collector. 16
1 is a one-shot multivibrator that operates on the rising edge of a lock signal and generates a lock pulse.
7 is set by the rising edge of the output of the one-shot multivibrator 16, and the channel selection start key 1 is pressed.
Flip-flop 19 reset by operation 8
The time constant switching circuit is composed of a relay 21 which is excited by the conduction of the transistor 20 by the set output Q, and the relay contact 11 of the reduction filter 6 is switched by the relay 21 being excited. Reference numeral 22 denotes a muting control circuit, to whose set terminal the tuning start key 18 is connected, and to its reset terminal the output of an AND gate 22 whose two inputs are the Q output of the flip-flop 19 and the output of the one-shot multivibrator 16. The set output Q is applied to the muting circuit 8 as a muting signal. Next, the operation of the present invention having such a configuration will be explained. When receiving another station from the station currently being received, the currently broadcasting station is selected by sequentially changing the value of the frequency division ratio setting means 3 by 1 by operating the selection start key 18. First, from the receiving state, press the channel selection start key 1
8 to change the value of division ratio setting means 3 from N to N+1.
We will explain in case the changes have been made. When the channel selection start key 18 is operated and a start pulse is generated, the value of the frequency division ratio setting means 3 is changed, and at the same time the programmable frequency divider 2
The frequency division ratio N of is changed and PLL 1 is operated, but
At this time, by operating the tuning start key 18, the flip-flop 19 of the time constant switching circuit 17 is reset, and the flip-flop 2 of the muting control circuit 22 is reset.
4 is set, the relay 21, which was energized in the receiving state, is demagnetized, the relay contact 11 is opened, the time constant of the reduction filter 6 is switched to a smaller value, and a muting signal is generated, cutting off the audio path. do. When PLL 1 is locked after passing through a transient response state, both outputs U and D of phase comparator 9 become H level, and a lock signal is generated from lock detection circuit 12 and output from one-shot multivibrator 16. When the first lock pulse _P1 is generated, the flip-flop 19 of the time constant switching circuit 17 is set in response to the rising edge of this lock pulse, the relay 21 is energized, and the relay contact 11 is closed, thereby reducing the filter 6. Set the time constant to a large value. At this time, due to the change in the time constant, the output of the reduction filter 6 changes somewhat during the transient response [second transient response T ₂ ], as shown in FIG. Then, since the oscillation frequency of the voltage controlled oscillator 4 changes, the PLL 1 becomes unlocked, one output of the digital phase comparator 9 becomes L level, and the output of the lock detection circuit 12 becomes L level. By the way, this second transient response
When T ₂ ends, PLL 1 locks and outputs U and D of phase comparator 9 both go to H level, and NAND
As the output of gate 13 becomes L level,
Transistor 15 becomes non-conductive, and the collector becomes H.
Generates a level lock signal. Therefore, this H
A second lock pulse P ₂ is generated from the one-shot multivibrator 16 based on the level lock signal.
is generated. At this time, the flip-flop 19 is set by the first lock pulse _P1 , the Q output is at H level, and the H level lock signal of the second lock pulse _P2 is applied to the AND gate 22. Therefore, a reset signal is applied from the AND gate 22 to the flip-flop 24. Therefore, the muting signal is canceled, and if a broadcast is being received at this time, it will be reproduced from the speaker 7. In this way, the noise generated during time constant switching is blocked. As mentioned above, the receiver of the present invention uses a local oscillation circuit.
It is configured with a PLL, and is configured so that the time constant of the reducing filter is switched depending on locking and unlocking of the PLL, and the muting is canceled by the second lock pulse generated after switching the time constant, so that the time constant can be switched. This makes it possible to reliably prevent noise from occurring.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the conventional configuration of the receiver according to the present invention, Fig. 2 is an operational waveform diagram of the main part of Fig. 1, Fig. 3 is a block diagram of the main part of Fig. 1, and Fig. 4 is a diagram of the main part of Fig. 1. FIG. 1 is an operational waveform diagram of the main part, FIG. 5 is a configuration diagram of the main part of the present invention, and FIG. 6 is an operational waveform diagram of the main part of FIG. 1 ...PLL, 6...Reducing filter, 9...Phase comparator, 10...Charge pump, 12...Lock detection circuit, 17...Time constant switching circuit, 22...
Muting control circuit.

Claims (1)

[Scope of utility model registration request] In a receiver in which the local oscillation circuit is composed of a PLL (phase locked loop) and the local oscillation frequency is controlled by changing the frequency division ratio, a lock detection means for detecting that the PLL is locked; After the first transient response of the reduction filter constituting the PLL due to a change in frequency ratio is completed, the time constant of the reduction filter constituting the PLL is switched by the first lock detection output from the lock detection means. A time constant switching means and the above-mentioned
After the second transient response of the reduction filter constituting the PLL is completed, a muting control circuit is activated by the second lock detection output from the lock detection means,
A receiver characterized in that noise at the time of switching the time constant is prevented by canceling the muting signal.