JPS63115430A - Communication equipment for correcting coding rate variable error - Google Patents

Abstract

PURPOSE:To apply the titled communication device to the burst mode communication of a TDMA communication system by producing internally an enable signal in accordance with the coding rate and selecting a continuous or intermittent action based on said enable signal. CONSTITUTION:An enable signal generating circuit 35 produces an enable signal 36 from a control signal 4 (PNC) and a data block (DCLK). The signal 36 serves as a DC signal of a low level with a punctured code of R=3/4 and then changes intermittently to a high level from a low level with a code of R=1/2. Then a transmitter 2a and a receiver 10a have continuous or intermittent actions based on the signal 36. Thus this communication device can always work with a fixed clock regardless of the coding rate. Then the working stability of a circuit is never deteriorated and no complicated control mechanism is required either.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a communication device that uses an error correction coding method, and uses a technique such as punctured coding to make the coding rate variable. The present invention relates to a variable coding rate error correction communication device having more functions.

[Prior Art] As a variable coding rate error correction communication device using punctured coding technology, for example, the document “Study on variable coding rate Vitabi decoder and its operation J (Y., Yasu
da, et, al, @DeveA? opment
ofvariaMerate Viterbi dec
order and its performance c
haracteristics”, 6th Int.

Conf,on Dig,Sat,Commun,,P
hoenix, Ar1zona (Sept, 1983)
] is described in detail. Below, the prior art will be explained based on this document.

FIG. 12 is a block diagram showing an example of a conventional coding rate variable error correction communication device, in which coding rate B=l/2 and R=
It is configured to select and perform two types of encoding: 3/4.

In the figure, 1 is input data (IDATA), 2 is a transmitter, 3a and 3b are transmission data in two channels P and Q (TDATAP, TDATAQ), and 4 is a control signal (PNC) for controlling the coding rate. , 5 is the data clock (DCLK), 6 is this data clock s (DCL
The transmission clock (TC) has a speed 2/3 times the speed of
LK), 7 is these data clock 5 (DCLK)
and transmit clock 6 (TCLK), and 8 is a switch that receives the clock (TCLK) selected by this switch 7.
SCLK), 9a, 9b are soft decision data (8DATAP, 5D
ATAQ), 10 is a receiver, and 11 is output data (01)ATA) of this receiver 10.

FIG. 13 is a block diagram showing extracted portions related to the transmitter 2 and switch 7 in FIG. 12.

In FIG. 13, the same numbers as in FIG. 12 indicate corresponding parts, 12 is a transmission buffer, 13 is data (BDATA) output from this transmission buffer 12, 14
15 is an address counter for controlling reading of the transmission buffer 12, and a read address A116 output from the address counter 14 is a variable coding rate encoder connected to the transmission buffer 12.

Figure 14 shows the coding rate variable encoder 1 in Figure 13.
6 is a configuration diagram showing an example of 6.

In FIG. 14, the same parts as in FIG. 13 are given the same reference numerals, and their explanation will be omitted.

In the figure, 17 is a convolutional encoder with R=1/2 code;
18a*18b are the two channels P of this encoder 11,
Coded data (CDATAP) which is the output of Q.

CDATAQ), 19 is coded data 18a,
FIF for 18b (CDATAP, CDATAQ)
O (First In-First Out) Mesori,
20a and 20b are punctured encoded data (PCD) output from two channels P and Q of the FIFO memory 19;
ATAP, PCDATAQ), 21 is encoded data 18
22 is a clock control circuit;
23a123b are write clocks (WCLKP,
WCLKQ).

FIG. 15 is a circuit diagram showing an example of the configuration of the encoder 17 shown in FIG. 14.

In FIG. 15, the same reference numerals as in FIG. 14 indicate corresponding parts, and 24a, 24b, . . . , 24f are delay elements whose delay time is only one period of clock 5 (8CLK);
25a, 25b, . . . , 25h are modulo-2 adders.

FIG. 16 is a configuration diagram showing an example of the clock control circuit 22 of FIG. 14.

In FIG. 16, the same parts as in FIG. 14 are designated by the same reference numerals, and their explanation will be omitted. In the figure, 26 is a counter, 27 is the output of this counter 26, 28 is an erasure pattern generation circuit for punctured encoding, 29a, 29b
is the cancellation path I-y(DP,
DQ), 30a and 30b are the selected clock 8 (SCLK) and erase pattern 29a (DP) and the selected clock 8 (SCLK) and erase pattern 29, respectively.
This is an AND gate that receives b(DQ) as an input.

FIG. 17 is a time chart showing the encoding process using R=172 code, (a) shows the transmission clock (TCLK), (b) shows the data (BDATA), (
c) is encoded data (CDATAP, CDATAQ
), (d) are transmission data (TDATAP, TDATAQ
).

FIG. 18 is a time chart showing the encoding process using R=374 punctured code, in which (a) shows a data block (DCLK), and (b) shows a data block (DCLK).
ATA), (C) is encoded data p (CDATAP.

CDATAQ), (d) is erased butter y (DP, DQ)
, (e) are write clocks (WCLKP, WCLKQ
), (f) shows the transmission clock (TCLK), and (g) shows the transmission data (TDATAP, TDATAQ).

FIG. 19 is a time chart showing the operation of the clock control circuit 22 in FIG. 14, and (a) is a clock (SC).
LK), and Φ) is the erase pattern (DP
, DQ), (C) is the write clock (WCLKP, W
CLKQ).

FIG. 20 is a block diagram of the receiver 10 in FIG. 12.

In FIG. 20, the same symbols as in FIG. 12 indicate corresponding parts, 31 is a variable coding rate Vitabi decoder, 32
is decoded data (DECDATA), 33 is a reception buffer, and 34 is an address counter.

Next, the operation will be explained.

First, the transmitter 2 of the variable coding rate error correction communication device shown in FIG. 12 encodes input data 1 (IDATA) and transmits data l3a, 3b (TDATAP,
TDATAQ), this transmission data 3a, 3b
is supplied to a modulator (not shown). Here, this transmitter 2 uses a convolutional code with a coding rate 'fL=172. Furthermore, this transmitter 2 adopts punctured coding technology to vary the coding rate, and as a result, it can perform two types of coding: coding rate hole = 1/2 and R = 3/4. It has the function to do. This coding rate selection is controlled by control signal 4 (
PNC). Then, on the receiving side, soft decision data 9a, 9b (8DATAP).

8DATAQ) is supplied from the illustrated demodulator, and the receiver 10 inputting the soft decision data 9a and 9b performs variable coding rate Vitabi decoding in accordance with the encoding of the transmitter 2, and outputs data 11 (ODATA). Output.

Next, the flow of signals in the transmitting section will be explained with reference to FIG.

First, input data 1 (IDATA) is first stored in the transmission buffer 12, and then read out by the clock B (SCLK) selected by the switch 7. The address counter 14 is a counter for giving the read address 15 (A) of the transmission buffer 12. For example, in a TDMA communication system, the transmission buffer 12 stores low-speed continuous data from the user in a predetermined time slot. It also has the ability to compress and create high-speed burst data.

Next, the data 13 read out from the transmission buffer 12
(BDATA) is encoded by the variable rate encoder 16. When 1't=1/2 code, the control signal 4 (PNC) causes the switch 7 to output the transmission clock 6.
(TCLK). On the other hand, F
In the case of L=374 punctured code, switch 7F
Controlled by selecting the i data clock 5 (DCLK).

Next, the operation of the variable coding rate encoder 16 will be explained with reference to FIGS. 14, 15, and 16.

First, consider the case where R=1/2 code as a first case.

The output data 13 (BDATA) of the transmission buffer 12 is encoded by the encoder 17 shown in FIG.
TAP, CDATAQ). Then, this encoded data 18a, 18b (CDATAP, C
DATAQ) is selected by the selector 21 and becomes the transmission data 3a.

3b (TI) ATAP, TDATAQ),! : Yes.

In this case, the clock FJ (
SCLK) is the same as transmit clock 6 (TCLK). Therefore, the time chart becomes as shown in FIG. 17. However, in FIG. 17, circuit delays are ignored for simplicity.

Next, as a second case, consider the case where R=3/4 punctured code.

In this case, encoded data 18a, 18b (CDATAP
, CDATAQ) are first stored in the FIFO memory 19. Then, the two channels P and Q are connected to each other 23a, 23b (WCLKP, WC
LKQ) is supplied from the clock control circuit 22. Here, it is the transmission clock 6 (TCLK) that reads out the FIFO memory 19. Then, the selector 21 selects the outputs 20 of the two channels P and Q of the FIFO memory 19.
Select a, 20b (PCDATAP, PCDATAQ).

In this case, the clock 9 (8CLK) that drives the encoder 11 and the clock control circuit 22 is the data clock 5 (DCLK), which has a speed 1.5 times the speed of the transmission clock.
Additionally, output data 13 (BDAT
A) is read out.

A time chart in this case is shown in FIG.

Again, circuit delays are ignored for simplicity.

Then, the encoder 17 uses the data clock 5 (DCLK)
Encoded data 18a, 18b (CDATAP
.

CDATAQ). Next, puncture encoding is performed using the encoded data consisting of 3 bits for each channel as one block. Then, in channel P, the last third bit of coded data in the block is erased, and in channel Q, the middle second bit of coded data is erased. That is, if the position of the erased bit is expressed as ``0'', the P channel erase pattern 29a (DP)
is @110' 17, Q channel erase pattern 29b
(DQ) is @101''. This erase pattern 29a
, 29b (DP, DQ)
3a (WCLKP, WeLKQ) are being created.

Then, transmission data 3a, 3b (TDATAP, TDA
The fact that TAQ) is synchronized with the transmitted CT rack (TCLK) is the same as in the case of 几=1/2 code.

Next, the operation of the clock control circuit 22 is shown in FIGS. 16 and 19.
The diagram will be explained.

First, the selected clock 9 (8CLK) is frequency-divided by the counter 26 and input to the erase pattern generation circuit 28, which generates the erase pattern y29a.
, 29b (DP, DQ). Then, in aoa and aob, the selected clock B (SCLK) and erase patterns 29a and 29b are selected.
(DP, DQ) and f)
WCLKQ) is created.

Next, output data 1 is output from the transmission buffer 12.
3 (BDATA) is synchronized with the transmission clock a (TCLK) in the case of R = 1/2 code, but in the case of R = 374 punctured code, it is data that is 1.5 times faster than that speed. Synchronized with clock 5 (DCLK). Therefore, the transmitter 2 operates in synchronization with the transmission clock 6 (TCLK) in the case of R;1/2 code, and )L=
Data clock 5 in case of H.374 punctured code
(DCLK). In either case, the transmitter 2 transmits transmission data 3a, 3b (TDATAP, TDATA) synchronized with the transmission clock 5 (TCLK).
Q) is output.

Next, the operation of the receiver 10 will be explained with reference to FIG.

The operation of this receiver 10 corresponds to the operation of the transmitter 2, and this receiver 10 receives received data 9a, 9b (8DATAP, 8DATAP,
8DATAQ) is received. Since the variable coding rate Viterbi decoder 31 is driven by the selected clock 8 (SCLK), in the case of )L=1/2 code, it operates in synchronization with the transmission clock e (TCLK), R=3/
In the case of a 4-punctured code, the data clock 5 (D
CLK). Then, the decrypted data 32
(DECDATA) are written to the receive buffer 33 at their respective clock speeds, and finally the output data 11 (
ODATA).

[Problem that the invention seeks to solve]

Conventional coding rate variable error correction communication devices are configured as described above, so in order to keep the speed of transmitted and received data constant, it is necessary to change the operating speed of the transceiver according to the coding rate. Therefore, when this device is applied to a TDMA communication system, the following problems occur.

That is, first of all, in a TDMA communication system, the coding rate of transmitted and received data changes for each data burst that is transmitted for a predetermined period of time. In order to deal with this,
It is necessary to operate the switch 7 in a time-division manner for each data burst. However, this is not preferable for the following reasons.

■ Switching noise during switching reduces the stability of circuit operation.

■ The circuit has the delay time necessary for signal processing. Therefore, in the above-described time division operation of the switch 70, for example, the clock 8 (8CLK
) and the switching time of the clock 8 (8CLK) supplied to the variable coding rate encoder 16 must be precisely adjusted in accordance with the delay time of the circuit. This requires a complicated adjustment mechanism, which further reduces the stability of the circuit operation.

Second, in order to solve the above problem, the transmission buffer 12
It is possible to change the circuit design rather than having the variable coding rate decoder 1B always operate on, for example, the transmission clock a (TCLK) regardless of the coding rate. However, in this case, the following problems occur.

■ Transmission data 13a, 3b (TDATAP, TDATA
The speed of Q) changes depending on the coding rate. therefore,
It is necessary to provide a buffer at the output of the transmitter 2 to absorb changes in the clock speed. However, this buffer requires a large capacity equivalent to approximately 1 data bursts, which increases the circuit scale.

■ Since the capacity of the buffer mentioned above is finite, it cannot be applied to continuous mode communication other than TDMA communication. However, there was a problem that if the design was changed to make it suitable for this purpose, it would become unsuitable for continuous mode communication.

This invention was made to solve such problems, and without reducing the stability of circuit operation,
The purpose of the present invention is to obtain a variable coding rate error correction communication device that does not require a complicated adjustment mechanism (can be applied to burst mode kGK of a TDMA communication system, and can also be applied to continuous mode communication). shall be.

[Means for solving problems]

The variable coding rate error correction communication device according to the present invention has a means for coding input data that operates in synchronization with a first clock having a constant speed regardless of the coding rate, and a means for coding input data that operates in synchronization with a first clock having a constant speed regardless of the coding rate. and means for outputting transmission data synchronized with a second speed clock, the variable encoding rate encoder selectively encoding the input data at a plurality of encoding rates and outputting the transmission data. and a means for decoding the input data synchronized with the second clock having a constant speed regardless of the encoding rate in synchronization with the first clock having a constant speed regardless of the encoding rate. On the other hand, there is a variable coding rate Vitabi decoder that selectively decodes the coding rate of the mantissa and outputs decoded data, and a variable coding rate Viterbi decoder that outputs decoded data by selectively decoding the coding rate of the mantissa, and a variable coding rate Vitabi decoder that sets the first clock speed and the second clock speed to be constant regardless of the coding rate. encoding means, converting the input data into data synchronized with the first clock in a transmission buffer, selectively encoding the data at a plurality of encoding rates, and converting the input data into data synchronized with the first clock; a transmitter that outputs transmission data synchronized with the variable coding rate encoder from the variable coding rate encoder, and performs encoding and decoding with the first clock speed and the second clock speed constant regardless of the coding rate. The transmitting buffer and the receiving buffer are provided on the means and the user side, data is read or written from each of the transmitting and receiving buffers using the first clock, and the data is interfaced with the modem using the second clock. It is something.

[Effect]

In this invention, an enable signal is internally generated corresponding to the coding rate, and continuous operation or intermittent operation is automatically selected and performed based on this, so that a constant clock is always maintained regardless of the coding rate. It works.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing an embodiment of a variable coding rate error correction communication device according to the present invention.

In FIG. 1, the same numbers as in FIG. 12 indicate corresponding parts, 2a is a transmitter, 3c and 3d are transmission data (TI) ATAP, TDAT in two channels P and Q.
AQ), 9c and 9d are two channels P.

10a is a receiver, 35 is an enable signal generation circuit, and 36 is an enable signal E.

FIG. 2 is a block diagram showing the transmitter 2a and enable signal generation circuit 35 of FIG. 1.

In FIG. 2, parts that are the same as those in FIG. 1 are given the same reference numerals and explanations will be omitted. 12a is a transmission buffer, 13a is data read from the transmission buffer 12a (BDAT
A), 14a is an address capacitor capable of intermittent operation to suppress the glare of the transmission buffer 12a.
It can be easily realized using 'l'L IC (SN74 L8163). 15a is a read address, and 16a is a variable coding rate encoder.

The transmitter@2a is equipped with a means for encoding the first clock speed and the second clock speed as constant regardless of the encoding rate, and converts the input data into data synchronized with the first clock in the transmitting amplifier 12a. This data is then selectively encoded at multiple encoding rates to generate the second data.
The coding rate variable encoder 16a outputs transmission data synchronized with the clock of the variable coding rate encoder 16a. The transmitter 2a also includes means for generating a control signal corresponding to a coding rate, and means for intermittently operating a transmission buffer and a variable coding rate encoder using this control signal,
Furthermore, means is provided for automatically selecting one of a continuous operation and a plurality of types of intermittent operations by selecting a coding rate.

FIG. 3 is a circuit diagram showing an example of the configuration of the enable signal generation circuit 31 shown in FIG. 2.

In FIG. 3, the same reference numerals as in FIG.
output, 39 is control signal 4 (PNC) and 3 frequency divider circuit 3
This is an AND gate that takes the output of 7 as an input.

FIG. 4 is a time chart showing the relationship between the operation of the enable signal generation circuit 31 and the read address 15a.
indicates the data clock (DCLK), (
b) shows the enable signal (g) rs; and (c) shows the read address (6).

FIG. 5 is a circuit diagram showing an example of the configuration of the variable coding rate encoder 16a of FIG. 2.

In FIG. 5, the same parts as in FIG. 2 are given the same reference numerals, and their explanation will be omitted. 17a is a convolutional encoder of 几=1/2 code, 18C and 18d' are this convolutional encoder 17
Encoded data p( which is the output of two channels P and Q of a)
CDATAP, CDATAQ), 19a is f'IFo memory, 20a, 20b are punctured encoded data, 2
1a is a selector, 22a is a clock control circuit, 23a, 2
3b are two channels P for FIFO memory 19a.
, Q (WCLKP, WCLK
Q), 4 G beam timing circuits, 41a, 41b are for retiming data (R
DATAP, RDATAQ).

The variable coding rate encoder 16a includes a means for coding input data by operating in synchronization with a first clock having a constant speed regardless of the coding rate, and a means for coding input data at a constant speed regardless of the coding rate. and means for outputting transmission data synchronized with a second clock of the speed, and is configured to selectively encode input data at a plurality of encoding rates and output transmission data. Moreover, this coding rate variable encoder 16 a
Fi, comprising means for intermittently operating the circuit by temporarily placing the circuit in a hold state, and means for retiming output data produced by the intermittent operation with a second clock; The apparatus is provided with means for automatically selecting one operation mode between continuous operation and a plurality of types of intermittent operations by selecting the conversion rate.

FIG. 6 is a circuit diagram showing an example of the configuration of encoder 17H in FIG. 5.

In FIG. 6, the same reference numerals as in FIG. 5 indicate corresponding parts, 25a, 25b, .
6. However, it is a delay element for only one period of the data clock s (DCLK) that can operate intermittently,
This can be easily realized using, for example, the aforementioned IC (SN74L8379).

FIG. 7 is a time chart showing the encoding process using R=1/2 code, (a) shows the data clock (DCLK), (b) shows the data (DATA), (c
) is the enable signal (121, (d) is the encoded data (
CDATAP, CDATAQ), (e) is the transmission clock (TCLK), (f) is the transmission data (TDATAP, T
DATAQ).

FIG. 8 is a circuit diagram showing an example of the timing circuit 40 shown in FIG.

In FIG. 8, the same reference numerals as in FIG. 5 indicate corresponding parts, and 43a is a first D flip-flop, which is capable of intermittent operation. And this is for example TEXAs INS-TRUMENTS
This can be easily realized using the TTL IC (8N74 L8379) manufactured by the company. 44a and 44b are output data (DFFIP) of the first D flip-flop 43a.

DFFIQ), 45 is the second D flip-flop, 48
a, 46b are the output data (DFFsP, DFFsQ) of this second D7 lip 70 tube 45, and 47 is the output data of the third D7
48 is a phase shifter, 49 is this phase shifter 48
transmit clock (TCLKKI) phase-shifted by, 5
0a and 50b are retiming data (RDATAP, 几DATAQ).

FIG. 9 is a time chart showing the operation of the timing circuit 40 shown in FIG. 5, and (a) is a data clock (DCLK).
The coded data (CDATA) is the coded data (CDATA).
P, CDATAQ), (C) is the enable signal Q), (
d) is the output of the first D flip-flop 43a (DFF
IP, DFFIQ), (e) is the sending cx7 link (TCL
K), (f) are the phase shifter output (TCLKl), (2) is the output of the second D flip-flop 45 (DFFgP, DF
FaQ), Φ) beam timing data ()t, DAT
AP, RDATAQ).

FIG. 10 is a block diagram showing an example of the receiver 108 in FIG. 1.

In FIG. 10, the same parts as in FIG. 1 are designated by the same reference numerals, and their explanation will be omitted. 36 is an enable signal (c),
51a is a variable coding rate Viterbi decoder, 52a is decoded data (DECDATA) which is the output of this variable coding rate Viterbi decoder 51a, 53 is a reception buffer, 54a is an address counter, and 55 is soft decision data (SDATAP).
, 8DATAQ), which is a flip-flop similar to the first D flip-flop 43a shown in FIG. 56a and 56b are retiming soft decision data (R8DATAP, R8DATAQ) output from this retiming circuit 55.

Note that, in the same way as creating a new encoder 17a shown in FIG. 5 from the conventional encoder 17 shown in FIG. By replacing all D flip-flops with D flip-flops with enable terminals capable of intermittent operation (for example, the 8N74 L8379), the new variable code rate Viterbi decoder 5 shown in FIG.
1a can be made.

The variable coding rate Viterbi decoder 51a synchronizes the input data, which is synchronized with the second clock which has a constant speed regardless of the coding rate, with the first clock which has a constant speed regardless of the coding rate. The decoding device is configured to selectively decode input data at a coding rate of the decimal number and output decoded data. The variable coding rate Viterbi decoder 51a also includes a means for intermittently operating the circuit by temporarily putting the circuit in a hold state, and a means for reproducing input data synchronized with the second clock using the first clock. The apparatus further includes means for automatically selecting one of continuous operation and a plurality of types of intermittent operation by selecting a coding rate.

FIG. 11 is a time chart of the input timing circuit 55 of the receiver 10a in FIG. 10, where (a) shows the transmission clock (TCLK), and (b) shows the soft decision data (8DATAP, 8DATAQ), (c)
are the data clock (DCLK) and (dl) timing soft decision data (R8DATAP, R8DATAQ).

And, the coding rate variable error correction communication device of the present invention has the following features:
The above-mentioned transmitter 2a, variable coding rate encoder 18a, and variable coding rate Vitabi virtual coder 51a are provided, and the first clock speed and the second clock speed are constant regardless of the coding rate. It has a means for decoding, and also has a transmission buffer and a reception buffer on the user side, reads or reads data from these buffers with a first clock, and interfaces with a modem with a second clock. It is composed of Further, this coding rate variable encoder's regular communication device includes means for generating a control signal corresponding to the coding rate, and means for intermittently operating a circuit according to the control signal, and further includes: The apparatus is equipped with means for fully automatically selecting one of continuous operation and a plurality of types of intermittent operation by selecting the conversion rate.

Next, the operation of the embodiment of the variable coding rate error correction communication device shown in FIG. 1 will be explained.

First, signal processing is basically the same as the conventional device shown in FIG.

However, in the device of the embodiment shown in FIG. 1, the enable signal 3B@ is generated in the enable signal generating circuit 35 from the control signal 4 (PNC) and the data clock 5 (DCLK). This enable signal 36υ is 几=3
In the case of a /4 punctured code, it is a @Low level DC signal, and in the case of R = 1/2 code, it is an intermittently “L” level DC signal.
ow'" to "High'". Then, the transmitter 2a and receiver 10a receive this enable signal 36 (c).
It operates continuously or intermittently based on

Next, the flow of signals in the transmitting section will be explained with reference to FIG.

When the enable signal 3B (6) shown in FIG. 1 is @Low'', the transmitter in FIG. 2 operates in the same way as the transmitter in FIG. 13 described above. Then, the enable signal 3B (6)
When becomes @)iigh'', the address counter 14a is not in the hold state, and the read address 15a (6) does not change even if the data clock 5 (DCLK) changes. Therefore, at this time, the address counter 14a is not changed. Data l 3 a (BiJATA) also remains unchanged.

On the other hand, the variable coding rate encoder 18a also enters a hold state when the enable signal 36@ is @High.

In this way, the transmission buffer 12a and the variable coding rate encoder 16m can operate intermittently based on the enable signal 36@.

Next, regarding FIGS. 3 and 4, enable signal 36@
).

In the case of a punctured code with a coding rate R=374, the control signal 4 (PNC) goes ``Low'' and the enable signal 36@ also goes ``Low''. On the other hand, the coding rate R
=172 code, control signal 4 (PNC) is '''
High”.Then, data clock 5 (DCL
A signal obtained by dividing the frequency of the signal K) by 3 by the frequency divider 37 is output as the enable 4h signal 36 (g). Therefore, the relationship between the data clock 5 (DCLK) and the enable signal 36@ is as shown in FIG. 4(a).

Next, the read address 15 is the enable signal 36.
When @ is 'Low''', data clock 5
When the enable signal 36 (DCLK) rises, it increases by 1, but when the enable signal 36) is @High, it is not in a hold state and does not change even when the data clock 5 (DCLK) rises. The signal time chart is as shown in Fig. 4. Therefore, the transmission buffer 12
The output data 13 a (BDATA) of a is always synchronized with the data clock 5 (DCLK) regardless of the coding rate. However, in the case of R=1/2 code, as is clear from the time chart of FIG. 4, two out of three clocks contain the same data consecutively.

Next, the operation of the variable coding rate encoder 16H will be explained with reference to FIGS. 5, 6, and 7.

First, in the case of a punctured code with R=3/4, the enable signal 36@ is "@Low", and the encoder 17a operates in the same way as the conventional encoder 17 shown in FIG. 14.

In addition, in this case, the selector 21a is the FIFO memory tsa
o Select output data 20a and 20b and send data 3
c, 3d (TDATAP, TDATAQ)
Output as . Therefore, in this case, the variable coding rate encoder 16a shown in FIG. 2 operates in the same way as the conventional variable coding rate encoder 16 shown in FIG. 13, and its time chart is the same as that in FIG. be.

Next, in the case of 几=l/2 code, the encoder 17a shown in FIG. 6 operates intermittently by the enable signal 36@. As a result, encoded data 18a, 18b (CDATAP, CDATA) as shown in the time chart of FIG.
Q) is obtained (see FIG. 7(d)). Then, in the retiming circuit 40 shown in FIG.
a, 19b (CDATAP, CDATAQ) are retiming timing data fi41a, 41b (RDATAP, RD) by transmission clock 6 (TCLK).
ATAQ). Then, the selector 21a selects timing data 41a, 41b (RDATAP).

RDATAQ) and transmit data 3c, 3d (TD
ATAP, TDATAQ). The time chart is shown in FIG. However, this seventh
In the figure, circuit delays are ignored for simplicity.

Next, regarding FIGS. 8 and 9, the retiming circuit 40
Explain the operation.

First, encoded data 18a, 18b (CDATAP, C
DATAQ) is first reflocked and shaped by the data clock 5 (DCLK) in the first D flip-flop 43a which operates intermittently. Then, the output data 44a and 44b are relocked by the second D flip 70 knob 45. Here, the second D flip-flop 45 is supplied with a transmission clock 49 (TCLK) whose phase is shifted by a phase shifter 48 so that the reflock timing is at the center of the change point of the output data 44a, 44b. has been done.

Next, the output data 4 of the second D flip-flop 45
6a and 46b are reflocked by the transmission clock 6 (TCLK) in the third D free lag flop 4f and retiming data 50a and 50b (RDATA
P.

RDATAQ). A time chart of this retiming circuit 40 is shown in FIG.

As described above, the transmitter 2a of the coding rate variable error correction communication device according to the present invention always operates in synchronization with the data clock 5 (DCLK) regardless of the coding rate, and transmits data 3c.
, 3d (TDATAP, TDATAQ) are output in synchronization with the transmission clock 6 (TCLK).

Next, the operation of the receiver 10H will be explained with reference to FIG.

First, the receiver 10a has a transmission clock 6 (TCLK).
Soft decision data 9c, 9d (8DATAP.

8DATAQ) is input. Then, in the retiming circuit 55, the soft decision data 9c, 9d (SDATA
P, 8 DATAQ) is the data clock 5 (D
CLK).

Next, input soft decision data 9c, 9d (SDAT
AP, 5DATAQ) and data clock 5 (DCLK
), the timing will be as shown in the time chart of Figure 11.

In this way, as a result of retiming, encoded data 18a, 18b (CDATAP,
Timing soft decision data 56a and 56b (R8DATAP) have the same form as CDATAQ).

R8DATAQ) is obtained.

The variable coding rate Vitabi decoder 51a in FIG. 10 is the variable coding rate encoder 16a in FIG.
Similarly, intermittent operation is performed only when R=1/2 code. The variable coding rate Viterbi decoder 51a always operates in synchronization with the data clock 5 (DCLK) regardless of the coding rate, and outputs decoded data 52a (DECDATA).
Output. It passes through a receive buffer 53 controlled by an address counter 54a that can operate intermittently.
It is output as output data 11 (ODATA).

Although the above embodiment is a device for continuous mode communication, by providing a control circuit for controlling the transmitter @2a, the receiver toa, and the enable signal generation circuit 35 in burst mode, it is possible to perform TDMA communication, for example. The device may have a configuration that can be applied to burst mode linkage of the system, and has the same advantages as the above embodiment.

Further, in the above embodiment, the case of a code with a coding rate R=1/2 and a punctured code with a coding rate R=3/4 has been described, but other coding rates may be used. Furthermore, punctured codes with a plurality of types of coding rates may be used, and the same advantages as in the above embodiments can be obtained.

1fc, in the above embodiment, the input soft decision data 9c, 9d in the retiming circuit 55 of the receiver 10a.
It is assumed that the timing of (SDATAP, 5DATAQ) and the timing of data clock 5 (DCLK) match well, but in general, if this condition is not met, input soft decision data 9c, 9d (S
A phase shifter and a D flip-flop for relocking the signals (DATAP, 8DATAQ) using a transmission clock whose phase has been shifted in advance may be provided at the input stage of the retiming circuit 55. It has the following advantages.

〔Effect of the invention〕

As described above, according to the present invention, the coding rate variable error correction communication device is configured to automatically generate an enable signal in accordance with the coding rate and perform intermittent operation based on the enable signal. Therefore, it is possible to always operate with a constant clock regardless of the coding rate, and the TDMA communication system can be improved without reducing the stability of circuit operation or requiring a complicated adjustment mechanism. This has the effect of providing a device that can be applied to burst mode communication as well as continuous mode communication.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of a variable coding rate error correction communication device according to the present invention, and FIG. 2 is a configuration diagram showing an extracted portion of the transmitter and enable signal generation circuit in FIG. 1. 3 is a circuit diagram showing an example of the enable signal generation circuit of FIG. 2, and FIG. 4 is a time chart showing the relationship between the operation of the enable signal generation circuit and the read address.
5 is a block diagram showing an example of the variable rate encoder shown in FIG. 2, FIG. 6 is a circuit diagram showing an example of the encoder shown in FIG. 5, and FIG.
The figure is a time chart showing the encoding process using the 几=1/2 code, Figure 8 is a circuit diagram showing an example of the timing circuit in Figure 5, Figure 9 is a time chart showing the operation of the timing circuit in Figure 10. Figure 11 is a block diagram showing an example of a receiver; Figure 11 is a time chart of the input timing circuit of the receiver; Figure 12 is a block diagram showing an example of a conventional variable coding rate error correction communication device; Fig. 13 is a block diagram showing the transmitter and switch in Fig. 12, Fig. 14 is a block diagram showing an example of the variable coding rate encoder in Fig. 13, and Fig. 15 is a block diagram showing an example of the encoder in Fig. 14. 16 is a configuration diagram showing an example of the clock control circuit in FIG. 14, and FIG. 17 is a circuit diagram showing an example of the clock control circuit in FIG.
Time chart showing the process of encoding using 2 codes, 1st
FIG. 8 is a time chart showing the encoding process using R=3/4 punctured code, FIG. 19 is a time chart showing the operation of the clock control circuit, and FIG. 20 is a configuration diagram showing an example of a receiver. 2a...Transmitter, 10a...Receiver, 12a...
...-Transmission buffer, 14a...Address counter, 16as--Coding rate variable encoder, 17a...
Encoder, 19a... FIFO memory, 21a...
・Selector, 22a・φe・Clock control circuit, 35...
...Enable signal generation circuit, 37...3 frequency divider,
39...AND gate, 40--...Retiming circuit, 423-42h@a e e delay element, 43a
@45,47 @...D flip-flop, 48...
- Phase shifter, 51a @... Variable coding rate Viterbi decoder, 53... - Reception buffer, 54a... Address counter, 55... Retiming circuit.

Claims (1)

[Claims] Means for encoding input data that operates in synchronization with a first clock having a constant speed regardless of the encoding rate, and outputting second transmission data synchronized with the lock that has a constant rate regardless of the encoding rate. a variable coding rate encoder that selectively encodes the input data at a plurality of coding rates and outputs the transmission data; and a variable coding rate encoder that outputs the transmission data by selectively encoding the input data at a plurality of coding rates; means for decoding input data synchronized with a second clock of the clock in synchronization with a first clock having a constant speed regardless of the coding rate, and selecting decoding of a plurality of coding rates for the input data. a variable coding rate Viterbi decoder that outputs decoded data according to the coding rate;
and a second clock speed, the input data is converted into data synchronized with the first clock in a transmission buffer, and the data is encoded at a plurality of encoding rates. a transmitter that selectively performs encoding and outputs transmission data synchronized with the second clock from the variable encoding rate encoder; means for encoding and decoding at a constant clock speed of 2, and the transmitting buffer and receiving buffer on the user side;
A coding rate variable error correction communication device characterized in that data is read or written from each of these transmission and reception buffers using the second clock, and interfaces with a modulator/demodulator using the second clock.