JPS63114246A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63114246A JPS63114246A JP61261215A JP26121586A JPS63114246A JP S63114246 A JPS63114246 A JP S63114246A JP 61261215 A JP61261215 A JP 61261215A JP 26121586 A JP26121586 A JP 26121586A JP S63114246 A JPS63114246 A JP S63114246A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- memory integrated
- circuit element
- spare
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 230000002950 deficient Effects 0.000 claims abstract description 16
- 238000012360 testing method Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 12
- 238000003860 storage Methods 0.000 description 34
- 238000000034 method Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 8
- 238000005520 cutting process Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は半導体装置に関し、特に多数個のメモリ集積
回路素子を１枚の半導体基板上に形成し大容量記憶ディ
スクとして使用する半導体装置に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a large number of memory integrated circuit elements are formed on a single semiconductor substrate and used as a large-capacity storage disk. It is.
［従来の技術］
数メガバイト級またはそれ以上の大容量記憶装置として
従来から磁気テープ、磁気ディスク、フロッピィディス
クがあり、また高速の大容量記憶装置として数個〜数１
０個のメモリＩＣチップを１枚のプリント基板上に配置
し、メモリＩＣチップ間を外部配線で接続したもの、あ
るいは数個のメモリＩＣチップを特殊なパッケージに配
置してモジュール化したものがある。ざらに、最近では
多数個のメモリ集積回路素子を１枚の半導体基板上に形
成し大容量記憶装置として利用するものがあり、ここで
はこの大容量記憶装置を仮に半導体記憶ディスクと名付
ける。[Prior Art] Magnetic tapes, magnetic disks, and floppy disks have conventionally been used as large-capacity storage devices of several megabytes or more, and high-speed large-capacity storage devices of several to several
There are 0 memory IC chips arranged on one printed circuit board and connected between the memory IC chips with external wiring, and there are also modules in which several memory IC chips are arranged in a special package. . Roughly speaking, recently there are devices in which a large number of memory integrated circuit elements are formed on a single semiconductor substrate and used as a large capacity storage device, and herein, this large capacity storage device is tentatively named a semiconductor storage disk.
第３図は、従来の半導体記憶ディスクを示す図である。FIG. 3 is a diagram showing a conventional semiconductor storage disk.
図において、１枚の半導体基板１上に基盤目状に複数個
のメモリ集積回路素子２が形成されており、Ｂｌ、Ｂ２
はそれぞれ一群のメモリ集積回路素子２からなるメモリ
ブロックである。メモリブロック８１、Ｂ２において正
常な動作をする良メモリ集積回路素子２ａ間のみが内部
配線〈図示せず）で接続されており、またメモリブロッ
クＢ１と８２とは内部配線５で接続されている。６は半
導体記憶ディスクを外部回路と接続するための外部配線
である。In the figure, a plurality of memory integrated circuit elements 2 are formed on one semiconductor substrate 1 in a grid pattern, and B1, B2
are memory blocks each consisting of a group of memory integrated circuit elements 2. In memory blocks 81 and B2, only good memory integrated circuit elements 2a that operate normally are connected by internal wiring (not shown), and memory blocks B1 and 82 are connected by internal wiring 5. 6 is an external wiring for connecting the semiconductor storage disk to an external circuit.
半導体記憶ディスクはこのように１枚の半導体基板１上
に釜数個のメモリ集積回路素子を形成しているので、各
メモリ集積回路素子２の歩留りが高いことが必要である
と同時に、良メモリ集積回路素子２ａと不良メモリ集積
回路素子２ｂを選択して不良メモリ集積回路素子２ｂを
良メモリ集積回路素子２ａから電気的に切離すことが必
要となってくる。Since the semiconductor storage disk has several memory integrated circuit elements formed on one semiconductor substrate 1 in this way, it is necessary that the yield of each memory integrated circuit element 2 is high, and at the same time, it is necessary to have a high quality memory. It becomes necessary to select the integrated circuit element 2a and the defective memory integrated circuit element 2b and electrically disconnect the defective memory integrated circuit element 2b from the good memory integrated circuit element 2a.
第４図は、第３図の半導体記憶ディスクの製造方法の工
程図である。FIG. 4 is a process diagram of a method for manufacturing the semiconductor storage disk of FIG. 3.
この製造方法について説明すると、まず、半導体基板１
上に複数個のメモリ集積回路素子２を形成する（ステッ
プＳ１）。次に、各メモリ集積回路素子２の動作をテス
トして、正常動作する良メモリ集積回路素子２ａと誤動
作する不良メモリ集積回路素子２ｂを選別する（ステッ
プ３２＞。次に、メモリブロック８１、Ｂ２において良
メモリ集積回路素子２８間のみ内部配線で接続して不良
メモリ集積回路素子２ｂを良メモリ集積回路素子２ａか
ら電気的に切離し、かつメモリブロックＢ１と８２間を
内部配線５で接続することによって半導体記憶ディスク
を完成する（ステップＳ３）。To explain this manufacturing method, first, the semiconductor substrate 1
A plurality of memory integrated circuit elements 2 are formed thereon (step S1). Next, the operation of each memory integrated circuit element 2 is tested to select a good memory integrated circuit element 2a that operates normally and a defective memory integrated circuit element 2b that malfunctions (step 32>.Next, the memory blocks 81, B2 By connecting only the good memory integrated circuit elements 28 with the internal wiring to electrically disconnect the defective memory integrated circuit element 2b from the good memory integrated circuit element 2a, and connecting the memory blocks B1 and 82 with the internal wiring 5. The semiconductor storage disk is completed (step S3).
次に、この半導体記憶ディスクの動作をテストする（ス
テップＳ４）、この後、半導体記憶ディスクの動作が正
常な場合にこれを外部配線６により外部回路と接続する
。Next, the operation of this semiconductor storage disk is tested (step S4). After this, if the operation of the semiconductor storage disk is normal, it is connected to an external circuit via external wiring 6.
［発明が解決しようとする問題点〕
従来の半導体記憶ディスクは以上のような工程で製造さ
れるが、半導体基板１上のどこに良メモリ集積回路素子
２ａ、不良メモリ集積回路索子２ｂが配置されるかは各
半導体記憶ディスクの製造ごとに種々異なるため、半導
体記憶ディスクごとに内部配線状況が変わって内部配線
工程が煩雑なものになり、半導体記憶ディスクの歩留り
や品質が低くなるという問題点があった。また、半導体
記憶ディスクごとに内部配線状況が変わるので、内部配
線を固定化してこれをメモリ集積回路素子２の動作テス
ト前に半導体基板１上にメモリ集積回路素子２と一括し
て同時に形成することができず、半導体記憶ディスクの
製造工程が長くなるという問題点もあった。[Problems to be Solved by the Invention] Conventional semiconductor storage disks are manufactured through the steps described above, but it is difficult to determine where on the semiconductor substrate 1 the good memory integrated circuit elements 2a and the bad memory integrated circuit elements 2b are placed. Since the internal wiring conditions vary depending on the manufacturing of each semiconductor storage disk, the internal wiring situation changes for each semiconductor storage disk, making the internal wiring process complicated and causing problems such as lowering the yield and quality of semiconductor storage disks. there were. Further, since the internal wiring situation changes for each semiconductor storage disk, it is necessary to fix the internal wiring and form it simultaneously with the memory integrated circuit element 2 on the semiconductor substrate 1 before testing the operation of the memory integrated circuit element 2. There was also the problem that the manufacturing process for semiconductor storage disks was lengthened.
この発明は上記のような問題点を解消するためになされ
たもので、歩留りが高く、かつ高品質で、かつ製造工程
を短縮できる半導体記憶ディスクを得ることを目的とす
る。The present invention has been made to solve the above-mentioned problems, and aims to provide a semiconductor storage disk that has a high yield, high quality, and can shorten the manufacturing process.
［問題点を解決するための手段］
この発明に係る半導体装置は、半導体基板上に、複数個
の集積回路素子と、少なくとも１個の予備の集積回路素
子と、複数個の集積回路素子のうちそれらの動作テスト
により選別された不良集積回路素子を予備の集積回路素
子と冨き換えるための冗長回路とを一括して同時に形成
したものである。[Means for Solving the Problems] A semiconductor device according to the present invention includes a plurality of integrated circuit elements, at least one spare integrated circuit element, and one of the plurality of integrated circuit elements on a semiconductor substrate. Defective integrated circuit elements selected through these operation tests are simultaneously formed with spare integrated circuit elements and a redundant circuit for replacing them.
［作用］
この発明においては、半導体基板上に集積回路素子以外
に予備の集積回路素子、冗長回路を形成し、冗長回路に
より不良集積回路素子を予備の集積回路素子と置き換え
るようにしているので、内部配線を固定化してこれを半
導体基板上に集積口！′８素子、予備の集積回路素子、
冗長回路と一括して同時に形成することができる。この
ため、従来の場合のような煩雑な内部配線工程を省くこ
とができ、半導体記憶ディスクの歩留りや品質が向上す
るとともにその工程が短縮化される。[Function] In this invention, in addition to the integrated circuit element, a spare integrated circuit element and a redundant circuit are formed on the semiconductor substrate, and the redundant circuit replaces a defective integrated circuit element with the spare integrated circuit element. Fix the internal wiring and integrate it onto the semiconductor substrate! '8 element, spare integrated circuit element,
It can be formed simultaneously with a redundant circuit. Therefore, the complicated internal wiring process required in the conventional case can be omitted, improving the yield and quality of semiconductor storage disks and shortening the process.
［実施例］ 以下、この発明の実施例を図について説明する。[Example] Embodiments of the present invention will be described below with reference to the drawings.
なお、この実施例の説明において、従来の技術の説明と
重複する部分については適宜その説明を省略する。In the description of this embodiment, the description of parts that overlap with the description of the conventional technology will be omitted as appropriate.
第１図は、この発明の実施例である半導体記憶ディスク
を示す図である。FIG. 1 is a diagram showing a semiconductor storage disk according to an embodiment of the present invention.
この実施例の構成が第３図の半導体記憶ディスクの構成
と異なる点は以下の点である。すなわち、半導体基板１
上にメモリ集積回路素子２以外に予備の集積回路素子お
よび冗長回路４が形成されている。８１’ 、Ｂ２’
はそれぞれ−群のメモリ集積回路素子２および予備のメ
モリ集積回路素子３からなるメモリブロックである。メ
モリブロック８１’ 、Ｂ２’ において正常な動作を
する良メモリ集積回路素子２ａ間、予備の集積回路素子
３間、良メモリ集積回路素子２ａと予備の集積回路素子
２ｂ間が固定化した内部配線（図示せず）で接続されて
おり、メモリブロック８１′と８２’ とは固定化した
内部配［１７により冗長回路４に接続されている。６は
半導体記憶ディスクを外部回路と接続するための外部配
線である。The configuration of this embodiment differs from the configuration of the semiconductor storage disk shown in FIG. 3 in the following points. That is, the semiconductor substrate 1
In addition to the memory integrated circuit element 2, a spare integrated circuit element and a redundant circuit 4 are formed thereon. 81', B2'
are memory blocks each consisting of a group of memory integrated circuit elements 2 and a spare memory integrated circuit element 3. In the memory blocks 81' and B2', fixed internal wiring ( The memory blocks 81' and 82' are connected to the redundant circuit 4 by a fixed internal wiring [17]. 6 is an external wiring for connecting the semiconductor storage disk to an external circuit.
第２図は、第１図の半導体記憶ディスクの製造方法の工
程図である。FIG. 2 is a process diagram of a method for manufacturing the semiconductor storage disk of FIG. 1.
この製造方法について説明すると、まず、半導体基板１
上に、メモリ集積回路素子２、予備のメモリ集積回路素
子３、冗長回路４、ならびにメモリ集積回路素子２間、
予備の集積回路素子３間、メモリ集積回路素子２と予備
のメモリ集積回路素子３間の固定化した内部配線（図示
せず）およびメモリブロック８１’ と８２’間の固定
化した内部配線７を一括して同時に形成する（ステップ
Ｓ５）。次に、各メモリ集積回路素子２の動作をテスト
し、正常動作する良メモリ集積回路素子２ａと誤動作す
る不良メモリ集積回路素子２ｂを選別する（ステップＳ
６）、次に、冗長回路４を用いて不良メモリ集積回路素
子２ｂを予備のメモリ集積回路素子３と置き換えて半導
体記憶ディスクを完成する。この置き換えは、たとえば
冗長回路４内のヒユーズを大電流により？ｌｉＦ融切断
する方法やレーザ光等の照射により溶融を切断する方法
によって論理電気回路的に行なわれる（ステップ８７）
。次に、半導体記憶ディスクの動作をテストする（ステ
ップ８８）。この後、半導体記憶ディスクの動作が正常
な場合にこれを外部配線６により外部回路と接続する。To explain this manufacturing method, first, the semiconductor substrate 1
Above, a memory integrated circuit element 2, a spare memory integrated circuit element 3, a redundant circuit 4, and between the memory integrated circuit elements 2,
Fixed internal wiring (not shown) between the spare integrated circuit elements 3, between the memory integrated circuit element 2 and the spare memory integrated circuit element 3, and the fixed internal wiring 7 between the memory blocks 81' and 82'. They are formed all at once (step S5). Next, the operation of each memory integrated circuit element 2 is tested, and a good memory integrated circuit element 2a that operates normally and a defective memory integrated circuit element 2b that malfunctions are selected (step S
6) Next, the redundant circuit 4 is used to replace the defective memory integrated circuit element 2b with the spare memory integrated circuit element 3 to complete the semiconductor storage disk. This replacement can be done by, for example, replacing the fuse in the redundant circuit 4 with a large current. This is carried out in a logical electrical circuit manner by a method of cutting the melt by LiF melting or by cutting the melt by irradiation with laser light or the like (step 87).
. Next, the operation of the semiconductor storage disk is tested (step 88). Thereafter, if the semiconductor storage disk is operating normally, it is connected to an external circuit via external wiring 6.
このように、半導体基板１上にメモリ集積回路素子２以
外に予備のメモリ集積回路素子３、冗長回路４を形成し
、冗長回路４によって不良メモリ集積回路素子２ｂを予
備のメモリ集積回路素子３で置き換えるようにしている
ので、半導体基板１上で不良メモリ集積回路素子２ｂが
どのような分布をしようともこれに関係なく、メモリ集
積回路素子２間、予備のメモリ集積回路素子３間、メモ
リ集積回路素子２と予備のメモリ集積回路素子３間の内
部配線およびメモリブロック８１’ と８２′間の内部
配線を固定化してこれを半導体基板１上にメモリ集積回
路素子２、予備のメモリ集積回路素子３、冗長回路４と
一括して同時に形成することができる。このため、従来
の場合のような半導体記憶ディスクごとに内部配線状況
が変る煩雑な内部配線工程が省け、半導体記憶ディスク
の歩留りや品質が向上するとともにその製造工程が短縮
化される。In this way, in addition to the memory integrated circuit element 2, a spare memory integrated circuit element 3 and a redundant circuit 4 are formed on the semiconductor substrate 1, and the redundant circuit 4 replaces the defective memory integrated circuit element 2b with the spare memory integrated circuit element 3. Since the replacement is made, regardless of how the defective memory integrated circuit elements 2b are distributed on the semiconductor substrate 1, the memory integrated circuit elements 2 are replaced, the spare memory integrated circuit elements 3 are replaced, and the memory integrated circuit The internal wiring between the element 2 and the spare memory integrated circuit element 3 and the internal wiring between the memory blocks 81' and 82' are fixed, and then the memory integrated circuit element 2 and the spare memory integrated circuit element 3 are fixed on the semiconductor substrate 1. , and the redundant circuit 4 can be formed simultaneously. Therefore, the complicated internal wiring process in which the internal wiring situation changes for each semiconductor storage disk, which is required in the conventional case, can be omitted, and the yield and quality of semiconductor storage disks are improved, and the manufacturing process thereof is shortened.
なお、上記実施例では半導体記憶装置について示したが
、この発明は半導体論理装置にも適用することができる
。Note that although the above embodiments have been described with respect to semiconductor memory devices, the present invention can also be applied to semiconductor logic devices.
［発明の効果〕
以上のようにこの発明によれば、半導体基板上に集積回
路素子と予備の集積回路素子と冗長回路とこれらの固定
化した内部配線とを一括し゛τ同時に形成し、冗長回路
により不良集積回路素子を予備の集積回路素子と置き換
えるようにしているので、従来の場合のような煩雑な内
部配線工程がなくなる。このため、歩留りが高く、かつ
高品質で、かつ製造工程を短縮できる半導体装置を得る
ことができる。[Effects of the Invention] As described above, according to the present invention, an integrated circuit element, a spare integrated circuit element, a redundant circuit, and their fixed internal wiring are simultaneously formed on a semiconductor substrate, and a redundant circuit is formed. Since the defective integrated circuit element is replaced with a spare integrated circuit element, the complicated internal wiring process required in the conventional case is eliminated. Therefore, it is possible to obtain a semiconductor device that has a high yield, high quality, and can shorten the manufacturing process.
第１図は、この発明の実施例である半導体記憶ディスク
を示す図である。
第２図は、第１図の半導体記憶ディスクの製造方法の工
程図である。
第３図は、従来の半導体記憶ディスクを示す図である。
第４図は、第３図の半導体配憶ディスクの製造方法の工
程図である。
図において、１は半導体基板、２はメモリ集積回路素子
、２ａは良メモリ集積回路素子、２ｂは不良メモリ集積
回路素子、３は予備のメモリ集積回路素子、４は冗長回
路、６は外部配線、７は内部配線である。
なお、各図中同一符号は同一または相当部分を示す。FIG. 1 is a diagram showing a semiconductor storage disk according to an embodiment of the present invention. FIG. 2 is a process diagram of a method for manufacturing the semiconductor storage disk of FIG. 1. FIG. 3 is a diagram showing a conventional semiconductor storage disk. FIG. 4 is a process diagram of a method for manufacturing the semiconductor storage disk of FIG. 3. In the figure, 1 is a semiconductor substrate, 2 is a memory integrated circuit element, 2a is a good memory integrated circuit element, 2b is a defective memory integrated circuit element, 3 is a spare memory integrated circuit element, 4 is a redundant circuit, 6 is an external wiring, 7 is internal wiring. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
、 前記半導体基板上に形成される少なくとも１個の予備の
集積回路素子と、 前記半導体基板上に形成され、前記複数個の集積回路素
子のうちそれらの動作テストにより選別された不良集積
回路素子を前記予備の集積回路素子と置き換えるための
冗長回路とを備えた半導体装置。[Scope of Claims] A semiconductor substrate, a plurality of integrated circuit elements formed on the semiconductor substrate, at least one spare integrated circuit element formed on the semiconductor substrate, and a semiconductor substrate formed on the semiconductor substrate. a redundant circuit for replacing a defective integrated circuit element formed and selected by an operation test among the plurality of integrated circuit elements with the spare integrated circuit element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61261215A JPS63114246A (en) | 1986-10-31 | 1986-10-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61261215A JPS63114246A (en) | 1986-10-31 | 1986-10-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63114246A true JPS63114246A (en) | 1988-05-19 |
Family
ID=17358743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61261215A Pending JPS63114246A (en) | 1986-10-31 | 1986-10-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63114246A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5138419A (en) * | 1988-06-01 | 1992-08-11 | Fujitsu Limited | Wafer scale integration device with dummy chips and relay pads |
-
1986
- 1986-10-31 JP JP61261215A patent/JPS63114246A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5138419A (en) * | 1988-06-01 | 1992-08-11 | Fujitsu Limited | Wafer scale integration device with dummy chips and relay pads |
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