JPS63111540A - Data drive type computer - Google Patents

Abstract

PURPOSE:To shorten the execution waiting time and to eliminate the bottleneck of an arithmetic part by allocating successively the computing elements which are not kept under execution modes by a computing element control part for execution of arithmetic operations in case plural instruction cells designate a single calculator at a time. CONSTITUTION:An arithmetic part 11 contains plural types of calculator blocks and carries out the addition/subtraction and the multiplication/division. A calculator control part 19 consists of an arithmetic part state register whether the calculators are working or not and a control part which allocates the started instruction cell data to the idle calculators. An instruction packet group, if existing in an instruction memory 18, is written into an instruction buffer 14. Each instruction cell starts successively the prepared operand data and sends them to the part 11. When the arithmetic operations are carried out, the multiplication jobs of instruction cells are carried out in parallel based on the control actions of the part 19.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the basics of a data-driven computer in which the operation of the computer is data-driven.

Conventional technology In recent years, with the aim of improving processing speed, in place of the Neumann-type computer, in principle all machine instructions with all operand data can be started, and all the parallelism inherent in programs can be realized in a natural form. Data-driven calculators that can be used to draw data are attracting attention.

However, since this method activates a machine instruction with all operand data, the processing speed is lower than the conventional pipeline method, which sequentially briefetches instructions.

An example of the conventional data-driven computer mentioned above will be described below with reference to the drawings.

Figure 2 shows a conventional data-driven computer, Figure 4 shows an example of writing a data flow program for the roots of a quadratic equation, and Figure 5 shows a packet group for a data flow program that finds the roots of a quadratic equation. It shows.

In FIG. 2, reference numeral 21 denotes an arithmetic unit consisting of n arithmetic units of different types of arithmetic operations. 14 is the instruction cell in FIG.
This is an instruction buffer that stores instructions. 18 is an instruction memory that stores the entire data flow program. 12
is a determination unit that determines the branch destination instruction cell when there is a branch instruction among the instruction cells in the instruction buffer 14. 13
is a control network (CNET) that activates the instruction cell in the instruction buffer 4 based on the result of the determination unit 12. 15 is a distribution network (DNET) that distributes data from the calculation unit 21 or the instruction memory 18 to each instruction cell in the instruction buffer 14; 16 is the instruction buffer 1;
An arbitration network (ANET
). Reference numeral 17 denotes an instruction cell of the instruction buffer 14 for reading from the instruction memory 18 or reading from the instruction memory 1.
When there is a write instruction to the instruction memory 18, the address data from the instruction cell in the instruction buffer 14 is arbitrated and the instruction memory 18
It is a memory command network (MNET) that sends to

In FIG. 3, the operation section in the instruction cell m is an addition (+)
, operation (-) 9 multiplication (x) 1 division (1).

Negative value ratio calculation (NEC), square calculation (↑), square root calculation (
Codes indicating operations such as SQRT) are stored. d
i and d2 are command cell numbers indicating the data movement destination. Operands are operand data.

In Figure 4, X of the quadratic equation ax2+bx+c=0
This shows the description of a data flow program for finding . The rectangular frame in the figure corresponds to the instruction cell m in FIG. 3, and the symbols within the frame indicate the aforementioned operations. The data of the arrow to that frame corresponds to the operand in FIG.

FIG. 5 shows a group of packets showing a data flow program for finding the root of the quadratic equation shown in FIG. 4 according to the description in the instruction cell shown in FIG.

The operation of the data-driven computer configured as described above will be explained below.

First, it is assumed that the packet group shown in FIG. 5 is stored in the instruction buffer 14 shown in FIG. In the packet group shown in FIG. 5, instruction cell 0 already stores a and C as operands, so it is activated when the program starts executing, and is sent to the multiplier in the calculation unit 21 through the ANET 16 shown in FIG. 2, where it is multiplied. is executed. The result is written to the instruction cell 2 through the DNET 15. At this point, instruction cell 2 is activated because the operand is prepared, and ANET
16 to the multiplier in the arithmetic unit 21. In addition, in parallel with the activation of instruction cell O, instruction cell 1, instruction cell 4,
The instruction cell 6 has been activated and execution of instructions has begun. In this way, each instruction cell executes in parallel to complete the program execution. (For example, Motooka Tatsum, VLsr Coy
Computer■, Iwanami Shoten, 1984゜PP7O-77) Problems to be Solved by the Invention However, in the above configuration, when multiple instruction cells in the instruction buffer 14 specify the same arithmetic unit and enter the activated state,
There is a problem in that execution waits occur in the arithmetic unit 21, which has one identical arithmetic unit, and the arithmetic unit 21 becomes a bolt neck, impairing the characteristics of parallel operation of a data-driven computer.

Furthermore, when processing large-scale array data, even though the memory access procedure is the same, an instruction cell must be prepared each time for memory access, resulting in a reduction in processing speed. There is.

Means for Solving the Problems In order to solve the above problems, the data-driven computer of the present invention has three main configurations. First, the arithmetic unit is composed of a plurality of types of arithmetic unit blocks, each of which is an arithmetic unit block that executes a plurality of identical operations. next,
In order to control the arithmetic unit, there is an arithmetic unit status register that indicates whether each arithmetic unit in each arithmetic unit block is running or not, and activated instruction cell data is assigned to an arithmetic unit that is not being executed based on the read result of the arithmetic unit status register. An arithmetic unit control section consisting of a control section is provided.

Furthermore, if there is an address pointer among the operands input to the arithmetic unit, a structure memory is provided from which data can be read and written using the pointer.

Effect of the Invention With the above-described configuration, the present invention allows, when a plurality of instruction cells simultaneously designate the same arithmetic unit, the arithmetic unit control section sequentially allocates the arithmetic units that are not currently being executed to execute the arithmetic operation without changing the structure of the instruction cell. This makes it possible to reduce execution waiting time, eliminate the bolt neck in the arithmetic unit that caused the problem mentioned above, and improve processing speed.

Furthermore, in the case of array data processing, processing speed can be improved because data can be accessed using the address pointer of the structure memory without preparing an instruction cell for memory access each time.

Embodiment Hereinafter, a data-driven computer according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of a data-driven computer in an embodiment of the present invention.

In FIG. 1, reference numeral 11 denotes an arithmetic unit that is composed of a plurality of types of arithmetic unit blocks, each of which is an arithmetic unit block that executes a plurality of identical operations, and that executes operations such as addition, subtraction, nine multiplications, and divisions. In order to control the arithmetic unit, reference numeral 19 includes an arithmetic unit status register that indicates whether each arithmetic unit in each arithmetic unit block is being executed or not, and an arithmetic unit that is not being executed based on the read result of the activated instruction cell data from the arithmetic unit status register. This is an arithmetic unit control unit consisting of a control unit assigned to the Reference numeral 181 denotes a structure memory from which data can be read and written using an address pointer, if one exists among the operands input to the calculation unit 11. FIG. 6 shows array data A, B, C (number of elements: 1) according to the description in the instruction cell of FIG.
A (r) = B (1) This is a packet group showing a program that executes IC(1) with element numbers I from 1 to 10 based on 0 pieces.

In the figure, Pi(A) means the address pointer value of element number i of array A.

The operation of the data-driven computer configured as described above will be explained below with reference to FIGS. 1 and 6.

First, it is assumed that the instruction packet group shown in FIG. 6 exists in the instruction memory 18. Next, the packet group is written to the instruction buffer 14 from the instruction memo January 8. Since each instruction cell is prepared with operand data, it is sequentially activated and sent to the arithmetic unit 11. The arithmetic unit 11 reads data from the structure memory 181 using the address pointer in each operand and writes the result of the operation to the structure memory 181 based on the destination address pointer. When performing arithmetic operations, the multiplication of each instruction cell is performed in parallel based on the control operation of the arithmetic unit control section 19.

Effects of the Invention As described above, according to the present invention, an arithmetic unit that executes a plurality of the same operations is used as an arithmetic unit block, an arithmetic unit constituted by a plurality of types of arithmetic unit blocks, and each arithmetic unit for controlling the arithmetic unit. an arithmetic unit control unit consisting of an arithmetic status register that indicates whether each arithmetic unit in the unit block is in execution; If there is an address pointer among the operands input to the section, the following effects can be obtained by providing a structure memory that can read and write data using the pointer.

When multiple instruction cells specify the same arithmetic unit at the same time,
By sequentially assigning arithmetic units that are not currently being executed in the arithmetic unit control unit and having them perform operations, execution wait time can be reduced and bolt necks in the arithmetic unit can be eliminated.In addition, in the case of array data processing, instruction cells for memory access can be allocated each time. Since data access can be efficiently executed using the address pointer of the structure memory without preparation, the processing speed of large-scale array data can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data-driven computer according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional data-driven computer, and FIG. 3 is a structural diagram of the instruction cell shown in FIGS. 1 and 2. , Figure 4 is a schematic diagram showing the description of a data flow program when calculating FIG. 6 is a schematic diagram of a packet group in which a data flow program is written. A (r
) =B (1) IC(I) with element number I from 1 to 1
FIG. 2 is an explanatory diagram of a packet group showing a program to be executed up to 0; 11... Calculation unit, 12... Judgment unit, 1
3... Control network (CNET), 14
...Instruction buffer, 15...Distribution network (DNET), 16...Arbitration network
Nodowork (ANET), 17...Memory Command Network (MNET), 18...
Instruction memory, 19... Arithmetic unit control unit, 181.
...Structure memory. Name of agent: Patent attorney Toshio Nakao Number 2 Figure 3 Figure 4 M = /, lo fOA (T = 8 (1) bowl C (1) 'E" f - evening 70 - 1 gram eight oki sa jinka e no te, P
)cormorant.

Claims (1)

[Claims] an arithmetic unit including at least one type of at least one arithmetic unit that executes the same arithmetic operation, an arithmetic unit status register that stores whether or not the arithmetic unit is in execution, and a read result of the arithmetic unit status register; A data-driven computer comprising: an arithmetic unit control unit comprising a control unit that allocates and executes operand data to an arithmetic unit that is not currently being executed; and a structure memory in which data can be accessed by an address pointer. .