JPS63110949U - - Google Patents

Info

Publication number
JPS63110949U
JPS63110949U JP20303586U JP20303586U JPS63110949U JP S63110949 U JPS63110949 U JP S63110949U JP 20303586 U JP20303586 U JP 20303586U JP 20303586 U JP20303586 U JP 20303586U JP S63110949 U JPS63110949 U JP S63110949U
Authority
JP
Japan
Prior art keywords
key
determining
predetermined time
execution
program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20303586U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP20303586U priority Critical patent/JPS63110949U/ja
Publication of JPS63110949U publication Critical patent/JPS63110949U/ja
Pending legal-status Critical Current

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  • Calculators And Similar Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の回路構成図、第2
図はアドレス制御部5の詳細回路図、第3図はA
Cキー10のキー出力が発生したときの処理フロ
ーを示す図である。 1…ROM、2…RAM(A)、4…RAM(
B)、5…アドレス制御部、7…演算中フラグ、
10…ACキー、11…演算部、22…復帰用ア
ドレスラツチ。
Figure 1 is a circuit configuration diagram of one embodiment of the present invention, Figure 2 is a circuit diagram of an embodiment of the present invention.
The figure is a detailed circuit diagram of the address control section 5, and FIG.
7 is a diagram showing a processing flow when a key output of the C key 10 occurs. FIG. 1...ROM, 2...RAM(A), 4...RAM(
B), 5...Address control section, 7...Calculating flag,
10... AC key, 11... Arithmetic unit, 22... Address latch for return.

Claims (1)

【実用新案登録請求の範囲】 所定のプログラムにしたがつて演算を実行する
と共に、実行中断キーが操作されると実行中の演
算を停止する小型電子機器において、 上記実行中断キーのキー出力時間を検出する検
出手段と、 この検出手段により検出された上記キー出力時
間が所定時間を越えているか否かを判断する判断
手段と、 上記実行中断キーが操作されたときの演算に対
するプログラム実行番地を記憶する記憶手段と、 上記判断手段が上記所定時間を越えていること
を判断した際には実行中の演算を停止させ、上記
所定時間を越えていないことを判断した際には上
記プログラム実行番地を上記記憶手段から読出し
て復帰させ、上記演算を継続させる処理手段とを
有することを特徴とする小型電子機器。
[Claims for Utility Model Registration] In a small electronic device that executes calculations according to a predetermined program and stops the calculation in progress when an execution interruption key is operated, the key output time of the execution interruption key is a detecting means for detecting; a determining means for determining whether the key output time detected by the detecting means exceeds a predetermined time; and storing a program execution address for the operation when the execution interrupt key is operated. and a memory means for storing the program execution address when the determining means determines that the predetermined time has exceeded, stops the operation being executed, and stores the program execution address when determining that the predetermined time has not been exceeded. A small electronic device characterized by comprising processing means for reading from and returning from the storage means and for continuing the above calculation.
JP20303586U 1986-12-29 1986-12-29 Pending JPS63110949U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20303586U JPS63110949U (en) 1986-12-29 1986-12-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20303586U JPS63110949U (en) 1986-12-29 1986-12-29

Publications (1)

Publication Number Publication Date
JPS63110949U true JPS63110949U (en) 1988-07-16

Family

ID=31167984

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20303586U Pending JPS63110949U (en) 1986-12-29 1986-12-29

Country Status (1)

Country Link
JP (1) JPS63110949U (en)

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