JPS63109564A - Multiple processing control system - Google Patents
Multiple processing control systemInfo
- Publication number
- JPS63109564A JPS63109564A JP25731386A JP25731386A JPS63109564A JP S63109564 A JPS63109564 A JP S63109564A JP 25731386 A JP25731386 A JP 25731386A JP 25731386 A JP25731386 A JP 25731386A JP S63109564 A JPS63109564 A JP S63109564A
- Authority
- JP
- Japan
- Prior art keywords
- processing unit
- input
- priority
- time
- processings
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012545 processing Methods 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 claims description 42
- 230000010365 information processing Effects 0.000 claims description 6
- 230000010354 integration Effects 0.000 claims 1
- 238000009825 accumulation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000007654 immersion Methods 0.000 description 1
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- Multi Processors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は情報処理装置における多重処理制御方式に関す
るもので、さらに詳しくは複数処理のディスパッチング
制御方式に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-processing control method in an information processing apparatus, and more specifically to a dispatching control method for multiple processes.
従来のディスパッチング制御方式では、優先順位を固定
的に処理単位に割り当て、これによって中央演算装置の
割り当てを行っていた。 ）〔発明が解決しよ
うとする問題点〕
上述した従来のディスパッチング制御方式は、各処理単
位がどのような処理特性を持っていても固定的に割り当
てられた優先順位に従って中央演算装置の割り当てを行
うため、各処理単位の処理特性に従ってあらかじめ最適
な優先順位を割り当てておかないと、スループットが悪
くなるという欠点がある。In conventional dispatching control systems, priorities are fixedly assigned to processing units, and central processing units are assigned based on this. ) [Problems to be Solved by the Invention] The conventional dispatching control method described above allocates central processing units according to fixedly assigned priorities, no matter what processing characteristics each processing unit has. Therefore, unless an optimal priority is assigned in advance according to the processing characteristics of each processing unit, the throughput will deteriorate.
本発明の目的は、上記欠点を除去し最適なディスパッチ
ングを可能とする多重処理制御方式を提供することにあ
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a multiprocessing control method that eliminates the above drawbacks and enables optimal dispatching.
本発明の多重処理制御方式の構成は、情報処理システム
の複数の処理単位を優先順位によって中央演算装置に割
り当てて実行せしめる多重処理制御方式において、前記
処理単位毎に対応して設けられた各処理単位の優先順位
を記憶する記憶域と、前記処理単位毎に対応して設けら
れた前記各処理単位が前記中央演算装置を使用した時間
を積算してこの積算時間を記憶する記憶域と、前記処理
単位毎に対応して設けられた前記各処理単位が実行した
入出力の実行回数を記憶する記憶域と、所定時間経過毎
に前記各処理単位毎の平均入出力間隔を前記積算時間及
び入出力回数を用いて算出する手段と、前記平均入出力
間隔に従って前記各処理単位をいくつかのグループに分
けそれぞれのグループの優先順位を変更する変更手段と
を設け、前記処理単位のそれぞれを前記中央演算装置の
使用時間及び入出力実行回数を積算しつつ前記優先順位
に従って前記中央演算装置を割り当てて実行せしめるよ
うにしたことを特徴とする。The configuration of the multiprocessing control method of the present invention is such that in the multiprocessing control method in which a plurality of processing units of an information processing system are assigned to a central processing unit according to priorities and executed, each processing unit is provided corresponding to each processing unit. a storage area for storing priority orders of units; a storage area provided corresponding to each processing unit for accumulating the time that each of the processing units used the central processing unit and storing the accumulated time; A storage area is provided corresponding to each processing unit to store the number of input/outputs executed by each processing unit, and the average input/output interval for each processing unit is stored in the accumulated time and the input/output interval. means for calculating using the number of outputs; and changing means for dividing each of the processing units into several groups according to the average input/output interval and changing the priority order of each group; The present invention is characterized in that the central processing unit is assigned and executed according to the priority order while integrating the operating time of the processing unit and the number of input/output executions.
効力式。Effect expression.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の多重処理制御方式を実現する情報処理
装置の一実施例のブロック図であり、中央演算装置の割
り当てを受ける処理Ｔ１〜Ｔ４を有する処理ファイルを
有し、各処理を優先順位に従って実行するための優先順
位制御部２、各処理の使用ＣＰＵ時間を積算する使用Ｃ
ＰＵ時間積算部３、各処理の入出力回数をカウントする
入出力回数カウント部４、経過時間制御タイマ部５、平
均入出力間隔計算部６、優先順位変更部７が設けられて
いる。FIG. 1 is a block diagram of an embodiment of an information processing device that implements the multiprocessing control method of the present invention, and has a processing file having processes T1 to T4 that are assigned to a central processing unit, and each process is prioritized. A priority control unit 2 for executing according to the order, and a usage C for accumulating the CPU time used for each process.
A PU time integrator 3, an input/output count section 4 that counts the number of inputs and outputs of each process, an elapsed time control timer section 5, an average input/output interval calculation section 6, and a priority change section 7 are provided.
各処理は使用ＣＰＵ時間積算領域Ｃｌ−０４を持ってお
り、各処理の使用ＣＰＵ時間は使用ＣＰＵ時間積算部３
によってこの領域に随時積算されていく。また、各処理
は入出力回数カウント１１〜Ｉ４を持っており、各処理
の入出力回数は入出力回数カウンタ部４によってこの領
域に随時カラン１へされていく。また、各処理は優先順
位の記憶領域Ｐ１〜Ｐ４を持っており、優先順位制御部
２はこの値によって各処理を中央演算装置に割り当てて
実行させる。Each process has a used CPU time accumulation area Cl-04, and the used CPU time of each process is calculated by the used CPU time accumulation section 3.
It is accumulated in this area from time to time. Further, each process has an input/output count 11 to I4, and the input/output count of each process is input to this area by the input/output count counter 4 as needed. Further, each process has priority storage areas P1 to P4, and the priority control unit 2 allocates each process to the central processing unit and executes it based on this value.
経過時間制御タイマ部５は、一定時間間隔毎に平均入出
力間隔計算部６分呼び出す。平均入出力間隔計算部６で
は、それぞれの処理の使用ＣＰＵ時間と入出力回数カウ
ンタ値から処理毎の平均入出力間隔を計算し、優先順位
変更部７を呼び出す。The elapsed time control timer section 5 calls the average input/output interval calculation section 6 minutes at regular time intervals. The average input/output interval calculating unit 6 calculates the average input/output interval for each process from the CPU time used for each process and the input/output count counter value, and calls the priority order changing unit 7.
優先順位変更部７は、平均入出力間隔の値に従ってそれ
ぞれの処理の優先順位を変更する。The priority change unit 7 changes the priority of each process according to the value of the average input/output interval.
次に、第１図を使って制御手順の詳細を説明する。ます
、各処理が処理をはじめて開始する時に、は南先順位値
、使用ＣＰＵ時間積算値、入出力回数カウンタが初期化
されなけらばならない。これはどの処理についても
Ｐ ＝ ｎ
Ｉ＝０
という値に初期１ヒされる。ここで、ｎはあらかじめ設
定されている固定値である。Next, details of the control procedure will be explained using FIG. First, when each process starts processing for the first time, the southern ranking value, the accumulated CPU time used, and the input/output count counter must be initialized. This is initially set to the value P=nI=0 for any process. Here, n is a fixed value set in advance.
初期化が行われた後、各処理は優先順位制御部２、使用
ＣＰＵ時間積算部３、入出力回数カウント部４を使い、
それぞれ非同期にＣＰＵ時間の割り当てを受けて処理を
続けて行く。一方、一定時間が経過すると経過時間制御
タイマ部５により平均入出力間隔計算部６が呼び出され
る。After initialization, each process uses the priority control unit 2, the CPU time usage unit 3, and the input/output count unit 4.
Each of them receives CPU time allocation asynchronously and continues processing. On the other hand, when a certain period of time has elapsed, the elapsed time control timer section 5 calls the average input/output interval calculation section 6.
第２図には本処理内部の制御手順を流れ図で示す。まず
、各処理毎の平均入出力間隔を求める。FIG. 2 shows a flowchart of the control procedure within this process. First, calculate the average input/output interval for each process.
次に、この大きさに従って各処理に番号を付ける。Next, number each process according to this size.
次に、各処理の使用ＣＰＵ時間積算領域および入出力回
数カウントの値を０にする。最後に、優先順位変更部を
呼び出して処理を終る。Next, the values of the used CPU time accumulation area and input/output count of each process are set to 0. Finally, the priority change unit is called to end the process.
第３図は南先順位変更部７内部の制御手順を流れ図で示
したものである。平均入出力間隔による各処理の順位ず
けが終った後で呼び出され、各処理の優先順位を変更す
る。変更はすべての処理を平均入出力間隔の値によって
２つに分け、平均入出力間隔の大きい処理をｎに、平均
入出力間隔の小さい処理をｎ−１に変更する。FIG. 3 is a flowchart showing the control procedure inside the south ranking change section 7. It is called after the ranking of each process based on the average input/output interval is finished, and the priority of each process is changed. The change is to divide all processes into two according to the value of the average input/output interval, and change the process with a large average input/output interval to n, and change the process with a small average input/output interval to n-1.
以」二説明したように本発明によれば、情報処理装置内
の複数の処理の特性を判定して最適な優先順位を割り当
てることにより、システム全体のスルーブッ１〜を向上
できる効果がある。As described above, according to the present invention, the throughput of the entire system can be improved by determining the characteristics of a plurality of processes within an information processing apparatus and assigning optimal priorities.
第１図は本発明の多重処理制御方式を実現する情報処理
装置の一実施例のブロック図、第２図は平均入出力間隔
計算部６の制御手順の流れ図、第３図は優先順位変更部
７の制御手順の流れ図である。
１・・・処理ファイル、２・・・優先順位制御部、３・
・・使用ＣＰＵ時間積算部、４・・・入出力回数カウン
ト部、５・・・経過時間制御タイマ、６・・・平均入出
力間隔計算部、７・・・優先順位変更部。
第１区
浸２区FIG. 1 is a block diagram of an embodiment of an information processing device that implements the multiprocessing control method of the present invention, FIG. 2 is a flowchart of the control procedure of the average input/output interval calculation section 6, and FIG. 3 is a priority change section. 7 is a flowchart of the control procedure of No. 7. 1... Processing file, 2... Priority control section, 3.
. . . Used CPU time accumulation unit, 4 . . . Input/output frequency counting unit, 5 . 1st ward immersion 2nd ward
Claims (1)
中央演算装置に割り当てて実行せしめる多重処理制御方
式において、前記処理単位毎に対応して設けられた各処
理単位の優先順位を記憶する記憶域と、前記処理単位毎
に対応して設けられた前記各処理単位が前記中央演算装
置を使用した時間を積算してこの積算時間を記憶する記
憶域と、前記処理単位毎に対応して設けられた前記各処
理単位が実行した入出力の実行回数を記憶する記憶域と
、所定時間経過毎に前記各処理単位毎の平均入出力間隔
を前記積算時間及び入出力回数を用いて算出する手段と
、前記平均入出力間隔に従って前記各処理単位をいくつ
かのグループに分けそれぞれのグループの優先順位を変
更する変更手段とを設け、前記処理単位のそれぞれを前
記中央演算装置の使用時間及び入出力実行回数を積算し
つつ前記優先順位に従って前記中央演算装置を割り当て
て実行せしめるようにしたことを特徴とする多重処理制
御方式。In a multiprocessing control method in which a plurality of processing units of an information processing system are assigned to a central processing unit according to priorities and executed, a storage area provided corresponding to each processing unit and storing the priority of each processing unit; a storage area provided corresponding to each processing unit for accumulating the time that each processing unit used the central processing unit and storing this accumulated time; and a storage area provided corresponding to each processing unit for storing the accumulated time. a storage area for storing the number of input/outputs executed by each processing unit; and means for calculating an average input/output interval for each processing unit every predetermined time period using the accumulated time and the number of input/outputs; changing means for dividing each processing unit into several groups according to an average input/output interval and changing the priority order of each group; A multi-processing control system characterized in that the central processing unit is assigned and executed according to the priority order while performing integration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25731386A JPS63109564A (en) | 1986-10-28 | 1986-10-28 | Multiple processing control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25731386A JPS63109564A (en) | 1986-10-28 | 1986-10-28 | Multiple processing control system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63109564A true JPS63109564A (en) | 1988-05-14 |
Family
ID=17304624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25731386A Pending JPS63109564A (en) | 1986-10-28 | 1986-10-28 | Multiple processing control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63109564A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03248257A (en) * | 1990-02-26 | 1991-11-06 | Nec Corp | Memory control system |
| JPH0830560A (en) * | 1994-07-13 | 1996-02-02 | Nec Corp | Load control system for computer system |
| KR101982447B1 (en) * | 2018-07-20 | 2019-08-28 | 세종대학교산학협력단 | Method for precessing i/o of virtual machine |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5636747A (en) * | 1979-09-03 | 1981-04-10 | Nec Corp | Dispatching system |
| JPS6016756A (en) * | 1984-05-31 | 1985-01-28 | Tamura Electric Works Ltd | Processing control system of device |
-
1986
- 1986-10-28 JP JP25731386A patent/JPS63109564A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5636747A (en) * | 1979-09-03 | 1981-04-10 | Nec Corp | Dispatching system |
| JPS6016756A (en) * | 1984-05-31 | 1985-01-28 | Tamura Electric Works Ltd | Processing control system of device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03248257A (en) * | 1990-02-26 | 1991-11-06 | Nec Corp | Memory control system |
| JPH0830560A (en) * | 1994-07-13 | 1996-02-02 | Nec Corp | Load control system for computer system |
| KR101982447B1 (en) * | 2018-07-20 | 2019-08-28 | 세종대학교산학협력단 | Method for precessing i/o of virtual machine |
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