JPS63109533U - - Google Patents
Info
- Publication number
- JPS63109533U JPS63109533U JP117287U JP117287U JPS63109533U JP S63109533 U JPS63109533 U JP S63109533U JP 117287 U JP117287 U JP 117287U JP 117287 U JP117287 U JP 117287U JP S63109533 U JPS63109533 U JP S63109533U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- current supply
- comparison
- supply circuit
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 2
Landscapes
- Emergency Protection Circuit Devices (AREA)
Description
第１図は本考案の電流制限回路の原理ブロツク
図、第２図は一実施例の電流制限回路のブロツク
図、第３図は一実施例の電流制限回路の信号波形
図、第４図は一実施例の過電流時の印加電圧およ
び供給電流特性図、第５図は保護抵抗を用いた電
流制限回路のブロツク図である。
図において、１は電源、２，２―１〜２―ｎは
装置、３は電流供給回路、４は保護抵抗、５はＭ
ＯＳ素子、８は比較回路、９はインヒビツト回路
、１０はスイツチ回路、１１は第１の比較器、１
２は遅延回路、１３はＯＲ回路、１４はＭＯＳ―
ＦＥＴ、１５は第２の比較器、１６は基準源、Ｌ
はコイルを示している。
Fig. 1 is a principle block diagram of the current limiting circuit of the present invention, Fig. 2 is a block diagram of a current limiting circuit of one embodiment, Fig. 3 is a signal waveform diagram of the current limiting circuit of one embodiment, and Fig. 4 is a block diagram of the current limiting circuit of one embodiment. FIG. 5 is a block diagram of a current limiting circuit using a protective resistor. In the figure, 1 is a power supply, 2, 2-1 to 2-n are devices, 3 is a current supply circuit, 4 is a protective resistor, and 5 is M
OS element, 8 is a comparison circuit, 9 is an inhibit circuit, 10 is a switch circuit, 11 is a first comparator, 1
2 is a delay circuit, 13 is an OR circuit, 14 is a MOS-
FET, 15 is the second comparator, 16 is the reference source, L
indicates a coil.
Claims (1)
流を供給するに際し、前記電流供給回路３に流れ
る過電流を制限する電流制限回路であつて、 前記電流供給回路３に過電流を制限するコイル
Ｌと、 前記装置２への供給電圧と基準電圧とを比較す
る比較回路８と、 該比較回路８の比較結果によつて前記電流供給
回路３を接、断するスイツチ回路１０と、 電源投入後の所定時間内での前記比較回路８の
出力と前記スイツチ回路１０の動作を制御するイ
ンヒビツト回路９とを備えて成ることを特徴とす
る電流制限回路。[Claims for Utility Model Registration] A current limiting circuit that limits overcurrent flowing through the current supply circuit 3 when supplying current from a power source 1 to the device 2 through the current supply circuit 3, the current supply circuit 3 comprising: A coil L that limits overcurrent; a comparison circuit 8 that compares the voltage supplied to the device 2 with a reference voltage; and a switch circuit that connects or disconnects the current supply circuit 3 depending on the comparison result of the comparison circuit 8. 10; and an inhibit circuit 9 for controlling the output of the comparison circuit 8 and the operation of the switch circuit 10 within a predetermined time after power is turned on.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP117287U JPS63109533U (en) | 1987-01-07 | 1987-01-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP117287U JPS63109533U (en) | 1987-01-07 | 1987-01-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63109533U true JPS63109533U (en) | 1988-07-14 |
Family
ID=30778829
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP117287U Pending JPS63109533U (en) | 1987-01-07 | 1987-01-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63109533U (en) |
-
1987
- 1987-01-07 JP JP117287U patent/JPS63109533U/ja active Pending
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