JPS63108773A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the displacement of a mask pattern by a method wherein the surface of a substrate to which a base layer is formed is coated with an insulating layer, an opening is shaped through selective removal, a polycrystalline silicon layer containing a diffusion source is laminated and sections except the polycrystalline silicon layer filled into be opening for an emitter are removed. CONSTITUTION:A base region 2 is shaped previously to the surface of a semicon ductor substrate 1, and a silicon oxide layer 3 is formed and a silicon nitride layer 4 is laminated, thus constituting an insulator layer. The insulator layer is removed selectively to shape an opening 5. A polycrystalline silicon layer 6 to which As is doped as a diffusion source and sections except the layer 6 filled into the opening 5 for an emitter are taken off, and As as the diffusion source is introduced into the region 2 from the opening for the emitter to form an emitter region 7. An emitter electrode 9 and a base electrode 8 are shaped, and a protruding section 10 is removed. Accordingly, the effect of the displace ment of a mask pattern for the polycrystalline silicon layer, side etching, etc. is removed, and the damage of the insulator layer due to etching can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, and is particularly suitable for high-frequency transistors.

(Prior Art) A method for manufacturing an npn-type bipolar transistor used as a high-frequency semiconductor element is explained with reference to FIG. 21 to about 200 by a known thermal oxidation method.
Form 0 people. This Si semiconductor substrate 20 is provided with a p-required region 23 which acts as a base layer in advance, and this silicon oxide layer 21 is selectively removed by a normal PEP method and used as an emitter and base contact, which will be described later. An opening 22... is provided (opening in Figure 1), and further As
PE after depositing the doped polycrystalline silicon layer 24 by CVD method.
Patterning is performed using the P method.

Through this step, the emitter opening is filled with the As-doped polycrystalline silicon layer 24 and the nearby silicon oxide 21
Then, this As is introduced into the Si semiconductor substrate to form an n-type emitter region 25 (Fig. Specifically, a layer of 1 μm is deposited using a sputtering method, and then a silicon oxide layer is deposited for approximately 3,000 layers, and then patterned using a PEP method to form electrodes 26° and 27. do. As a result, as shown in FIG.
remains, so this is further removed by etching and the second
The high frequency transistor shown in Figure 2 is completed.

(Problems to be Solved by the Invention) A high-frequency transistor, that is, a μ-wave transistor manufactured by the manufacturing method shown in FIG.
Since an extremely fine structure of m is required, the reality is that there is no margin for mask alignment in the PIEP process used for forming various patterns. For this reason, the base electrode 26 and the As-doped polycrystalline silicon layer 24 may be short-circuited, or the center of the polycrystalline silicon layer 24 may not coincide with the center of the opening 22, and the electrode A1 may be directly connected to the emitter region 25. There is also a risk that a phenomenon may occur if there is contact and piercing.

Since the above-mentioned fine pattern is required, the distance between the emitter electrode 27 and the base electrode 26 is narrow, less than 1.5 μm, and furthermore, since there is a protruding portion 28 of the polycrystalline silicon layer, the PUP process necessary for the electrode pattern forming process is required. This step difference causes resist residue and resist pattern thinning, resulting in a decrease in yield.

Furthermore, when etching the protruding portion 28 of the polycrystalline silicon layer, the emitter electrode 27 and the base electrode 2 are etched as described above.
The distance between 6 and 6 is narrow at 0.75 μm, and the polycrystalline silicon between them cannot be sufficiently confirmed, resulting in variations even if Justetch and B are performed. In addition, the insulation exposed by this etching process The present invention relates to a new method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks, and in particular eliminates the effects of mask pattern misalignment and side etching of the polycrystalline silicon layer, and further improves insulation by etching. The purpose is to eliminate damage to the material layer.

[Structure of the invention]

(Means for Solving the Problem) In order to achieve this object, the present invention further includes coating an insulating layer on the surface of a semiconductor substrate on which a base layer has been formed in advance, and then selectively removing the insulating layer to create a flower. A polycrystalline silicon layer containing a diffusion source is laminated, and then the polycrystalline silicon layer other than the polycrystalline silicon layer filled in the emitter hole is removed.

As a result of this removal step, most of the surface of the insulator layer has a laminated structure with the polycrystalline silicon layer, and a method of performing S emitter diffusion, deposition of metal for the A1 electrode, and patterning thereof was adopted. During this patterning, the polycrystalline silicon layer is also removed outside the AI main electrode.

(Function) As described above, in the method of the present invention, only the emitter opening is filled with the polycrystalline silicon layer containing the diffusion source and the base opening is filled with the polycrystalline silicon layer containing the diffusion source. A method is adopted in which A1 or A1 alloy for electrodes is deposited with the polycrystalline silicon layer remaining. Therefore, there is no need to worry about misalignment of the polycrystalline silicon layer filled in the emitter hole, and when etching the AI or A1 alloy layered thereon, it has the advantage of not directly damaging the insulating layer. The effect will be improved if the layers have a multi-layer structure. Furthermore, even if the distance between the emitter and the base electrode is extremely narrow as 0.75 μm, it is possible to perform etching while visually observing the polycrystalline silicon layer existing over the entire surface, which has the advantage of increasing accuracy.

(Example) An example of the present invention will be described in detail with reference to FIGS.

n-type semiconductor substrate 1 with ρ of 0.001 to 0.002Ω
Prepare an n+ resistivity of 0.65 to 0.75Ω1.
a shaped epitaxial layer (not shown) is provided in a conventional manner;
This is a region where a collector electrode of a μ-wave transistor to be described later will be formed.

After forming a base region 2 in advance with a surface concentration of about 5 x 10" atoms/cc by ion-implanting B into the n-region surface of the semiconductor substrate 1, a silicon oxide film with a thickness of about 2000 nm is deposited on this surface by a thermal oxidation method. After forming the layer 3, about 1700 silicon nitride layers 4 are stacked by CVD to form an insulating layer.

This insulating layer is selectively removed by a normal PEP method to provide openings 5... and a pitch of 5.5 is formed on a single wafer.
The emitter hole 5 is formed with a diameter of 0.6μ, and the distance between the base hole 5 adjacent to the emitter hole is 1.5μ. Form an ultra-fine pattern to maintain. (Figure 1A) Next, a polycrystalline silicon layer 6 doped with As as a diffusion source was deposited in an ultra-fine pattern with a thickness of 3800 mm as shown in Figure 1, and then the emitter opening was filled. Regular PEP for other items
This is removed by the process to obtain Figure 1(c), and As is a diffusion source is introduced into the base region 2 through this emitter opening to form a mouth-shaped emitter region 7 with a surface temperature of about 2×10” atoms/ce. .

Although only a single emitter region is shown in the southern region, it is of course possible to create a plurality of emitter regions as described above.

After this process, A1 for emitter electrode and base electrode
A thickness of approximately 1 μm is deposited by a sputtering method, and then a silicon oxide layer (not shown) is further coated by approximately 3,000 layers. This prevents pattern accuracy from decreasing due to damage to the resist during A1 patterning.

The silicon oxide layer is patterned by a normal PEP process, and then Al is patterned by RIE. The conditions are that A1 is etched using a 5iC1420SC with a power of 450 V and a pressure of 8 Pascal, but the polycrystalline silicon layer 6 adjacent to AI is patterned by making the Just Etching time about 10 minutes longer.

In this process, the polycrystalline silicon layer deposited on the opening surface with the base hole is visually observed.
Al-5i or Al-5L-Cu
It should be noted that this is also applicable.

By completing the patterning step A1, the μ-wave transistor shown in the first diagram is completed.

〔Effect of the invention〕

In the method of the present invention, a polycrystalline silicon layer containing a diffusion source is coated on a semiconductor substrate on which a base layer has been formed and an insulator layer has been patterned, and the emitter openings are closed and the base openings are closed. Since the polycrystalline silicon layer is present over the entire surface of the small gap, the darkened color can be determined visually, and the silicon nitride layer that makes up the surface of the insulating layer is not attacked by chlorine gas, making it possible to perform good etching. .

[Brief explanation of the drawing]

1A to 1H are cross-sectional views showing an embodiment according to the present invention in the order of steps, and FIG. 2I is a cross-sectional view showing a conventional process.

Claims (1)

[Claims] A process of coating an insulator layer on the surface of a semiconductor substrate of an opposite conductivity type having a region exhibiting a certain conductivity type, a process of selectively removing this insulator layer to form an opening, and a process of coating this insulator layer and exposed areas. a step of laminating a polycrystalline silicon layer containing a diffusion source in a conductivity type region; a step of removing this polycrystalline silicon layer filling another of the apertures located close to a part of the aperture; a step of introducing a diffusion source contained in the polycrystalline silicon layer filling a part of the opening into the certain conductivity type region to form a second opposite conductivity type region; A method for manufacturing a semiconductor device, comprising the steps of: forming an electrode continuous to the certain conductivity type region; and removing the polycrystalline silicon layer remaining between the two electrodes.