JPS63108244U - - Google Patents

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Publication number
JPS63108244U
JPS63108244U JP1986201134U JP20113486U JPS63108244U JP S63108244 U JPS63108244 U JP S63108244U JP 1986201134 U JP1986201134 U JP 1986201134U JP 20113486 U JP20113486 U JP 20113486U JP S63108244 U JPS63108244 U JP S63108244U
Authority
JP
Japan
Prior art keywords
signal level
resistor
monitor circuit
intermediate tap
level monitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986201134U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986201134U priority Critical patent/JPS63108244U/ja
Publication of JPS63108244U publication Critical patent/JPS63108244U/ja
Pending legal-status Critical Current

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  • Monitoring And Testing Of Transmission In General (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案による信号レベルモニタ回路の
一実施例を示す回路図、第2図は従来の信号レベ
ルモニタ回路を示す回路図である。 1……信号源、2……負荷、3……抵抗器、4
……測定器、T……トランス、R……信号源イ
ンピーダンス、RL……負荷インピーダンス、R
……抵抗値、A,B,C……端子、X……信号レ
ベル検出点。
FIG. 1 is a circuit diagram showing an embodiment of a signal level monitor circuit according to the present invention, and FIG. 2 is a circuit diagram showing a conventional signal level monitor circuit. 1...Signal source, 2...Load, 3...Resistor, 4
...Measuring instrument, T...Transformer, R g ...Signal source impedance, RL...Load impedance, R
...Resistance value, A, B, C...terminal, X...signal level detection point.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電気通信装置の信号レベル検出点と基準電位と
に巻線の両端がそれぞれ接続してあり中間タツプ
を有するオートトランスと、前記中間タツプに一
端が接続された抵抗器と、この抵抗器の他端に接
続された測定用端子とを備えることを特徴とする
信号レベルモニタ回路。
An autotransformer having both ends of a winding connected to a signal level detection point and a reference potential of a telecommunications device and having an intermediate tap, a resistor having one end connected to the intermediate tap, and the other end of the resistor. A signal level monitor circuit comprising: a measurement terminal connected to the signal level monitor circuit.
JP1986201134U 1986-12-27 1986-12-27 Pending JPS63108244U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986201134U JPS63108244U (en) 1986-12-27 1986-12-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986201134U JPS63108244U (en) 1986-12-27 1986-12-27

Publications (1)

Publication Number Publication Date
JPS63108244U true JPS63108244U (en) 1988-07-12

Family

ID=31164303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986201134U Pending JPS63108244U (en) 1986-12-27 1986-12-27

Country Status (1)

Country Link
JP (1) JPS63108244U (en)

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