JPS63107379A - Halftone image display device - Google Patents

Abstract

PURPOSE:To convert the time width of a digital signal with simple circuit constitution by providing an advantage for digital processing by constituting the picture elements of a display part in a matrix of 2<a> pieces vertically and 2<b> pieces laterally (a, b are positive integers), and providing memories corresponding to the number of the picture elements and a comparator capable of the on/off decision for data to a control circuit. CONSTITUTION:The control circuit 31 incorporated by a module 4 converts a data written in its frame memory 15 in combination with a unit 3 to a data having a prescribed time width, to supply it to an on/off decision part 16 that controls the display, so that a unit selection gate 19 is controlled. The reading of the content of the frame memory 15 to display the data and the writing of a data there to update the content of the display, are controlled by time division; an address for the writing and an address for the reading are selected by an address selector 43. In the display part, picture elements are arrayed in the matrix of 2<a>X2<b>. An address in the frame memory 15 is specified by means of signals lines in a-pieces in the vertical direction and b-pieces in the lateral direction that correspond to the (2<a>X2<b>) pieces of picture elements of the display part.

Description

Detailed Description of the Invention [Field of Industrial Application] This invention relates to a display device in which a large number of pixels are arranged in a matrix, and in particular to a halftone image for displaying an image of a signal having halftones such as a television signal. This invention relates to display devices.

[Conventional technology]

Conventionally, as an example of this type of large-screen display device, a display section is generally constructed by arranging a large number of single-pixel light-emitting elements using CT or light bulbs. In other words, a display device that performs color display has R, G, B
Three types of single pixel light emitting elements were regularly arranged, or a large number of single pixel light emitting elements including three colors of tGtB were arranged. These display devices consist of a unit made up of multiple light emitting elements and electronic circuits that drive them, and are made up of a display device in which a large number of each unit is arranged, a control device that controls the display, and a power supply device. C,
FIG. 9 is a configuration diagram showing an example of a conventional display device. In the figure, 30 is the screen of this display device, 3 is a unit as a component of this screen 30, 6 is a housing that accommodates a plurality of units 3 and constitutes the screen, 13 is a power supply, and 29 is a housing. This is a display control section that controls each unit 3 of the screen 30. FIG. 10 is a block diagram showing the configuration of the display control section 29, and in the figure, 26 is an analog-to-digital converter (hereinafter referred to as an A/D converter) that converts the input video signal into a digital signal. , 15 is a frame memory for storing a digitized video signal, 16 is an on/off determining unit connected to the frame memory 15, and 27 is a line connected to the on/off determining unit 16 for selecting 300 lines of the free text. A selection circuit, 2B is a column selection circuit that selects a column of the screen 30, 18 is an address control unit that controls addresses of this row selection circuit 27 and the frame memory 15, and 22 is this address control unit 18 and the A/D conversion circuit. A timing control section 32 for controlling the timing of the device 26 is a plurality of single pixel light emitting elements arranged in a grid to form the unit 3.

Next, the operation will be explained. First, a video signal input to this display device is converted into a predetermined digital signal by the A/D converter 26 and stored in the frame memory 15. The data stored in the frame memory 15 is read out according to the address corresponding to the single pixel light emitting element 32, sequentially converted into an on/off signal, and the data stored in the single pixel light emitting element 32 specified by the column selection circuit 28 and the row selection circuit 21C is read out.
supplied to Each single pixel light emitting element 32 has a memory function, and the on-off signal supplied to the single pixel light emitting element 32 is held until the signal is supplied again. The contents of the frame memory 15 are read out multiple times for each field, converted into predetermined on/off signals, and displayed. It is proportional to the amplitude of the signal. On the other hand, the screen 30 can have various sizes depending on how the units 3 are arranged, and the display control section 29 can control various screen sizes. That is, a light emitting element with a plurality of pixels arranged in a kx-e lattice is used as a light emitting part, and the light emitting element is mounted on a substrate together with a driving circuit.
Unit 3 is formed by arranging n grids,
Further, such two units 3 are arranged in a pxq grid to form a module together with a display control section 29 and a power supply 13 that control these units, and a screen is constructed by arranging a plurality of these modules. ing.

Moreover, FIG. 11 is a block diagram showing the overall configuration of FIG.
They are arranged in a horizontal grid of two (k, -e are positive integers). In the figure, the case where k=4 and A=4 is shown as an example. 3 has this light emitting element 1 in m pieces vertically and n pieces horizontally (m,
(n is a positive integer) units arranged in a lattice shape, and the figure shows an example where m=4 and n=4.

4 has this unit 3 vertically p units and horizontally q(r/d(p,
(q is a positive integer) Seven joules are arranged in a lattice pattern, and the figure shows an example of p=2*q=2.

5 is a module group in which this module 4 is arranged vertically, 6
is a casing, and 30 is a screen configured by arranging module groups 5 horizontally within a casing 6. The luminous cord 1
For example, the display device is a dot matrix display device such as a liquid crystal or a fluorescent display tube, and the display is controlled by combining two types of control poles, first and second, which are orthogonal to each other.

Next, the configuration will be explained using a fluorescent display tube as an example.

FIG. 12 is a schematic sectional view showing the internal groove structure of the fluorescent display tube. 9 is a cathode that emits thermoelectrons, 8 is a grid that accelerates electrons, 7 is an anode coated with fluorescent material), 1
0 is a wiring for applying voltage to the anode 7, 11 is an exhaust port, and 12 is an electrode for external connection. In this fluorescent display tube, a fluorescent substance coated on the surface of the anode 7 emits light when thermoelectrons from the cathode 9 collide with the anode 7, and the anode 7 is controlled by a voltage applied from a wiring 10. . Here, this anode 7 is connected to the first control #[
The grid 8 also corresponds to the second control electrode.

FIG. 13 is an explanatory diagram showing the configuration of control electrodes that control display, and the grid 8 has four electrodes Y1 to Y4 common in the row direction.
Furthermore, the four anodes 7, X1 to X4, are commonly connected in the column direction to form a matrix, and the display of the light emitting parts 2 arranged corresponding to the intersections of the two orthogonal control electrodes is controlled. . When configuring a full-color display device, use 几 (red) and G (green).

B (back) is used, in which the anode is regularly coated with a 3ffI class fluorescent substance. In particular, if the number of R, G, and B light emitting parts 2 is approximately: G: B = 1:2: l, and the pixel arrangement is as shown in Fig. 13, a color display device with an advantage in resolution can be obtained. .

As shown in FIG. 11, the unit 3 is constructed by arranging a light emitting element 1 of a plurality of pixels such as a fluorescent display tube and a drive circuit for the light emitting element 1 including a shift register, a latch, etc. on a substrate.

As shown in FIG. 14, the module 4 includes a plurality of units 3, a control circuit 31 that controls them, and a power supply 13.
It consists of In particular, as shown in FIG. 15, by arranging the control circuit 31 and the power supply 13 after the unit group forming the module 4, it is possible to make the system more compact. FIG. 16 is a block diagram showing the configuration of the control circuit 31. In the figure, 15 is a frame memory, 16 is an on/off determination unit connected to the frame memory 15, and 19 is a block diagram connected to the on/off determination unit 16. a unit selection gate connected to select unit 3;
Reference numeral 17 designates an address control section that controls the addresses of the frame memory 15, the on/off determination section 16, and the unit selection gate 19; and 17, a timing control section that controls the timing of the address control section 18.

Here, since it is difficult to directly transmit the digital video signal sampled at high speed to each module 4 using a flat cable, a plurality of modules 4 are connected by a common signal line 14 as shown in FIG. A module group 5 is formed by arranging a plurality of module groups 5 to form a screen 30. In addition, in the figure, 24 and 25 are the buffer and termination part of the common signal line 14, 26 is an A/D converter that converts the input video signal into a digital signal, and 21 is provided corresponding to the module group 5. a backup memory 2 that stores the digital video signal from the A/D converter 26 and performs speed conversion;
Reference numeral 2 denotes a timing generator for controlling the timing of the A/l) converter 26 and the backup memory 21, and 20 denotes a signal supply means constituted by these components.As shown in FIG. It is housed in the casing 6 together with a power distribution means 33 that distributes the power.

Next, the operation shown in FIG. 17 will be explained. First, the input video signal is sent to the A/D converter 26 of the signal supply means 20.
The signal is converted into a predetermined digital signal and temporarily stored in the backup memory 21 provided corresponding to each module group 5. The video signals stored in this buffer memory 21 are output one after another at a low speed, addresses are added, and the signals are individually sent to the corresponding module group 5. Each module group 5 receives the video signal in a buffer 24 and transmits it to each module 4 via a common signal line 14. here,
Since the video signal received by the buffer 24 is converted at low speed by the buffer memory 21 as described above, a flat cable can be used as the common signal line 14.

Each module 4 has an address, and inputs a corresponding portion of the video signal from a common signal line 14 according to the address. The input video signal is once written into the frame memory 15 of the control circuit 31 in FIG. Sent to Unit 3. Each unit 3 sends this video signal to each light emitting element 1 arranged in a grid pattern, causing a predetermined light emitting section 2 to emit light at a predetermined brightness.

FIG. 18 is a time chart of signals applied to the fluorescent display tube as the light emitting element 1. 4 grids 8 have X1~
Scanning signals with different timings are periodically inputted at X4, and predetermined video signals are inputted to the anode 7 in synchronization with the scanning signals at each of X1 to X4, causing the light emitting section 2 at the intersection thereof to emit light. In such a matrix type light emitting element 1, the display of each light emitting part 2 cannot be controlled individually, but it is controlled in a time division manner row by row according to a scanning signal, and continuous display is realized by increasing the scanning speed. There is.

Furthermore, displaying intermediate gradations is realized by changing the brightness of the light emitting section 2 by inputting a signal with a time width proportional to the amplitude of the video signal to the anode 7.

[Problem that the invention seeks to solve]

Conventional display devices have the same structure as described above, so in order to achieve high resolution, it is necessary to arrange grained single-pixel light-emitting elements at high density. The number of devices will be enormous, and the number of drive circuits and other peripheral circuits will also increase dramatically, but on the other hand, the cost reduction due to miniaturization of single pixel light emitting elements is small, and the number of drive circuits and other peripheral circuits will increase dramatically. Since similar peripheral circuits are used, there are problems in that it is extremely difficult to achieve high resolution, low cost, and light weight and thinness at the same time.

In addition, the process of converting digital data stored in memory into a predetermined time width is one of the most important signal processing processes for a display device, and the signal processing section, which was previously concentrated in one place, is now divided into modules. There were problems such as the division resulted in an expensive device.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a halftone image display device that can perform time width conversion of a digital signal with a simple circuit configuration.

[Failure to solve the problem]

In the display device according to the present invention, the number of pixels of the display section is 2a vertically.
, 2b on the side, and is configured to be advantageous for digital processing (a and b are positive integers), and the control circuit includes a memory corresponding to the number of pixels, a series of counters that successively divide the clock, and data on/off control. A comparator is provided to determine the frequency of the clock, and the frequency division value of the clock obtained as the output of the counter is assigned to a memory address and one input of the comparator, and the data read from the memory is sequentially compared in magnitude with the output of the counter. The obtained data representing "dog" or "small" (on or off) is arranged corresponding to the pixels using a clock.

[For production]

In the counter of the halftone image display device according to the present invention, the cumulative time during which the display of each pixel is all turned on during one cycle is proportional to the data in the corresponding memory.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the same parts as in FIG. 10 are indicated by the same reference numerals. In FIG. an address counter 42 driven by a signal outputting an inverted signal of DWT) and an output signal of the comparator 41 via a NAND circuit 45; and an address counter 43 that uses the output signal of the address counter 42 as one input signal. It has

Next, the operation will be explained. First, FIG. 1 is a block diagram of the control circuit 31 included in the module 4, which when combined with the unit 3 converts the data written in the frame memory 15 into a predetermined time width and controls the display. It has a function of supplying to the determination section 16 and controlling the unit selection gate 19.

Here, the content of the frame memory 15 is controlled by time and division between reading for displaying data and writing of data for updating the display contents, and an address selector 43 selects an address for writing and an address for reading. address is selected. Data is supplied through a common signal line 14 (data signal line, timing signal line DWT and ALE) and written to a predetermined address in the frame memory 15.

Addresses and data are multiplexed on the common signal line 14 to reduce the number of signal lines, and addresses and data are separated by two unique timing signal lines ALFJ and DWT. Predetermined data is written to the address. On the other hand, reading needs to be shown in correspondence with the configuration of the display section.

FIG. 2 shows a configuration diagram of the display section, in which 2b pixels are arranged in a matrix at 22 degrees vertically and horizontally. FIG. 3 shows a rewritten version of the part necessary for reading out the frame memory 15 of FIG. 1, that is, controlling the display. Here, it is assumed that the read address is selected as the address of the frame memory 15, and the address counter 43 is omitted.

Also, the frame memory 15 stores the number of pixels of the display section (2a x 2
Addresses are designated by vertical and horizontal (a-)-b) signal lines corresponding to b). Here, a=5, b=
5, and 10 bits from AO to A9 are used as the address. On the other hand, data is input and output using C bits.

This indicates that a 2° gradation halftone image can be displayed.

Here, the explanation will proceed assuming that C=6. 16 is an on/off determination unit that compares the magnitude relationship of 6-bit data. 1
7 is a timing control unit that controls clock generation, etc.;
18 consists of a series of counters that divide the clock,
The output of the address control unit and address counter 42, which has output (a-)-b-)-c) bits corresponding to the prime number 2a x 2b and the number of display gradations 2° of the display section, is sequentially XO'x4Iy2 from the lower bit. 〜y4IyOyllCO′C5, respectively. Here, XO"=X4TYO~y
4 represents the address of the frame memory 15, and each corresponds to the arrangement of pixels in the display section as shown in FIG. The display section is composed of four units 3 as shown in FIG. 11, and each unit is also composed of 16 light emitting elements 1. Each light emitting element 1 in each unit 3 is controlled by a drive circuit mounted on a common substrate.

FIG. 4 shows a part of the control circuit of the unit 3. The control circuit 31, which is equipped with such a circuit corresponding to each light emitting element 1, needs to send data to each unit individually, but the data, latch signal, and scanning signal are commonly transmitted to each unit, and the data is arranged. Sudame's clock CKl
~CKJ is transmitted individually for each unit. Each unit receives predetermined data using a corresponding clock.

Next, specific operations will be explained in detail. First, the output of the address control section 18 corresponds to the address of the frame memory 15, and the read data is immediately transferred to the data (CO to C5) of the on/off determination section 16, which is the output of the address control section 18. The magnitude relationship is compared, and if the data in the frame memory 15 is large, it becomes "1" (corresponding to pixel on), and if it is small, it becomes "o" (corresponding to pixel off).L bit on/off converted to data. This data is arranged into corresponding pixels of corresponding units by the clock. On the other hand, the address control unit 18 updates the address as it counts clocks, sequentially reads data from the frame memory 15, and repeats the above operation. In the wiring shown in FIG. 3, first, the data in the row indicated by Yl in FIG. 2 is converted into on-fist-off data and sequentially arranged in a shift register. Further - latched in unison and held for a predetermined period, the corresponding X electrodes (second control electrode group)
to drive. At the same time, the scanning electrode (control electrode) Yl is driven and lights up (here, the Y-4 poles are referred to as the first control electrode group). The address control unit 18 further counts Y2 and Ya as it counts the blacks and ticks.

The same operation as Y4 is repeated to complete displaying one screen of on/off binary images. The timing at this time is as shown in FIG. In FIG. 3, the upper digits of the address control unit 18 contain 6 bits of on/off determination data (CO to C5).
is assigned. This allows the above-mentioned binary image to be displayed (Co-Cr,
) means that it repeats 64 times from (0-0) to (lt). This is illustrated in the time chart of FIG. 5. In the figure, the periods in which the output (CO to C5) of the on/off determination unit 16 is from (0 to 0) to (1-1) are indicated by T1 to T64, respectively.

Here, T1 refers to the magnitude relationship between the data in the frame memory 15 and the comparison data (Co=C5)=(0 to 0) in the on/off determination unit 16, which are converted into on/off data and then converted into a binary image. This is the period displayed. '1゛2~
T64 is a period during which the contents of the frame memory 15 are converted into on/off data and displayed for each updated comparison data. In this way, while the address control unit 18 goes around once, the contents of the frame memory 15 are 64.
It is read out repeatedly υ times, respectively from (0 to O) to (1 to
The magnitude relationship is compared with 64 types of binary data updated by 1 up to 1), and each image is displayed as 64 binary images. Therefore, the display during one cycle of the address control unit 18 is proportional to the cumulative time that each pixel is turned on, and a 64-gradation halftone image is displayed.

On the other hand, TV signals are 1/60 in the case of NTSC (7).
The video of one field is switched during sec. Therefore, when displaying a television signal, the contents of the frame memory 15 are rewritten with one field worth of data every 1/6 osec. Therefore, by selecting the clock frequency so that the address control section 18 makes one cycle in 1/6oSec, it becomes possible to display the television signal in 64 gradations. Note that in the case of PAL, one field is 1150 seconds, so the clock frequency is 5/6 of that in the case of NTSC.

One embodiment of the present invention has been described above with reference to a display element whose display is controlled by dynamic drive of 1/4 duty. On the other hand, the present invention relates to the relationship between the number of pixels of the display section, the number of gradations of the halftone image, and the number of outputs of the address control section 18, and is effective regardless of the drive method of the display element. Various ways of allocating the output of 18 to the address or comparison data (Co=C5) are conceivable.

FIG. 6 is an explanatory diagram showing an example of how these assignments are made. (a) corresponds to FIG. 3, and the timing obtained is shown in FIG. 5. Since the rows specified by yoyt are scanned all at once, they are assigned to the upper digits of the counter. Figure 6 (bl is the allocation when controlling the display by dynamic drive with l/8 duty, and the timing at this time is as shown in Figure 7. In this case, 64 binary images are also superimposed. As a result, a halftone image is obtained. In FIG. 6(C), the display is controlled by dynamic drive with l/4 duty as in FIG. 3, but yoyl is assigned to the most significant digit. In this case, data is read out repeatedly 64 times during each period in which each scanning line is driven, time width conversion is performed for each scanning line, and display of 64 gray levels is completed in one scan.At this time, The timing is as shown in Figure 8.

〔Effect of the invention〕

As described above, according to the present invention, the number of pixels of the display section can be increased by 2 vertically.
Since the limit is set to a and 2b horizontally (a and b are positive integers) to be advantageous in terms of digital signal processing, the output of the address control section consisting of a series of binary counters can be effectively used as a control signal, and the With a simple circuit configuration, it is possible to efficiently control halftones during one cycle of the address control section. Furthermore, when the present invention is implemented as a control circuit for a module, the module control circuit itself is simplified, and the unit only needs to arrange one pit of data, and the unit also has a simple structure.
The effect can be seen in that large-screen displays can be significantly reduced in cost and made more compact.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a control circuit of a module according to an embodiment of the present invention, FIG. 2 is a diagram showing a display section to which the present invention is applied, and FIG. 3 is a block diagram of the display control section in FIG. 1. , FIG. 4 is a block diagram showing part of the control circuit of the unit, FIGS. 5 and 7. FIG. 8 is a time chart of the present invention, FIG. 6 is an application diagram of the present invention, FIG. 9 is a configuration diagram of a conventional display device, FIG. 10 is a block diagram of the control device and screen of FIG. 9, and FIG.
12 is an internal configuration diagram of a fluorescent display tube, FIG. 13 is an electrode matrix structure diagram of a fluorescent display tube, FIG. 14 is a block diagram of a module, and FIG. 15 is a screen diagram. 16 is a block diagram of the module control circuit, FIG. 17 is a block diagram showing the structure of the screen, and FIG. 18 is a time chart of signals input to the fluorescent display tube. In the figure, 1 is a light emitting element, 2 is a light emitting section, 3 is a unit, 4 is a module, 5 is a module group, 15 is a frame memory, 16 is an on/off determination section, 17 is a timing control section, and 18 is an address control section , 30 is the screen, 32
is a single pixel light emitting element. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent Applicant: Mitsubishi Electric Corporation (a) (b) (C) -N PQ Arm 10 1 To Notosu To To To To To × Figure 9 Figure 10 jO Niscreen Figure 12 Figure 13 Figure 14 Figure 15 Figure 16

Claims (4)

[Claims] (1) A display section in which pixels 2a vertically and 2b horizontally are arranged in a matrix, and 1-bit data indicating whether the pixel is on or off is arranged corresponding to the pixel and retained for a required period of time. It has a timing control section that drives the display section, and an output of (a+b+c) bits corresponding to the number of pixels of the display section, 2^a x 2^b, and the number of display gradations, 2^c, and has a clock speed of 1/1. From 2 (1/2)^a^+^b^+
an address control section that sequentially divides the frequency up to ^c;
1. A halftone image display device comprising: a frame memory whose address is specified by ) bits and into which c-bit data is input/output; and an on/off determination section that compares the magnitude relationship of the c-bit binary data. (2) The display section includes control electrodes that control the display section, including a first group of control electrodes commonly connected in the vertical direction and a second group of control electrodes commonly connected in the horizontal direction, 2. The halftone image display device according to claim 1, wherein the pixel is a display element or a set of display elements in which the pixel is arranged corresponding to the intersection of both control electrode groups. (3) The halftone image display device according to claim 1, wherein the address control section makes one round in synchronization with one field period of a television signal. (4) The halftone image display device according to claim 1, wherein the display device is configured in units of modules, and a plurality of modules are arranged to perform a series of displays.