JPS63106865A - Vectorizing method for loop including recurrent arithmetic calculation - Google Patents

Vectorizing method for loop including recurrent arithmetic calculation

Info

Publication number
JPS63106865A
JPS63106865A JP25404186A JP25404186A JPS63106865A JP S63106865 A JPS63106865 A JP S63106865A JP 25404186 A JP25404186 A JP 25404186A JP 25404186 A JP25404186 A JP 25404186A JP S63106865 A JPS63106865 A JP S63106865A
Authority
JP
Japan
Prior art keywords
vectorization
vectorized
loop
code
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25404186A
Other languages
Japanese (ja)
Inventor
Masaru Nakai
賢 中井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP25404186A priority Critical patent/JPS63106865A/en
Publication of JPS63106865A publication Critical patent/JPS63106865A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053Vector processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
  • Devices For Executing Special Programs (AREA)

Abstract

PURPOSE:To shorten an execution time, by performing a vector processing when possibility of vectorization exists by deciding it just before executing a loop, even when it is not decided whether the vectorization is possible or not at time of compilation. CONSTITUTION:A function which finds a vectorization possible condition at the time of detecting the loop including recurrent arithmetic calculation in a conventional vector complier, and the function which generates an object program which includes two kinds of codes, a vectorized code and a non- vectorized code, and selects either code by deciding the vectorization possibility at time of execution, are added. And a vector compiler providing with such vectorization system is stored in a main memory device 1, and the vectorization is executed by a central processor 3. As a result, source programs stored in large capacity memory devices 5 and 6 are converted to object programs, and all of the loops possible to be vectorized out of the loops including the recursive arithmetic calculation are executed with vectorized codes. In such as way, the execution time can be shortened.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、ベクトルコンパイラによる再帰演算を含むル
ープのベクトル化方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for vectorizing a loop including recursive operations using a vector compiler.

従来の技術 従来のベクトルコンパイラは、再帰演算を含むループに
関しては、プログラマによってベクトル化可能か否かと
いう情報が前もって与えられた場合にベクトル化を行う
2. Description of the Related Art Conventional vector compilers vectorize loops that include recursive operations when information as to whether or not they can be vectorized is given in advance by a programmer.

発明が解決しようとする問題点 しかし、実行時にならないとベクトル化可能か否かが判
定できないような再帰演算を含むループはベクトル化す
ることができないという問題点があった。たとえば下記
のような再帰演算を含むDOループをコンパイルする場
合を想定する。
Problems to be Solved by the Invention However, there has been a problem in that loops containing recursive operations cannot be vectorized, for which it cannot be determined whether vectorization is possible until execution time. For example, assume that a DO loop including the following recursive operation is to be compiled.

(1)    Do  10 1=L、M、N10  
A (I)=A (I+K) (2)    Do  10  I=1,10010 
 A (I+M)=A (I+N)(1)の例ではNと
Kの符号が同符号の場合、(2)の例ではM≦Nの場合
であれば再帰演算にならないので、ベクトル化可能であ
るが従来のベクトルコンパイラではコンパイル時にこれ
らの条件がわかっている場合でなければベクトル化する
ことができなかった。
(1) Do 10 1=L, M, N10
A (I)=A (I+K) (2) Do 10 I=1,10010
A (I+M)=A (I+N) In the example (1), if the signs of N and K are the same, and in the example (2), if M≦N, it is not a recursive operation, so vectorization is possible. However, with conventional vector compilers, these conditions must be known at the time of compilation to vectorize.

そこで本発明は、コンパイル時にベクトル化可能か否か
が判定できない場合であっても、そのル−プの実行直前
にベクトル化可能性を判定して可能な場合にはベクトル
処理を行うようにするものである。
Therefore, even if it is not possible to determine whether vectorization is possible at compile time, the present invention determines whether vectorization is possible immediately before execution of the loop and performs vector processing if possible. It is something.

問題点を解決するための手段 上記問題点を解決するための本発明の技術的な手段は従
来のベクトルコンパイラに、再帰演算を含むループを検
出した際にベクトル化可能条件を求める機能と、ベクト
ル化したコードとベクトル化しないコードの2種類のコ
ードを含み実行時に−・りトル化可能性を判定してどち
らのコードを実行するかを選択することができるような
目的プログラムを生成する機能を付加するものである。
Means for Solving the Problems The technical means of the present invention for solving the above problems is to add a function to a conventional vector compiler to obtain a vectorizable condition when a loop including a recursive operation is detected, and a vector compiler. A function that generates an objective program that contains two types of code: vectorized code and non-vectorized code, and can determine the rittleability at runtime and select which code to execute. It is an addition.

ここで言うベクトル化可能な場合とはループ中で変更し
た配列変数の値を用いて演算をおこなわない場合である
。また再帰演算式中にループ制御変数以外のループ中で
変化する変数を含む場合などはベクトル化不可能と判定
するものとする。
The case where vectorization is possible here refers to the case where no calculation is performed using the value of the array variable changed during the loop. Furthermore, if the recursive expression includes variables that change during the loop other than loop control variables, it is determined that vectorization is not possible.

作用 この技術的手段による作用は次のようになる。action The effect of this technical means is as follows.

ソースプログラム中に再帰演算を含むループが存在する
場合には上記のような目的プログラムが生成されるので
、実行時にその部分がベクトル化可能と判定された場合
にはベクトル化されたコードが選択実行され、実行時間
が短縮される。
If a loop containing a recursive operation exists in the source program, the above target program will be generated, so if that part is determined to be vectorizable at runtime, the vectorized code will be selected and executed. will reduce execution time.

実施例 以下、本発明の一実施例を図面を参照しながら説明する
EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

第1図は本発明を実施するだめのハードウェア構成の一
例を示すものである。第1図において1は主記憶装置、
2は記憶制御装置、3は中央処理装置、4はチャネルブ
ロセソザ、5と6は大記憶装置である。1の上記j61
装置に本発明のベクトル化方式を有したベクトルコンパ
イラを格納し、3の中央処理装置によってその実行を行
う。その結果、5の大記憶装置に格納しておいたソース
プログラムが目的プログラムに変換されて、6の大記憶
装置に格納される。
FIG. 1 shows an example of a hardware configuration for implementing the present invention. In FIG. 1, 1 is the main memory;
2 is a storage control unit, 3 is a central processing unit, 4 is a channel processor, and 5 and 6 are large storage units. 1 above j61
A vector compiler having the vectorization method of the present invention is stored in the device, and is executed by the central processing unit No. 3. As a result, the source program stored in the large storage device No. 5 is converted into a target program and stored in the large storage device No. 6.

第2図は、本発明のバク1−ル化方式を有したベクトル
コンパイラの機能ブロック図である。ソース解釈部は、
ソースプログラムを第1図・5の大記1q装置から入力
し、文を解釈して中間コードに変換する。記憶域割付部
は、プログラム中の各種データの番地割付を行う。ルー
プ検出部はプログラム中よりループの検出を行う。再帰
演算ループベクトル化部は、プログラム中より再帰演算
を含むループを取り出し、ベクトル化可能条件を求める
。目的プログラム出力部は、中間コードを目的プログラ
ムに変換して第1図・6の大記憶装置に出力する部分で
、再帰演算ループベクトル化部でベタ1−ル化可能条件
が求められた再帰演算を含むループに関しては、第4図
に示されるような処理の流れを持つ目的プログラムを生
成する。
FIG. 2 is a functional block diagram of a vector compiler having the backing method of the present invention. The source interpretation section is
A source program is input from the Daiki 1q device shown in Figure 1/5, and the sentences are interpreted and converted into intermediate code. The storage allocation unit performs address allocation for various data in the program. The loop detection section detects loops in the program. The recursive operation loop vectorization unit extracts a loop including a recursive operation from the program and determines vectorizable conditions. The target program output section converts the intermediate code into the target program and outputs it to the large storage device shown in Figure 1/6. As for the loop including the above, a target program having a processing flow as shown in FIG. 4 is generated.

第3図は、再帰演算ルーブベクl−ル化部における処理
の流れを示すものである。まず、ループの中の再帰演算
を検出する。これは、具体的にはループ実行中に変更し
た配列変数の値を用いて演算を行う可能性のある文の検
出を行っており、従来の技術で実現できる。
FIG. 3 shows the flow of processing in the recursive calculation rube vectorization section. First, a recursive operation in a loop is detected. Specifically, this detects a statement that may perform an operation using the value of an array variable changed during loop execution, and can be realized using conventional techniques.

再帰演算を検出した後、その再帰演算のベクI・ル化可
能条件を求める。これは左辺と右辺の配列変数の添字の
すべての組合せに対して次式を求め、その論理積をとる
ことによって得られる。
After detecting a recursive operation, the conditions under which the recursive operation can be converted into a vector are determined. This can be obtained by calculating the following equation for all combinations of subscripts of the array variables on the left and right sides, and then taking the logical product.

((右辺配列変数添字)−(左辺配列変数添字))×(
(ループ上限)−(ループ下限))≧0ただし、配列変
数の添字に含まれるループ制御変数以外の変数がループ
実行中に変化する場合、すなわちループ内でそのような
変数への代入がおこなわれている場合はベクトル化不可
能とみなすものとする。目的プログラム出力部では、こ
のベクトル化可能条件が求められたループに関しては、
ベクトル化したコードとベクトル化しないコードの両方
を含み実行時にこのベクトル化可能条件の判定結果に基
づいてどちらかのコードを選択実行できる目的プログラ
ムを生成する。この目的プログラムの処理の流れを第4
図に示す。
((Right side array variable subscript) - (Left side array variable subscript)) × (
(Loop upper limit) - (Loop lower limit)) ≧ 0 However, if a variable other than the loop control variable included in the subscript of the array variable changes during loop execution, that is, if such a variable is assigned within the loop. If so, it shall be considered that vectorization is not possible. In the target program output section, for the loop for which this vectorizable condition was found,
A target program is generated that includes both vectorized code and non-vectorized code, and can selectively execute either code at the time of execution based on the determination result of the vectorizable condition. The process flow of this purpose program is explained in the fourth section.
As shown in the figure.

例として、以下に示すような再帰演算を含むループを考
える。
As an example, consider a loop that includes a recursive operation as shown below.

Do  10  I=1.5 10  A H+M)=A (I+N)この場合、ベク
トル化可能条件は ((I +N)−(1+M))  x  (5−1) 
 ≧0によって得られるのでN2Mとなる。したがって
生成される目的プログラムのこの部分に関する処理の流
れは、第4図のベクトル化可能条件のところをN2Mで
おきかえたものになる。これを実行すると、この再帰演
算の実行直前にN2Mが満たされた場合にはベクトル化
されたコードが実行される。
Do 10 I=1.5 10 A H+M)=A (I+N) In this case, the vectorizable condition is ((I +N)-(1+M)) x (5-1)
Since it is obtained by ≧0, it becomes N2M. Therefore, the processing flow regarding this part of the target program to be generated is the same as that of the vectorizable condition in FIG. 4 replaced by N2M. When this is executed, if N2M is satisfied immediately before executing this recursive operation, the vectorized code will be executed.

発明の効果 以上述べてきたように、本発明には再帰演算を含むルー
プのうちベクトル化可能であるものはすべてベクトル化
されたコードで実行されるので、実行時間をかなり短縮
できるという効果がある。
Effects of the Invention As mentioned above, the present invention has the effect that execution time can be significantly reduced because all loops that include recursive operations that can be vectorized are executed using vectorized code. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明を実施するためのハードウェア構成図、
第2図は本発明のベクトル化方式を用いたベクトルコン
パイラの機能ブロック図、第3図は再帰演算ループベク
トル化部における処理の流れ図、第4図は目的プログラ
ムの再帰演算を含むループの部分の処理の流れ図である
。 ■・・・・・・主記憶装置、2・・・・・・記憶制御装
置、3・・・・・・中央処理装置、4・旧・・チャネル
プロセッサ、5゜6・・・・・・大記憶装置。 代理人の氏名 弁理士 中尾敏男 はが1名(’JC′
) IR派
FIG. 1 is a hardware configuration diagram for implementing the present invention,
Fig. 2 is a functional block diagram of a vector compiler using the vectorization method of the present invention, Fig. 3 is a flowchart of processing in the recursive operation loop vectorization section, and Fig. 4 is a flowchart of the loop portion including the recursive operation of the target program. It is a flowchart of processing. ■...Main storage device, 2...Storage control unit, 3...Central processing unit, 4.Old channel processor, 5゜6... Large storage device. Name of agent: Patent attorney Toshio Nakao ('JC')
) IR group

Claims (1)

【特許請求の範囲】[Claims] ソースプログラム中の再帰演算を含むループを検出して
ベクトル化可能条件を求める手段を具備し、ベクトル化
したコードとベクトル化しないコードの両方を含み実行
時にベクトル化可能性を判定してどちらかのコードを選
択実行することが可能であるような目的プログラムを生
成することを特徴とする再帰演算を含むループのベクト
ル化方法。
It is equipped with a means to detect vectorizable conditions by detecting loops including recursive operations in a source program, and includes both vectorized code and non-vectorized code, and determines vectorizability at runtime. A method for vectorizing a loop including a recursive operation, characterized by generating a target program in which code can be selectively executed.
JP25404186A 1986-10-24 1986-10-24 Vectorizing method for loop including recurrent arithmetic calculation Pending JPS63106865A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25404186A JPS63106865A (en) 1986-10-24 1986-10-24 Vectorizing method for loop including recurrent arithmetic calculation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25404186A JPS63106865A (en) 1986-10-24 1986-10-24 Vectorizing method for loop including recurrent arithmetic calculation

Publications (1)

Publication Number Publication Date
JPS63106865A true JPS63106865A (en) 1988-05-11

Family

ID=17259415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25404186A Pending JPS63106865A (en) 1986-10-24 1986-10-24 Vectorizing method for loop including recurrent arithmetic calculation

Country Status (1)

Country Link
JP (1) JPS63106865A (en)

Similar Documents

Publication Publication Date Title
US4710872A (en) Method for vectorizing and executing on an SIMD machine outer loops in the presence of recurrent inner loops
US4821181A (en) Method for converting a source program of high level language statement into an object program for a vector processor
EP0533813B1 (en) Method for representing scalar data dependencies for an optimizing compiler
JP2500079B2 (en) Program optimization method and compiler system
US5598561A (en) Optimizing compiler which generates multiple instruction streams to be executed in parallel
CN104641351B (en) Part vectorization compiling system
JPH0475139A (en) Loop parallelizing system
JPH06324881A (en) Compiler device with superposition deciding function of memory data
US6425124B1 (en) Resource allocation device for reducing the size and run time of a machine language program
US5850551A (en) Compiler and processor for processing loops at high speed
US6282704B1 (en) Method for analyzing array summary for loop including loop exit statement
JPS63106865A (en) Vectorizing method for loop including recurrent arithmetic calculation
JPS63111578A (en) Method for transforming loop including recursive arithmetic into vector
JPH0440742B2 (en)
JP3412323B2 (en) Vectorization processing device
JPS6367676A (en) Processing system for vector formation from general loop
JPS63120367A (en) Program transformation device
JP2853604B2 (en) Vectorization processing method of infinite loop
JP2901720B2 (en) Object code comparison method
JP3658771B2 (en) Compiler device
JP2870218B2 (en) Parallel execution instruction sequence generation method
JPH0455945A (en) Compiled code output system for generation of nonlocal outlet function frame
JPH01263574A (en) Apparatus for automatically forming test pattern program
JPH04332044A (en) Vectorization processing system for compiler
JPS61285544A (en) Program executing method