JPS6310617U - - Google Patents

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Publication number
JPS6310617U
JPS6310617U JP10351486U JP10351486U JPS6310617U JP S6310617 U JPS6310617 U JP S6310617U JP 10351486 U JP10351486 U JP 10351486U JP 10351486 U JP10351486 U JP 10351486U JP S6310617 U JPS6310617 U JP S6310617U
Authority
JP
Japan
Prior art keywords
amplifier
output signal
amplifies
signal
logarithmic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10351486U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10351486U priority Critical patent/JPS6310617U/ja
Publication of JPS6310617U publication Critical patent/JPS6310617U/ja
Pending legal-status Critical Current

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  • Amplifiers (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の増幅回路の原理ブロツク図、
第2図は一実施例の増幅回路の信号波形図、第3
図は一実施例の増幅回路のブロツク図、第4図は
対数増幅器の特性図、第5図は従来の増幅回路の
ブロツク図である。 図において、1は目標物体、2は検知器、3は
第1の増幅器、4は表示器、5は対数増幅器、6
は減算回路、7は第2の増幅器を示している。
Figure 1 is a block diagram of the principle of the amplifier circuit of the present invention.
Figure 2 is a signal waveform diagram of the amplifier circuit of one embodiment;
FIG. 4 is a block diagram of an amplifier circuit according to an embodiment, FIG. 4 is a characteristic diagram of a logarithmic amplifier, and FIG. 5 is a block diagram of a conventional amplifier circuit. In the figure, 1 is a target object, 2 is a detector, 3 is a first amplifier, 4 is a display, 5 is a logarithmic amplifier, and 6
7 indicates a subtraction circuit, and 7 indicates a second amplifier.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号をほぼ直線状に増幅する増幅器3と、
前記増幅器3の出力信号を対数状に増幅する対数
増幅器5と、前記増幅器3の出力信号から前記対
数増幅器5の出力信号を減算する減算回路6とよ
り構成されて成ることを特徴とする信号対雑音比
の改善増幅回路。
an amplifier 3 that amplifies the input signal substantially linearly;
A signal pair comprising a logarithmic amplifier 5 that logarithmically amplifies the output signal of the amplifier 3, and a subtraction circuit 6 that subtracts the output signal of the logarithmic amplifier 5 from the output signal of the amplifier 3. Amplification circuit with improved noise ratio.
JP10351486U 1986-07-04 1986-07-04 Pending JPS6310617U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10351486U JPS6310617U (en) 1986-07-04 1986-07-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10351486U JPS6310617U (en) 1986-07-04 1986-07-04

Publications (1)

Publication Number Publication Date
JPS6310617U true JPS6310617U (en) 1988-01-23

Family

ID=30976140

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10351486U Pending JPS6310617U (en) 1986-07-04 1986-07-04

Country Status (1)

Country Link
JP (1) JPS6310617U (en)

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