JPS63104548A - Bias circuit - Google Patents

Bias circuit

Info

Publication number
JPS63104548A
JPS63104548A JP24998786A JP24998786A JPS63104548A JP S63104548 A JPS63104548 A JP S63104548A JP 24998786 A JP24998786 A JP 24998786A JP 24998786 A JP24998786 A JP 24998786A JP S63104548 A JPS63104548 A JP S63104548A
Authority
JP
Japan
Prior art keywords
switch
input
terminal
modulation signal
modulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24998786A
Other languages
Japanese (ja)
Other versions
JPH0724408B2 (en
Inventor
Tomonori Shiomi
智則 塩見
Yoshio Horiike
良雄 堀池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP24998786A priority Critical patent/JPH0724408B2/en
Publication of JPS63104548A publication Critical patent/JPS63104548A/en
Publication of JPH0724408B2 publication Critical patent/JPH0724408B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Amplitude Modulation (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To prevent the aperture efficiency of the eye parttern of a modulation signal from being deteriorated and also a transition state just after transmission begins from being generated constituting a bias circuit only with resistances and a switch and not using a capacitor which obstructs a direct current. CONSTITUTION:A titled circuit has the resistances 3-6 and the switch 7 and in case of reception the switch 7 is made in ON state so as to keep an input terminal 1 in the same electric potential as a second reference voltage terminal(earth) and meanwhile in case of transmission the switch 7 is turned OFF so as to input the modulation signal in the input terminal 1 and obtain the outputs from connection point of first and second registances 3 and 4. Thus the aperture efficiency of the eye pattern of the modulation signal inputted in a modulator 9 is not deteriorated and the transition state does not occur just after the transmission begins, since the capacitor is not used, which obstructs the direct current and causes time constant.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、通信機の変調器に用いることができるバイア
ス回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a bias circuit that can be used in a modulator of a communication device.

従来の技術 近年、データ通信が急速に普及し、通信品質の鍵を担う
変調器にも、その高性能化が求められている。
BACKGROUND OF THE INVENTION In recent years, data communications have rapidly become widespread, and modulators, which play a key role in communication quality, are required to have higher performance.

以下、図面を参照しながら、従来のバイアス回路の一例
について説明する。第3図は従来のバイアス回路のブロ
ック図であり、11は変調信号を入力する入力端子、1
2は電源端子、13は入力端子11に入力された変調信
号の直流分を阻止するコンデンサ、14および15は後
段の回路にバイアス電圧を与える抵抗、16はコンデン
サ13にて直流分を除かれた変調信号を入力し変調を行
う変調器、17は変調器16の出力端子である。
An example of a conventional bias circuit will be described below with reference to the drawings. FIG. 3 is a block diagram of a conventional bias circuit, in which 11 is an input terminal for inputting a modulation signal;
2 is a power supply terminal, 13 is a capacitor that blocks the DC component of the modulation signal input to the input terminal 11, 14 and 15 are resistors that provide a bias voltage to the subsequent circuit, and 16 is the capacitor 13 that removes the DC component. A modulator 17 is an output terminal of the modulator 16 which inputs a modulation signal and performs modulation.

以上のように構成されたバイアス回路について、その動
作を倫理“1”と“0”のNRZ信号が変調信号として
入力されたとして説明する。ここでは、電源端子に加え
る電圧を■、とし、抵抗14および15は等しいものと
する。第4図の波形図で示すように倫理“1”と“0″
からなる変調信号(a)を入力端子11に入力する。入
力された変調信号(a)はコンデンサ13と抵抗14お
よび15の時定数に応じた微分効果により、変調信号(
b)に示す波形となり変調器16へ入力される。変調器
16では入力信号(b)に応じた変調を行い、出力端子
17より出力する。
The operation of the bias circuit configured as described above will be explained assuming that NRZ signals of ethics "1" and "0" are input as modulation signals. Here, it is assumed that the voltage applied to the power supply terminal is 2, and that the resistors 14 and 15 are equal. As shown in the waveform diagram in Figure 4, ethics “1” and “0”
A modulated signal (a) consisting of the following is input to the input terminal 11. The input modulation signal (a) is transformed into a modulation signal (
The waveform becomes as shown in b) and is input to the modulator 16. The modulator 16 modulates the input signal (b) and outputs it from the output terminal 17.

発明が解決しようとする問題点 しかしながら、上記のような構成では、変調器16はコ
ンデンサ13と抵抗14および15の時定数に応じた信
号fb)にて変調を行うため、コンデンサ13の容量値
が小さいと、信号(b)の時間t2からt3までの間に
みられるような倫理“1”あるいは“0”が連続した場
合のアイパターンの開口率が劣化し、またそれを防ぐた
め、容量値を大きくすると送信開始時間t1直後からの
過渡状態の時間が長くかかり、この部分で復調時に著し
い歪が発生し、倫理レベルの判定が困難になるという問
題点を有していた。
Problems to be Solved by the Invention However, in the above configuration, since the modulator 16 performs modulation using the signal fb) corresponding to the time constants of the capacitor 13 and the resistors 14 and 15, the capacitance value of the capacitor 13 is If it is small, the aperture ratio of the eye pattern will deteriorate when the ethics "1" or "0" are consecutive as seen from time t2 to t3 of signal (b), and to prevent this, the capacitance value If the value is increased, the transient state immediately after the transmission start time t1 takes a long time, and significant distortion occurs during demodulation in this portion, making it difficult to determine the ethical level.

本発明は上記問題点に鑑み、変調器へ入力される変調信
号のアイパターンの開口率を劣化させず、かつ送信開始
直後の過渡状態も発生せしめないバイアス回路を提供す
るものである。
In view of the above-mentioned problems, the present invention provides a bias circuit that does not deteriorate the aperture ratio of the eye pattern of the modulated signal input to the modulator and does not cause a transient state immediately after the start of transmission.

問題点を解決するだめの手段 上記問題点を解決するために、本発明のバイアス回路は
、2つの基準電圧を与える第1と第2の基準電圧端子と
、前記第1と第2の基準電圧の中点電圧を中心に変化す
る変調信号を入力する入力端子と、前記第1と第2の基
準電圧端子の間に直列に接続した第1と第2の抵抗と、
前記第1と第2の抵抗の接続点と前記入力端子との間に
接続した第3の抵抗と、前記第1と第2の抵抗の接続点
と前記第1の基準電圧端子との間に直列に接続した第4
の抵抗とスイッチを具備し、受信時には前記スイッチを
ON状態にして、なおかつ前記入力端子を前記第2の基
準電圧端子と同電位に保ち、送信時には、前記スイッチ
をOFF状態にして、なおかつ前記入力端子に前記変調
信号を入力し、前記第1と第2の抵抗の接続点から、出
力を得るという構成を備えたものである。
Means for Solving the Problems In order to solve the above problems, the bias circuit of the present invention has first and second reference voltage terminals that provide two reference voltages, and an input terminal for inputting a modulation signal that changes around a midpoint voltage; and first and second resistors connected in series between the first and second reference voltage terminals;
a third resistor connected between the connection point between the first and second resistors and the input terminal; and between the connection point between the first and second resistances and the first reference voltage terminal. 4th connected in series
The switch is equipped with a resistor and a switch, and when receiving, the switch is turned on and the input terminal is kept at the same potential as the second reference voltage terminal, and when transmitting, the switch is turned off and the input terminal is kept at the same potential as the second reference voltage terminal. The modulation signal is input to a terminal, and an output is obtained from a connection point between the first and second resistors.

作用 本発明は上記した構成によって、時定数を生じる要因と
なった直流を阻止するコンデンサを用いないため、変調
器へ入力される変調信号のアイパターンの開口率が劣化
せず、かつ送信開始直後の過渡状態も生じないこととな
る。
Effect of the Invention With the above-described configuration, the present invention does not use a capacitor to block the direct current that causes the time constant, so the aperture ratio of the eye pattern of the modulated signal input to the modulator does not deteriorate, and the aperture ratio of the eye pattern of the modulated signal input to the modulator does not deteriorate immediately after the start of transmission. This means that no transient state occurs.

実施例 以下、本発明の一実施例であるバイアス回路について、
図面を参照しながら説明する。
Example Below, regarding a bias circuit which is an example of the present invention,
This will be explained with reference to the drawings.

第1図は本発明のバイアス回路の一実施例を示すブロッ
ク図である。第1図において、1は変調信号を入力する
入力端子、2は電源端子、3および4は後段の回路にバ
イアス電圧を与える抵抗、5および6は受信時にバイア
ス電圧を与える抵抗、7はスイッチ、8はスイッチ7を
制御する制御端子、9は抵抗3および4にてバイアス電
圧を与えられた変調信号を入力し変調を行う変調器、1
0は変調器9の出力端子である。
FIG. 1 is a block diagram showing one embodiment of the bias circuit of the present invention. In FIG. 1, 1 is an input terminal for inputting a modulation signal, 2 is a power supply terminal, 3 and 4 are resistors that apply a bias voltage to the subsequent circuit, 5 and 6 are resistors that apply a bias voltage during reception, 7 is a switch, 8 is a control terminal for controlling the switch 7; 9 is a modulator for inputting a modulation signal applied with a bias voltage through resistors 3 and 4 for modulation; 1;
0 is the output terminal of the modulator 9.

以上のように構成されたバイアス回路について、その動
作を倫理“1”と“0”のNRZ信号が変調信号として
入力されたとして説明する。ここでは電源端子2に加え
る電圧を■1とし、抵抗3および4は等しく抵抗値はR
I、抵抗5および6も等しく抵抗値はR2とする。また
スイッチ7は制御端子8が倫理“l”のときON状態と
なり、倫理“0”のときOFF状態となるものとする。
The operation of the bias circuit configured as described above will be described assuming that NRZ signals of ethics "1" and "0" are input as modulation signals. Here, the voltage applied to power supply terminal 2 is assumed to be 1, and resistors 3 and 4 are equal in resistance value R.
It is assumed that resistors 5 and 6 have the same resistance value R2. Further, it is assumed that the switch 7 is in an ON state when the control terminal 8 is in the logic "1" and in an OFF state when the logic is in "0".

また制御端子8に受信時には倫理“1”、送信時には倫
理“O”を入力するものとする。まず、第2図の波形図
で示すように時間t1およびt4以降は受信、時間゛t
Iからt4の間は送信とし、波形図(a)で示すような
倫理“1”と“0”からなる変調信号を入力端子lへ入
力する。制御端子8には前記のとおり制御信号(b)を
入力する。まず受信時には、入力端子1に倫理“0”が
入力され、かつスイッチ7がON状態になるので変調器
9の入力信号(C)はVl/2となる。次に送信時には
、入力端子1に変調信号が入力され、かつスイッチ7が
OFF状態になるので、変調器9にはV I/2の中点
電圧としてR1/ (R1+2R2)の振幅を持つ信号
(C)が入力されることになる。
It is also assumed that ethics "1" is input to the control terminal 8 during reception and ethics "O" is input during transmission. First, as shown in the waveform diagram of FIG. 2, reception is received after time t1 and t4, and
During the period from I to t4, transmission is performed, and a modulated signal consisting of ethical "1" and "0" as shown in the waveform diagram (a) is input to the input terminal l. The control signal (b) is input to the control terminal 8 as described above. First, at the time of reception, the logic level "0" is input to the input terminal 1 and the switch 7 is turned on, so that the input signal (C) of the modulator 9 becomes Vl/2. Next, at the time of transmission, a modulation signal is input to the input terminal 1 and the switch 7 is turned off, so the modulator 9 receives a signal ( C) will be input.

以上のように本実施例によれば、抵抗とスイッチのみで
バイアス回路を構成し、直流阻止のコンデンサを用いて
いないので時定数が生じず、時間t2からt3までの間
にみられるような倫理“1″あるいは“0”が連続した
場合でもアイパターンの開口率の劣化は、全く発生しな
い。また、送信開始時間1.直後からの過渡状態も全く
発生しない。また、変調器9への入力信号の振幅は抵抗
3.4および6の抵抗値によりきまるので、これらを変
えることにより変調器9の変調度を任意に設定すること
ができる。また、受信時には変調器9への入力信号はV
+/2に固定され変調器9の出力には変調がかからない
ため、この出力を受信器の局部発振信号としても利用で
きる。
As described above, according to this embodiment, the bias circuit is configured with only resistors and switches, and no DC blocking capacitor is used, so there is no time constant, and the ethical problem seen between time t2 and t3 is avoided. Even when "1" or "0" is continuous, the aperture ratio of the eye pattern does not deteriorate at all. Also, transmission start time 1. No transient state occurs immediately after. Further, since the amplitude of the input signal to the modulator 9 is determined by the resistance values of the resistors 3.4 and 6, the degree of modulation of the modulator 9 can be arbitrarily set by changing these values. Also, during reception, the input signal to the modulator 9 is V
Since it is fixed at +/2 and no modulation is applied to the output of the modulator 9, this output can also be used as a local oscillation signal of the receiver.

なお、本実施例において、スイッチ7はトランジスタ、
ゲートIC等を用いて簡単に構成できる。
Note that in this embodiment, the switch 7 is a transistor,
It can be easily constructed using a gate IC or the like.

また、制御端子8に加える制御信号(b)もマイコン、
ゲートIC等で簡単に発生させることができる。
Furthermore, the control signal (b) applied to the control terminal 8 is also controlled by the microcomputer.
This can be easily generated using a gate IC or the like.

なお、本実施例において、電源端子2に電源電圧■、を
加え、抵抗4の一端をアースとしたが、この2つは基準
となる電圧であればなんでもよい。
In this embodiment, the power supply voltage (2) is applied to the power supply terminal 2, and one end of the resistor 4 is grounded, but any voltage may be used as long as these two voltages serve as a reference voltage.

また、変調信号を倫理“1”が■1、倫理“0”がOの
矩形波としたが、前記2つの基準電圧の中点電圧を中心
に変化する信号であれば何でもよい。
In addition, although the modulation signal is a rectangular wave with ethics "1" being 1 and ethics "0" being O, any signal may be used as long as it changes around the midpoint voltage of the two reference voltages.

また、抵抗3および4を等しいとしたが、これはシステ
ムを設計する際、変調器入力信号の振幅変動許容範囲に
入るならば、バラツキがあってもよい。また、抵抗5お
よび6も等しいとしたが、これもシステムを設計する際
、変調器入力信号の振幅変動許容範囲に入るならば、バ
ラツキがあって以上のように本発明は、抵抗とスイッチ
のみでバイアス回路を構成し、直流阻止のコンデンサを
用いていないため、倫理″1″あるいはo”が連続した
場合でもアイパターンの開口率の劣火が全く発生せず、
また送信開始直後の過渡状態も発生しないという優れた
効果が得られる。さらに、抵抗値を変えることにより変
調器の変調度を任意に設定でき、また受信時には変調器
の出力を受信器の局部発振信号としても利用できるとい
う効果も得られる。
Further, although the resistors 3 and 4 are assumed to be equal, they may vary as long as the amplitude fluctuations of the modulator input signal are within the permissible range when designing the system. In addition, resistors 5 and 6 are also assumed to be equal, but when designing the system, if the amplitude fluctuation of the modulator input signal is within the tolerance range, there will be variations, and as described above, the present invention can be applied only to the resistors and switches. Since the bias circuit is configured with , and no DC blocking capacitor is used, there is no underfire of the eye pattern aperture ratio even if the ethics "1" or "o" are repeated.
Further, an excellent effect can be obtained in that no transient state occurs immediately after the start of transmission. Furthermore, by changing the resistance value, the modulation degree of the modulator can be set arbitrarily, and the output of the modulator can also be used as a local oscillation signal of the receiver during reception.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例のブロック図、第2図(a)
 (b) (C)は本発明の一実施例の各部波形図、第
3図は従来のバイアス回路のブロック図、第4図(al
(blは従来のバイアス回路の各部波形図である。 1・・・・・・変調信号の入力端子、2・・・・・・電
源端子、3および4・・・・・・後段の回路にバイアス
電圧を与える抵抗、5および6・・・・・・受信時にバ
イアス電圧を与える抵抗、7・・・・・・スイッチ、8
・旧・・スイッチの制御端子、9・・・・・・変調器、
10・・・・・・変調器の出力端子。 代理人の氏名 弁理士 中尾敏男 はか1名第1図 tt         tz     乙s    t
p♂
Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2(a)
(b) (C) is a waveform diagram of each part of an embodiment of the present invention, FIG. 3 is a block diagram of a conventional bias circuit, and FIG.
(bl is a waveform diagram of each part of a conventional bias circuit. 1... Input terminal for modulation signal, 2... Power supply terminal, 3 and 4... For subsequent circuit Resistors that provide bias voltage, 5 and 6... Resistor that provides bias voltage during reception, 7... Switch, 8
・Old...Switch control terminal, 9...Modulator,
10... Output terminal of modulator. Name of agent: Patent attorney Toshio Nakao Figure 1 tt tz Otsu s t
p♂

Claims (1)

【特許請求の範囲】[Claims] 2つの基準電圧を与える第1と第2の基準電圧端子と、
前記第1と第2の基準電圧の中点電圧を中心に変化する
変調信号を入力する入力端子と、前記第1と第2の基準
電圧端子の間に直列に接続した第1と第2の抵抗と、前
記第1と第2の抵抗の接続点と前記入力端子との間に接
続した第3の抵抗と、前記第1と第2の抵抗の接続点と
前記第1の基準電圧端子との間に直列に接続した第4の
抵抗とスイッチを具備し、受信時には前記スイッチをO
N状態にして、なおかつ前記入力端子を前記第2の基準
電圧端子と同電位に保ち、送信時には、前記スイッチを
OFF状態にして、なおかつ前記入力端子に前記変調信
号を入力し、前記第1と第2の抵抗の接続点から、出力
を得ることを特徴とするバイアス回路。
first and second reference voltage terminals providing two reference voltages;
an input terminal for inputting a modulation signal that changes around the midpoint voltage of the first and second reference voltages; and first and second terminals connected in series between the first and second reference voltage terminals. a resistor, a third resistor connected between a connection point between the first and second resistors and the input terminal, a connection point between the first and second resistances and the first reference voltage terminal; A fourth resistor and a switch are connected in series between the switch and the switch.
N state, and the input terminal is kept at the same potential as the second reference voltage terminal, and at the time of transmission, the switch is turned OFF, and the modulation signal is input to the input terminal, and the first and second reference voltage terminals are kept in the N state. A bias circuit characterized in that an output is obtained from a connection point of a second resistor.
JP24998786A 1986-10-21 1986-10-21 Bias circuit Expired - Lifetime JPH0724408B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24998786A JPH0724408B2 (en) 1986-10-21 1986-10-21 Bias circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24998786A JPH0724408B2 (en) 1986-10-21 1986-10-21 Bias circuit

Publications (2)

Publication Number Publication Date
JPS63104548A true JPS63104548A (en) 1988-05-10
JPH0724408B2 JPH0724408B2 (en) 1995-03-15

Family

ID=17201145

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24998786A Expired - Lifetime JPH0724408B2 (en) 1986-10-21 1986-10-21 Bias circuit

Country Status (1)

Country Link
JP (1) JPH0724408B2 (en)

Also Published As

Publication number Publication date
JPH0724408B2 (en) 1995-03-15

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