JPS63102563A - Image processing device - Google Patents

Abstract

PURPOSE:To realize a high efficient encoding regardless of the character of a picture quality by encoding a forecasting error pattern extracted by a forecasting error detecting means with a runlength method. CONSTITUTION:A pre-processing part 3 blocks dither image data DD with a said dither matrix size (4X4), and forecasts a forecasting error pattern PD concerning a next image block BD based on a forecasting error pattern ED' of the result compared with a forecasting bit pattern PD' concerning an image block BD' blocked immediately before it. Next, the bit pattern of the image block BD and a forecasting bit pattern PD forecasted concerning the bit pattern of the image block BD are compared, and a forecasting error pattern ED of the result is extracted. This is corrected to serial error pattern data SED, matched with an MH encoding part 4, encoded by the runlength method and encoding image data CD are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device, and particularly to an image processing device that can obtain a high data compression rate for dithered image data.

[Prior Art] Conventionally, the encoding methods used in facsimile machines and the like include the modified Huffman method (MH method), which is a one-dimensional encoding method, the modified read method (MR method), which is a two-dimensional encoding method, and the modified modified method. There are read methods (MMR methods), etc. However, since these encoding methods are basically run-length encoding methods, it is not possible to obtain a high data compression rate for dithered images in which black pixels are distributed almost randomly, and in some cases, the data compression rate is lower than that of the original image data. The amount of code will increase.

[Problems to be Solved by the Invention] The present invention has been made against the background of the above-mentioned prior art, and its purpose is to maintain compatibility with devices using the conventional run-length encoding method. An object of the present invention is to provide an image processing device that can simultaneously improve the data compression rate of dithered image data.

[Means for Solving the Problem] As a means for solving this problem, for example, the image processing apparatus of the embodiment shown in FIGS. A dither conversion unit 2 that dither-converts the read and digitally converted image data VD using a dither matrix of a predetermined size (for example, 4×4), and a previous stage for obtaining a high data compression rate according to the present invention for the converted dither image data DD. a preprocessing unit 3 that performs prediction error extraction processing; a modified Huffman (MH) encoding unit 4 that encodes the prediction error pattern ED subjected to the prediction error extraction processing using a run-length method; and a modified Huffman (MH) encoding unit 4 that performs the prediction error extraction processing. It includes a data transmitting section 5 that transmits data of a data CD.

Here, the preprocessing unit 3 includes an image blocking means 61 that blocks the dithered image data DD with the dither matrix size (4x4), and according to an aspect thereof, blocks the image block BD' that was immediately previously blocked. a block pattern prediction means 63 for predicting a prediction bit pattern PD for the next image block BD based on a prediction error pattern ED' as a result of comparison with the prediction bit pattern PD'; It includes prediction error detection means 62 that compares predicted pit patterns PD predicted for the bit pattern of the next image block BD and extracts the resulting prediction error pattern ED.

According to another aspect shown in FIGS. 3(a) to 3(d),
a block pattern prediction means 63' (not shown) for predicting a predicted bit pattern PD for the next image block BD based on the block density counted for the image block BD' that has been turned into a block immediately before; A predicted bit pattern P predicted for the bit pattern and the bit pattern of the next image block BD
It includes prediction error detection means 62 for comparing D and extracting the resulting prediction error pattern ED.

[Operations] In the configuration of FIGS. 1 and 2, the image blocking means 61 blocks the dithered image data DD with the dither matrix size (4×4). The block pattern prediction means 63 predicts the next image block BD based on the prediction error pattern ED' which is the result of comparing the image block BD' which has been turned into a block immediately before with the prediction bit pattern PD' by the prediction error detection means 62. Predict the bit pattern PD. Prediction error detection means 62
compares the bit pattern of the next image block BD with the predicted bit pattern PD predicted for the bit pattern of the next image block BD, and extracts the resulting prediction error pattern ED. The MH encoding unit 4 encodes the prediction error pattern ED extracted by the prediction error detection means 62 using the run-length method.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram of an image processing device according to an embodiment;
FIG. 2 is a block diagram of the preprocessing section 3 shown in FIG. 1.

In FIG. 1, an image reading section 1 reads a halftone image, such as a photograph, and performs sampling and quantization. The multi-gradation digital image data VD obtained as a result is sent to the dither converter 2, and is binarized into dither image data DD using a dither matrix of a predetermined size (for example, 4×4).

In the preprocessing section 3 in FIG. 2, the image is divided into blocks.

The means 61 blocks the dithered image data DD into image blocks BD with the dither matrix size (4×4). 11 is an (n-3) bit shift register, and its output signal Dim is sent to a flip-flop (FF) 12.
．． 13. 14 in turn. In this way, the shift register 11 and the following FFs 12 to 14 store dithered image data DD for one main scanning line consisting of a total of n pixels. Next, the output signal D14 of the FF 14 is input to the shift register 21. Therefore, the shift register 21 and the FFs 22 to 24 similarly store the previous dithered image data DD of one line consisting of n pixels. Furthermore, the same applies to shift registers 31 to FF34 and shift registers 41 to FF44.

On the other hand, the EOL detector 64 uses dithered image data D, for example.
Count n pixels of D. Furthermore, the counter 65 counts four EOL signals (or a horizontal synchronization signal may be used) output by the EOL detector 64 for every n pixels. Therefore, when the signal M is output from the counter 65, the first image block BD is cut out. After that, the next image block BD is cut out every four shift clocks.

The block pattern prediction means 63 uses the prediction error pattern ED' as a result of comparing the image block BD'' which has been turned into a block immediately before with the prediction bit pattern PD'' by the prediction error detection means 62 to predict the next image block B.
Predict the predicted bit pattern PD for D.

However, since prediction cannot be made in this way at first, prediction is performed using the default pattern DPD. For example, when there is a high possibility that the first image block BD is all white bits (logic "0"), the default pattern DPD is also all white bits (logic "O"). 311 is a JK flip-flop (FF) shown as storing one of the predicted bit patterns PD. For example, when the default pattern DPD is all white bits, the FF 311 is forcibly reset.

When the first prediction is made in this way, the prediction error pattern ED as a result of the comparison is fed back. If the error bit signal E11 of the prediction error pattern ED is logic “1” (
(prediction mismatch), the logic “0” of the prediction bit signal pH held by the FF 311 and the logic “°°1” of the error bit signal Eel are different.Exclusive OR circuit (E
OR) 211 detects this state and applies a logic "1'° signal to the JK input terminal of FF 311. Therefore, the strobe signal ST is applied to the FF 311 before comparing the next image block.
The predicted hit signal pii of 311 is inverted. That is, the block pattern prediction means 63 of the embodiment predicts the predicted bit pattern P for the next image block so as to follow the bit pattern of the image block BD' which has been turned into a block immediately before.
Change D. Generally, in a halftone image, pixels of similar density tend to be continuous, so the block pattern prediction means 6
The above prediction based on 3 is also performed well.

The prediction error detection means 62 compares the bit pattern of the next image block BD with the predicted bit pattern PD predicted for the bit pattern of the next image block BD, and extracts the resulting prediction error pattern ED. One input of the prediction error detection means 62 is the image blocking means 61
Bit pattern D11 of the image block BD cut out by
~D44. The other input is the bit patterns P11 to P44 of the prediction block PD predicted by the block pattern prediction means 63. Reference numeral 111 denotes an exclusive OR circuit (EOR) used for error detection.
When the logic values of 1 are compared and a match is not obtained, the logic "1" of the error bit signal Ell is outputted to the output terminal.

Other EORs 122, 133, 144 and EOs not shown
The same applies to Rl 12, 121, etc. As a result, the prediction error pattern E extracted by the prediction error detection means 62
Coupled with the fact that the prediction accuracy by the block pattern prediction means 63 is high, D converts the bit pattern of the image block BD so as to increase the number of apparent white pixels. Therefore,
A prediction error pattern ED suitable for the run-length method can be provided.

Note that the block pattern prediction means 63 is not limited to the configuration and operation described above. FIGS. 3(a) to 3(d) are conceptual diagrams for explaining the configuration and operation of block pattern prediction means 63' (not shown) of another embodiment. Figure 3 (a
) is the (4x4) dither matrix DM adopted in this example.
FIG. 3 is a diagram showing an array of threshold values for . However, in general, a dither matrix of size (MxN) can be used to implement the invention.

Figure 3(b) shows an image block BD cut out at a certain point.
is the bit pattern of When one pixel of the original image VD corresponds one-to-one to one element of the dither matrix in the dither converter 2, an image block BD having a bit pattern as shown in FIG. 3(b) may exist. That is, there is a state in which there are pixels that exceed the threshold value '10' and there are pixels that do not exceed the threshold value '9' even though they are adjacent pixels. but,
As the resolution of the image reading section 1 increases, the image area included in the dither matrix size also becomes narrower, so it is thought that the density of the original image VD becomes more uniform accordingly.

Further, in a halftone image, the density becomes uniform even between adjacent image blocks. Therefore, the prediction means 63', which will be described later, becomes effective.

That is, the block pattern prediction means 63' counts the number of black pixels in the immediately preceding image block BD' as shown in FIG. 3(b), for example. According to the figure, a total of eight black pixels are included. Therefore, the block pattern prediction means 63' assumes that 20 degrees of the entire immediately preceding image block is "8", and determines the bit pattern of the prediction block PD for this as shown in FIG. 3(C). That is, the predicted bit pattern of FIG. 3(C) is a dither conversion pattern that would naturally be expected if each pixel of the next image block BD had a uniform density of "8".

The block pattern prediction means 63' includes, for example, a counting means for inputting the bit pattern of the immediately preceding image block BD' and counting the total number of bits of black pixels contained therein, and is addressed by the count value of the counting means, and a predetermined predicted bit pattern PD as an output corresponding to the count value.
This is realized by a storage means (ROM, RAM) that can read out the information.

In this way, the prediction error detection means 62 detects the actual condition as shown in FIG. 3(b).
The bit pattern BD in Figure 3 (C) is compared with the predicted bit pattern PD in Figure 3 (C).
) is extracted as a prediction error pattern ED. Of course, if the predictions match perfectly, the prediction error pattern ED in FIG. 3(d) is entirely correct. In addition, even if the prediction is wrong, the prediction error pattern ED will almost always correct the apparent white pixel due to the uniformity of density within one image block and the number of g1 degrees of similarity between adjacent image blocks. converted to increase. That is, in general, the change in density of a halftone image is gradual, and the change in density in an area comparable to a dither matrix is small. Therefore, according to the above processing, the prediction error appears conspicuously mainly at the edge portions of the image, and the other portions become white. Therefore, a prediction error pattern ED suitable for the run-length method can be provided.

Furthermore, the block pattern prediction means 63, 63' is not limited to predicting the bit pattern of the next image block in the main scanning direction. Generally, the image reading unit 1 scans the original image by main scanning (horizontal direction) and simultaneously sub-scanning (direction perpendicular to the main scanning). On the other hand, since the characteristics of the original image to be read should not be distinguished between the main scanning direction and the sub-scanning direction, the present invention is equally applicable to images in either scanning direction.

Therefore, other block pattern prediction means 6 of the tree/embodiment
3'' is an image block BD adjacent to the image block BD' of the next block line based on the block density counted for a certain blocked image block BD'.
Predict the predicted bit pattern PD for .

Alternatively, other block pattern prediction means 6 of this embodiment
3'' predicts a predicted bit pattern PD for an image block BD adjacent to the image block BD'' of the next block line based on the prediction error pattern ED as a result of comparing a certain blocked image block BD''.

Alternatively, other block pattern prediction means 6 of this embodiment
3'' is the block density ND counted for a certain blocked image block BD' and the block density ND counted for the image block BD'' immediately before the image block BD adjacent to the image block BD' on the next block line. 1ND2, a predicted bit pattern PD of the image block BD is predicted. Based on the block densities ND and ND2 means, for example, based on the average value of the sum of both block densities ND, ND2.

Such a block pattern predicting means 63'' can be easily implemented, for example, by doubling the number of buffer lines for image blocking, which are comprised of shift registers and FFs, in the image blocking means 61 in the sub-scanning direction.

FIG. 4 is a block diagram of the image signal converting means 66.
The image signal converting means 66 is included in the preprocessing section 3. Since the prediction error pattern ED extracted by the prediction error detection means 62 is processed in parallel for each 4×4 pixel, it is necessary to convert it into serial error pattern data SED and match it with the MH encoder 4. . Prediction error pattern E D
FF411 to shift register 4 for every 4 x 4 pixels
44. Furthermore, the contents of each shift register 414-444 are shifted to the right before the next prediction error pattern ED is formed. In this way, when the prediction error pattern ED for four main scanning lines is accumulated, each shift register 4
The contents of 14-444 are serially shifted starting with the contents of shift register 444 until the contents of shift register 414 are all shifted out.

Next, the M HfJ encoding section 4 encodes the serial error pattern data SED outputted from the image signal generating means 66 by the run-length method to form encoded image data CD. Then, the data transmitter 5 transmits the encoded image data CD to the communication line 6.

[Effects of the Invention] As described above, according to the present invention, it is possible to realize highly efficient encoding regardless of the nature of the image, and it has the effects of shortening the transmission time and effectively utilizing the recording medium.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of the image processing device of the embodiment, FIG. 2 is a block diagram of the preprocessing section 3 of FIG. 1, and FIGS. 3(a) to (d) are block patterns of other embodiments. A conceptual diagram for explaining the configuration and operation of the prediction means 63'. FIG. 4 is a block diagram of the image signal conversion means. In the figure, 1... image reading section, 2... dither conversion section, 3
... Preprocessing unit, 4... MH encoding unit, 5... Data transmission unit, 6... Communication line, 61... Image blocking means, 62... Prediction error detection means, 63 ... block pattern prediction means, 64 ... EOL detector, 65
. . . Counter, 66 . . . Image signal conversion means. Patent applicant Canon Co., Ltd. D

Claims (5)

[Claims] (1) An image blocking means that blocks dithered image information with the dither matrix size; and a block pattern prediction means that predicts a predicted bit pattern for a predetermined image block based on the bit pattern of the blocked image block. , a prediction error detection means for comparing the bit pattern of the predetermined image block with a predicted bit pattern predicted for the bit pattern of the predetermined image block and extracting a resulting prediction error pattern. Device. (2) The image processing device according to claim 1, wherein the block pattern prediction means predicts the predicted bit pattern for the next image block based on the block density counted for the blocked image block. . (3) The block pattern prediction means predicts a predicted bit pattern for an image block adjacent to the image block of the next block line based on the block density counted for the image block that has been divided into blocks. The image processing device according to scope 1. (4) The block pattern prediction means predicts the predicted bit pattern for the next image block based on the prediction error pattern as a result of comparing the blocked image blocks. Image processing device. (5) The block pattern prediction means predicts a prediction bit pattern for an image block adjacent to the image block in the next block line based on a prediction error pattern as a result of comparing the image blocks that have been divided into blocks. An image processing device according to claim 1.