JPS63102400U - - Google Patents
Info
- Publication number
- JPS63102400U JPS63102400U JP19742986U JP19742986U JPS63102400U JP S63102400 U JPS63102400 U JP S63102400U JP 19742986 U JP19742986 U JP 19742986U JP 19742986 U JP19742986 U JP 19742986U JP S63102400 U JPS63102400 U JP S63102400U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- sub
- stereo demodulation
- main
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims 1
- 230000005236 sound signal Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Stereophonic Arrangements (AREA)
Description
第１図は本考案のサラウンド再生回路の一実施
例の回路図、第２図は第１図のサラウンド再生回
路１中のステレオ復調回路３の回路図、第３図は
第１図の実施例におけるスピーカ１１〜１４の配
置を示す図、第４図は第１図の実施例における各
スピーカの出力の経時変化を示す説明図、第５図
は従来のサラウンド再生回路の構成およびスピー
カの配置を示す説明図である。
１…サラウンド再生回路、３…ステレオ復調回
路、４，９…減算回路、５，８…加算回路、６ａ
，６ｂ，１０ａ，１０ｂ…パワー増幅器、７…遅
延回路、１５〜１９…演算増幅器、１１，１２…
メインスピーカ、１３，１４…サブスピーカ、Ｒ
１〜Ｒ１９…抵抗、Ｃ１〜Ｃ１３…コンデンサ、
Ｌ…左信号、Ｒ…右信号。
FIG. 1 is a circuit diagram of one embodiment of the surround reproduction circuit of the present invention, FIG. 2 is a circuit diagram of the stereo demodulation circuit 3 in the surround reproduction circuit 1 of FIG. 1, and FIG. 3 is an embodiment of the surround reproduction circuit of the present invention. FIG. 4 is an explanatory diagram showing the change over time in the output of each speaker in the embodiment of FIG. 1, and FIG. 5 is a diagram showing the configuration of a conventional surround reproduction circuit and the arrangement of speakers. FIG. 1... Surround reproduction circuit, 3... Stereo demodulation circuit, 4, 9... Subtraction circuit, 5, 8... Addition circuit, 6a
, 6b, 10a, 10b...power amplifier, 7...delay circuit, 15-19...operational amplifier, 11, 12...
Main speaker, 13, 14...Sub speaker, R
1 to R19 ...resistance, C1 to C13 ...capacitor,
L...Left signal, R...Right signal.
Claims (1)
＋Ｒとサブ信号Ｌ−Ｒを得、メイン信号Ｌ＋Ｒと
サブ信号Ｌ−Ｒのいずれか一方を遅延させ、その
遅延された信号と他方の信号とを合成して、再生
オーデイオ信号に含まれる残響成分をステレオ復
調するステレオ復調回路を有するサラウンド再生
回路。 Main signal L is obtained by combining the left signal L and right signal R.
+R and sub-signal LR, delay either the main signal L+R or the sub-signal LR, and synthesize the delayed signal with the other signal to generate the reverberation component included in the reproduced audio signal. A surround playback circuit that has a stereo demodulation circuit that performs stereo demodulation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19742986U JPS63102400U (en) | 1986-12-24 | 1986-12-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19742986U JPS63102400U (en) | 1986-12-24 | 1986-12-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63102400U true JPS63102400U (en) | 1988-07-04 |
Family
ID=31157159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19742986U Pending JPS63102400U (en) | 1986-12-24 | 1986-12-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63102400U (en) |
-
1986
- 1986-12-24 JP JP19742986U patent/JPS63102400U/ja active Pending