JPS63100894A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To reduce the distortion in an output data signal by providing a 1st level difference having a correlation and a 2nd level difference without correlation and outputting an interpolation video data to vary the output data smoothly at the intermediate level difference. CONSTITUTION:A gradient of a part (d) is changed into a gradient (g) in a range Y to interpolate the parts (d,f) linearly. That is, a value (A+B)+f(A-B) being an arithmetic output of input data A and a delayed data B is outputted from a 2nd adder 45, and halved by a divider 46 to form an output signal C. That is, C={(A+B)+f(A-B)}/2. In interpolating the gradient (g) in the range Y linearly, since step difference is eliminated, the signal distortion is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] What does the present invention cover? The color signals of each system are time-axis compressed, and the color signals of these two systems are input to a recording/reproducing system, for example, as l-system color signals that are arranged alternately, and the time axis is expanded on the playback side, and the two systems of color signals are The present invention relates to a video signal processing circuit suitable for processing color signals, such as color signals, on the playback side of a video tape recorder (VTR).

[Conventional technology]

2. Description of the Related Art Conventionally, VTRs have been known that record and reproduce luminance signals and color signals on separate tracks.

FIG. 5 shows an example of a recording system of such a VTR. In the figure, a luminance signal Y and color difference signals RY and BY, which are video signal outputs, are recorded.

The high frequency range of the luminance signal Y is emphasized by the pre-emphasis circuit 1, and FM modulated by the FM modulator 2, resulting in an FM luminance signal Y.
FM, and the rotating magnetic head HYI via the amplifier 3.
, HY2.

As shown in FIG. 6, diagonal recording tracks TY are formed on the magnetic tape 4 for each field by these disks HH and Hv2.

The time axes of the color difference signals R-Y and B-Y are compressed to 1/2 by the time axis compressor 5, and as shown in FIG.
, B-Y signals are arranged in order within one horizontal section.

The high frequency of this time-compressed color difference signal C is emphasized by a pre-emphasis circuit 6, and then FM modulated by an FM modulator 7.The FM color difference signal CFM is then sent to a rotating magnetic field via an amplifier 8. , l, H (2).The magnetic tape 4 is supplied with the 6th HCI and HO2.
As shown in the figure, each field has a diagonal recording track T.
c is formed.

Note that in C of FIG. 7, PC indicates a horizontal synchronization panel.

Luminance signal Y and color difference signal R recorded as shown in FIG.
-Y and B-Y are reproduced by the reproducing system in the opposite process to that of the recording system, but since the color difference signals R-Y and B-Y are time axis compressed, the time axis of each is doubled in the reproducing system. is expanded to.

By the way, the time axis compressor 5 of the recording system shown in FIG.
A charge transfer device (COD) with a capacity for the IH period
) is used.

That is, two signals are used for the R-Y signal and two signals are used for the B-Y signal. When the input is large, the IH component is outputted at 1/2H from the output side, and a compressed color difference signal C is formed.

In such a time base compressor 5, the R-Y signal and the B-
When the characteristics of the first and second CODs used for each Y signal do not match, the level difference for each IH of the R-Y signal and B-Y signal obtained by time axis expansion in the reproduction system is generated. (DC offset) occurs, especially for color difference signals (R-Y).
In the case of (B-Y), there was a problem in that the hue was changed in the color demodulation circuit.

Therefore, in order to remove noise caused by such a C offset, a comb filter consisting of a delay line 9 having a delay time equal to IH and an adder 1O as shown in FIG. 8 has been used. was. This adder IO is constructed by connecting three resistors of equal resistance value in a J-shape, and outputs the average of two input signals a and b, ie (a+b)/2.

As is well known, color difference signals have line correlation. on the other hand,
As described above, noise such as DC offset caused by COD during recording has a frequency component that is an integral multiple of 1/2 of the horizontal frequency fH, so its phase is inverted for each IH.

Therefore, in the adder circuit 10, the input signal A mixed with noise as shown in FIG. 9A and the input signal t as shown in FIG.
In the output signal B of the xt delay line 9, the noise including the DC offset is canceled out.

However, when the uncorrelated part of input signal A and output signal B is output from a comb filter, the level of F' becomes l/'2 due to averaging, as shown in Figure 9, and BK In this case, a 1/2 level color signal that does not exist in the input signal A appears, and in the case of an r4 degree signal, the vertical resolution decreases, and in the case of a color signal, the hue and brightness change.

In order to solve the above-mentioned problems, Japanese Patent Application Laid-Open No. 1569/1986
The method described in Publication No. 93 has been proposed.

The comb filter circuit described in the above publication is shown in FIG.
This will be explained with reference to FIG.

The color signal supplied from the input terminal IN is sent to the IHH extension line 9,
It is commonly supplied to the first adder 10 and the X-multiplier 11, and the output of the delay line 9 is commonly supplied to the 21u adder 10 and the subtracter 11.

The subtracter 11 represents a clip-type correlator as a whole, in which half 20 of the difference between the two input signals a and b is extracted from an amplifier 12, a clipper 13, a small-amplitude pass-type phase blocker 14 and two clamp circuits 15 and 16. It is configured.

The output signal without line correlation from the subtractor 11 is supplied to one input terminal 11a of the clip-form interlude 20,
Via an amplifier 12, a clipper 13 and a clamp circuit 15, it is supplied to the - force of a small amplitude pass-through phase enveloper 14. The output signal is supplied to the other input terminal of the clip type correlator 20 via a clamp circuit 16.

The output of the small-amplitude pass phase surroundr 14 and the addition output of the first adder 10 are supplied to the second adder 18 and output as an addition output to the output terminal OUT.

The operation of the configuration shown in FIG. 10 will be explained using FIG. 11.

The color signal A (shown in FIG. 11A) inputted to the input terminal f I N passes through the IH delay line 9 and is delayed by 1 Hllj as shown in FIG. 11B. Therefore, the output C of the first adder lO becomes as shown in FIG. 11C.

Further, the signal shown in Fig. 11, which is obtained by subtracting the signal shown in B in Fig. 11 from the signal shown in A in Fig. 11, is outputted as D from the subtractor 11.

After the output of the subtracter 11 is amplified by the amplifier 12, the low level portion is cut by the clipper 13, resulting in the signal shown in FIG. 11E.

The small amplitude pass phase enveloper 14 correlates the signal shown in FIG. 11E with the signal shown in the same diagram, and outputs the smaller amplitude signal, resulting in the signal shown in FIG. 11J. The output signal J of the small-amplitude pass-type phaser 14 and the output C of the first adder 10 shown in C of the same figure are added by the second adder 18 to obtain the color signal shown in K of the same figure. You can get to the output terminal.

As is clear from the signal shown at K in Figure 11, this circuit does not output the average value for uncorrelated horizontal line signals, so the colors do not become pale or blurring occurs. It can be seen that a color signal from which noise is removed and noise is removed can be obtained with the configuration shown in Figure m10.

However, the one shown in Figure 10 uses analog processing and uses glass or COD as the IH delay line, so there are problems with changes in linearity, S/N, frequency characteristics, temperature characteristics, etc. Ta.

The invention that solved these problems was patented in 1986-816.
It has already been filed as No. 19.

21! The above invention is explained using FIGS. 12 and 13! ]do.

In the configuration shown in FIG. 12, the latch circuits 21 and 22
is supplied with a color signal that has been converted into a digital signal in a reproduction system.

In the figure, data RY from the delay circuit 26 [l is the number of times %3 of switches constituting the dropout compensation circuit 23
0R. The output data R-Yoi of this switch 7/child circuit 3OR is supplied to a shift register 31R forming an IH delay line, and the output data R-Yts2 of this shift register 31H is supplied to the other switch circuit 3OR.

Furthermore, the output data R-YDI of the switch circuit 30R is R
OM32R1 For example, it is supplied to P-ROM as the first bit of the address signal, and the soft register 31
The output data RYo;- of R is supplied to the ROM 32R as the lower bit of the address signal.

In this case, the address of the ROM32R specified by the output data R-YDI and R-YO2 contains the output data R-YDI and R-YO2.
When DI and R-YCI2 are correlated, data ((R-You) + (R-YO2))/2=R-M
When DI2 is stored and there is no correlation, data R-MDI is recorded.

In addition, the output data of ROM32R is
The signal is latched at and supplied to the D/A converter 24.

Further, the switch circuit 30R is supplied with a dropout pulse DP from a dropout pulse generator (not shown) when there is a dropout in the color signal, and the shift register 31R and latch circuit 33R are supplied with a clock 1/2R. CK” is supplied.

In the above configuration, when the dropout pulse Dp is not supplied to the switch circuit 30R, the current data R- is used as the output data R-Yo+ of the switch circuit 30R.
When YD is output and dropout pulse Dp is also supplied, data R-YD2 before LH is output as output data R-YDI of the switch circuit 30R, thereby compensating for dropout.

Further, data is read from the ROM 32R at an address specified by the output data R-YDI of the switch circuit 30R and the output data R-Y,2 of the shift register 31R. That is, when there is a correlation between the output data R-YDI and R-YO2, ((R-Yol) + (R-
Yo2))/2=R-YO12 is read. This data is the current data R-MDI and the data R-Y before IH.
This is the additive average with D2.

Further, when there is no correlation between output data R-Yol and R-YO2, data R-Yo+ is read.

This data is current data.

For example, the output data R-Y01 of the switch circuit 30R changes over time as shown in FIG. 13 (ImA is its analog waveform), while the output data R-YD2 of the shift register 31R changes over time as shown in FIG. change(
(C in the same figure is its analog waveform), the output data of the ROM 32R changes with time as shown in F in the same figure, for example (E in the same figure is its analog waveform). In this example, data R-MDI is [111111013 and data R-Y
[Poems where 17 is m1l11111 are said to be correlated, and the data of the additive average value of both data [11111110
1 is output.

Further, in FIG. 12, the system of data B-Yo is constructed in the same manner as the data R-YD described above, and its operation is also similar.

Therefore, according to the configuration of FIG. 12, the correlation is ROM32R.
, 32B, uniformly digitally determined and processed. Therefore, linearity, S/N, f¥! Problems with f, temperature, etc. are eliminated.

[Problem that the invention seeks to solve]

However, such conventional video signal reproducing circuits have the disadvantage that waveform distortion occurs in their output. In other words, if there is a correlation between the U signal before IH and the current signal, processing is performed to output the average of both signals, and if there is no correlation, processing is performed to output the current signal as is. . Therefore, a step in the waveform always occurs at the reprocessing switching point.

This will be explained using FIG.

When the signal change before IH is B in FIG. 1(a) and the current signal is A in FIG. 1(a), for example, range X is a level range in which there is a correlation.

In a range other than the range X, the current signal A is output as is, so it becomes the part shown by d in FIG. Range X
In the range of , the average of signal A and signal B (A+B
)/2, so it becomes the part shown by f in FIG.

Since the level is switched at the boundary between the uncorrelated part and the certain part, the q-s part and r-p part of the same figure (b)
There will be a difference in level between the parts.

There is a problem in that such a stepped portion distorts the signal, making it impossible to obtain a normal color signal.

[Means for solving problems]

In the range shown by Y in FIG. 1(C), the slope of the part d is changed to two slopes as shown by g, and the part d and the part f are linearly interpolated.

[Effect]

By linearly interpolating the range shown by Y in FIG. 1(C) with the part shown by g, the level difference is eliminated, so that signal distortion is improved.

〔Example〕

FIG. 3 is a diagram showing an embodiment of the present invention, and FIG. 2 is a characteristic diagram of read data from the ROM 44.

In FIG. 3, input data A is supplied to the first addition base 42 and also to the IH shift register 41. In FIG. Note that data A has been converted into a digital signal.

The delayed data B of the IH shift register 41 is supplied to the first adder 42, and the sum signal (A + B) of both data is supplied to the second adder 45.

Further, the difference between data A and data B is calculated by the subtracter 43, and the uncorrelated data portion (A-B) of both data is stored in the ROM.
44 is supplied to the ROM 44 as a read address signal. The function af (A-B) shown in the figure ff12 is read out from the ROM 44 which is a function generator, and the second adder 45
supplied to

Therefore, the second adder 45 outputs (A+B)+f (A-B), which is the summed output of both data, which is divided into l/2 by the divider 46 and becomes the output signal C.

That is why.

Next, the operation shown in FIG. 3 will be explained.

If the current data A and the data B before IH are within a correlated range (first level difference), the subtracter 43 in FIG.
For example, the data of (A - B) which is the output of -
It is in the range from L to L, therefore, the readout output f (A-B) of the ROM44 becomes "O", f (A-B)
= 0, the second adder 45 outputs (A + B), and the output data C is the average of both data A and B. The current data A and the data before IH are non-uniform. If the correlation range, that is, the output data (A-B) of the subtracter 43 is greater than M in FIG. 2 or smaller than -M (second level difference), the read output f (
As is clear from Fig. 2, f (A-B)
= (A-B).

Therefore, the second adder 45 becomes (A+B)+(A=A), and the current data A is output as the output data C.

Next, the range where the current data A and the data B before IH are slightly correlated, that is, the output data of the subtracter 43 (A - B
) is between L and M in FIG. 2, and between -L and -M in FIG. 2 will be explained.

If data (A-B) is between L and M, the second
As is clear from the figure, the readout output of the ROM 44 is as follows.

Therefore, the addition output of the second adder 45 is
The data of the g portion of the characteristic C' shown in FIG.

Further, when the data (A-B) is between -ri and -M, the readout output of the ROM 44 is as follows from the characteristics shown in FIG. Therefore, the addition output of the adder 45 of f52 is as follows, and the data of the g portion of the characteristic C' shown in FIG. 1(C) is output from the output terminal C.

In other words, in the range where the current data A and the data B before IH are slightly correlated (which overlaps with the range Y in Figure 1 (C)), the part g in Figure 1 (C) is obtained. Because it comes to that,
The characteristic of the configuration shown in FIG. 3 is to output data with smooth characteristics as shown in FIG. 3(C).

The function generator 44 in FIG. 3 uses a ROM, and the data with the characteristics shown in FIG. 2 is stored in the ROM, but the circuit shown in FIG. 4 may be used instead of the ROM. Similar interpolated video data can be obtained by using

The circuit shown in FIG. 4 will be explained. The difference data (A − B>) between the current data A and the data B before lH is supplied to the line 51 and input to the coefficient multiplier 52, the absolute value circuit 60, and the selection circuit 56 as the first input data. At the same time, only the MSB bit, which is the sign bit of the data (A-B), is supplied to the inverter 53 and the C/N 61, and the complement circuit 5
It is input to 0.

The complement circuit 50 is an exclusive NOR (EX-NOR).
) consists of 54 parallel circuits, and the data (A -
Since the MSB bit, which is the sign bit representing the positive/negative polarity of B), is supplied to one input terminal of all EX-NORs 54, the data (A north circuit 50 inverts it and supplies it to the adder 55, and , the MSB bit is inverter 5
3 and then supplied to the adder 55. That is, an adder is used to combine the output of the complement circuit 50 and the output of the inverter 53.

Further, the output data of the coefficient multiplier 52 is also supplied to the adder 55 . Since the input of the addition fi355 is like this, the output data when the difference data (A-B) is positive is, and conversely, when the difference data (A-B) is negative, the output data is The signal is outputted to the line 62 and supplied to the selection circuit 56 as second input data.

The third input data to selection circuit 56 is the "0" signal on line 63.

The absolute value circuit 60 that obtains the absolute value IA-Bl of the difference data (A-B) includes an exclusive OR (EX-OR) 57
The MSB bit of the difference data (A-B) is supplied to one input terminal of all EX-OR5V. This MSB bit is a sign bit representing the positive/negative polarity of the difference data (A - B), so the difference data (
When A - B) is negative, data (
AB) is inverted and supplied to comparators 58 and 59 as absolute value data IA-Bl.

The comparators 58 and 59 are supplied with a constant value R or M, respectively, and the comparators 58 and 59 are supplied with absolute value data IA-B.
When l exceeds the constant M or L, a "1" signal is output on line 64 or 65.

The 2-bit signal on lines 64 and 65 is supplied as a selection signal to selection circuit 56, which selects one of the first to third input data and sends it to line 70.

When both selection signals are "1", the first input data is sent to line 70; when both selection signals are "O",
The third input data is sent to line 70 and the third input data is sent to line 64-
The selection signal on line 65 is “1” and the selection signal on line 65 is “O”.
”, the second input data is sent to line 70.

In other words, it can be seen that the data sent to line 70 has the characteristics shown in FIG.

In this case, the coefficient multiplier 52 can be easily constructed with a shift register.

Furthermore, constants M and L are functions of input data A and H, M=M
(A, B), L=L (A, B). In this case, it will be determined whether there is a correlation or not.

Furthermore, although the above-described embodiment is applied to a processing system for color difference signals R-Y and B-Y, it is of course applicable to other video signal processing systems that may cause similar problems.

(Effects of the Invention) As described above, according to the signal processing circuit of the tree, a first level difference with a correlation and a second level difference with an uncorrelated level are provided, Since the level difference outputs interpolated video data that smoothly changes the output data, distortion of the output data signal is reduced compared to conventional video signal processing circuits.

Furthermore, since the correlation is performed by digital processing, the stability is extremely high.

[Brief explanation of the drawing]

1st Ug! J is a data diagram for explaining the characteristics of the signal processing circuit of the present invention shown in FIG. 3, FIG. 2 is a characteristic diagram showing data f (A-B) output according to the degree of correlation, and FIG. FIG. 4 is a block diagram showing a part of the configuration of FIG. 3, FIG. 5 is a recording block diagram of a VTR, FIG. 6 is an explanatory diagram showing a tape recording pattern, and FIG. Figure 8 is a signal waveform diagram, Figure 8 is a block diagram of a comb filter, Figure 9 is a waveform diagram for explaining the present invention in detail, Figure 10 is a block diagram of a signal processing circuit showing the prior art, and Figure 11. 10 is a waveform diagram of the main part of FIG. 10, FIG. 12 is a block diagram showing another prior art, and FIG. 13 is a waveform diagram of the main part of FIG. 12. In the figure, 41 is an IH shift register, 42°45.55 is an adder, 43 is a subtracter, 44 is a function generator, and 54 is an EX
-NOR157 is EX-OR150 is complement circuit, 60
is an absolute value circuit, 58 and 59 are comparators, and 56 is a selection circuit. Sommon data/) Neighborhood diagram Figure 1 Custom-made custom made BAO smoker diagram Figure 3 - Two lamp records 5 - Tom customer seven tigers, two shoes? Turn Chide tlB Figure 6 Pressure Riniro Arc 2 No. Sa L Akiko Figure 7 Rin 12 Figure! Q *L Figure 13 (a) (b) (C) (d) (e) 111Q Opening

Claims (1)

[Claims] The two systems of video signals are compressed on the time axis using memory, arranged alternately, and transmitted as one system of video signals, and this one system of video signals is expanded on the time axis to create the two systems of video signals. In a circuit that processes the signal, the time-axis expanded video signal data of each system is synthesized via a delay line of one horizontal period, and the signal is processed as 1/2f_H.
When removing component noise, the current video signal data and 1
When the delayed video signal data before the horizontal period has a correlation within the first level difference, output the video data of the summed average value, and output the video data of the summed average value, and at the same time, if the delayed video signal data before the horizontal period has a correlation within the first level difference, and the second level A video signal processing circuit characterized in that when the correlation is within a difference, interpolated video data is output that makes the data difference between the video data of the addition average value and the video signal continuous.