JPS6298941A - Priority control system for packet - Google Patents

Abstract

PURPOSE:To attain sure control between packet exchanges by providing a control means for controlling a threshold level generating means to make a threshold level different from other cases when an input-side FIFO memory stores a packet from a specific input terminal. CONSTITUTION:The 1st transfer circuit (incoming transfer circuit) and the 2nd transfer circuit (outgoing transfer circuit) are provided with the following means; that is, a threshold level generating means 101 selects any of plural threshold levels and outputs the result. Further, a control means 104 allows a packet transfer means 103 to transfer a packet when the storage capacity in an output-side FIFO memory does not exceed the output threshold level as the result of comparison of a comparison means 102, and controls the threshold level generating means 101 to make the threshold level different from other cases when the input-side FIFO memory stores a packet from a specific input terminal. Thus, the control between packet exchanges is ensured more.

Description

[Detailed Description of the Invention] [Summary] The output of the first FTPO memory provided for each human communication channel is multiple-connected to the first lotus, and the output of the second FIFO memory provided for each outgoing communication channel is multiplexed. The input is multiple-connected to the second lotus, and a third FIF is connected at each intersection of the first lotus and the second lotus.
A first FIFO is configured such that an O memory is provided to store packets of a first lot and transfer them to a corresponding second bus, and the first FIFO is connected to the first bus by a first transfer circuit.
A third FI extracts packets from memory and corresponds to the destination.
A packet switching device that sends the packet to the F○ memory, extracts the packet in the third FIFO memory connected to the second lot by the second transfer circuit, and sends it to the second FIFO memory corresponding to the destination. When the first and second transfer circuits transfer the packets sucked out from the input side FIFO memory to the output side FIFO memory, the storage capacity in the output side FIFO memory is set as the storage amount threshold level. By comparison, packets are transferred only when this threshold level is not exceeded, and this threshold level is used only when extracting packets from a FIFO memory that accumulates packets from a specific input terminal. By making this different from the case of , the probability of packet discard within the switching device for packets from a specific input terminal is reduced.

[Industrial application field]

The present invention relates to a packet exchange control method in a packet switch, and particularly to a bucket l-priority control method that can reduce the probability of packet discard for packets from a specific input terminal when the exchange FIFO memory is congested. It is related to.

F I F O (First In First Ou
t) A method of realizing a large-capacity, high-speed packet switch by arranging memories in a grid is progressing.

In such a switching system, for specific packets such as control packets between adjacent packet switches, the probability of packet discard is reduced even when the exchange FIFO memory is congested, and control packets between packet switches are It is desired to make this more reliable.

[Conventional technology]

FIG. 3 shows the conceptual configuration of a high-speed bucket exchange bandai using FIFO memory. In the figure, high-speed packets arriving at the uplink 1J11 signal pass through external connections 1-0 to ]-3, 1+, 15, and 8-FIFOs 2-0 to 2 3.2 4. at arbitrary timing. 2
It is accumulated in s, -. 3-o, 3-1. - is an upstream transfer circuit, and X has 4 o, 4 +,
- through /IFI FO2-o~2 3. 2-+
, 2 9. - Poll each A-FIF○ connected to the respective 3. After selling [B-F IFO to be transferred,
Check the amount of packets accumulated in that B-FIFO,
If there is space to write a new packet]・X lotus 5-o, 5-1. --Transfer the packet to the B-FI FO via one. 6-o, 6-1+ - are respectively connected to X lotus 5-O, 13-FIFO 17-o,
? B-FIFOs 18-o, 8-, . . . -1+-- are respectively connected to the X lotus 5-1.

On the other hand, the downlink transfer circuits 10-0.10-, , - have X-lots 9-o, 9-1. - polls each B-F IFO connected to it via the
At the same time, the packet storage + capacity in that C-FIFO is counted 8 times, and if there is enough free space to write a new packet, it is transferred to the C-FIFO via X hash 11-o, 11-H, -. forward the packet to. 12-0~]
2-3 are C-F connected to X lotus 11-0 respectively
IFO112-,.

+2-5. - is C-Ff connected to X lotus 11-1
It is FO.

In the downlink communication path, external connection units 1-o to 1-3°1 4.
1 C-F I F0 connected to 'i+--・
If there is a packet in 12o to 12-3, 12-4, 125+-, the packet is extracted and transmitted at an arbitrary timing.

As described above, by the method shown in FIG. 3, it is possible to realize a large-capacity, high-speed packet switching device by arranging FIFO memories in a grid pattern. Regarding such a packet switch, the patent application filed in 1986 by the present applicant
-27029, it is explained in detail.

[Problem that the invention seeks to solve]

In the high-speed packet switching system shown in Fig. 3, B-
When transferring packets to FIFO and C-FIFO, as the amount of packets passing increases, these FIFOs
The amount of packets stored in the memory gradually increases until a situation arises in which there is not enough free space to input new packets. In such a case, the packet will be discarded, but normally the storage capacity of each B-FTFO and C-FIFO is
It is set so that the packet discard probability is sufficiently low.

In the high-speed packet switching system shown in FIG. 3, all packets are treated equally. However, due to the configuration of the switching system, it is necessary to reduce the probability of packet discard for certain packets, such as control packets between adjacent packet switches, and to ensure more reliable control between packet switches. However, in the conventional method, such a point was not taken into account at all.

[Means for solving problems]

In order to solve these problems, the present invention provides a packet switching device as shown in FIG. Each means is provided as shown in the figure.

Reference numeral 101 denotes a threshold level generating means, which selects and outputs one of a plurality of threshold levels.

Comparison means 102 compares the storage capacity in the FIFO memory on the output side and the output threshold level.

103 is a packet transfer means, which is a FIFO on the input side.
Extracts the packet from the memory and transfers it to the FIFO memory on the output side.

Reference numeral 104 denotes a control means, which causes the packet transfer means (103) to transfer the packet when the storage capacity in the output side FIFO memory does not exceed the output threshold level as a result of the comparison by the comparison means (102); When the input FIFO memory stores packets from a specific input end, the threshold level generating means (101) is controlled so that the threshold level is different from other times.

[For production]

In the present invention, in the packet switching device as shown in FIG. 3, the first transfer circuit (uplink transfer circuit)
When transferring packets extracted from IFO to B-FIFO, the storage capacity in B-FIFO is compared with the storage amount threshold level, and the packet is transferred only when the threshold level is not exceeded. In addition, in the second transfer circuit (downward transfer circuit), B-
C-F I F packets extracted from F I FO
When transferring the packet to O, the storage capacity in the C-F I FO is compared with the storage amount threshold level, and the packet is transferred only when the threshold level is not exceeded. FIF that accumulates packets from a specific input end using a threshold level
Only when extracting a packet from O memory is made different from other cases.

〔Example〕

FIG. 2 shows an embodiment of the present invention, and shows an example of the configuration of a transfer circuit according to the present invention. Although this figure shows the case of an uplink transfer circuit, the same applies to the case of a downlink transfer circuit.

In FIG. 2, the control unit 21 supplies an address update clock (count up clock) to the A-FTFO address counter 22, whereby the address counter 22 inputs the address for A-FIF○ selection. A-FI FOs connected to the X bus connected to the upstream transfer circuit are sequentially polled based on this address. When there is a packet in the selected A-FIFO, the packet present signal is sent to that A-FIFO.
Since the information is returned from A to the control unit 21, the control unit 2I
- Send a packet transfer command to the FIFO and transfer unit 23.

When a packet is transferred from A-1'lFO, the address analysis unit 24 examines the header (destination address) of the packet, determines the transfer destination B-F IFO, and
The IFO address selects the B-FIFO connected to the X bus connected to the upstream transfer circuit. As a result, information on the storage capacity of packets in the B-F r FO is output from the B-FIFO.

The comparator 25 compares the information on the storage capacity in the B-FIFO with the threshold level outputted via the switch 26, and outputs information on the comparison result to the control unit 21. Control unit 2
1, when the storage capacity in the B-FIFO does not exceed the threshold level, the packet transferred from the A-FIFO is transferred to the B-FIFO.

At this time, the switch 26 selects the set value 1 of the threshold level setting section 27 and the threshold level setting section 2 as the threshold level based on the command from the control section 21.
8, the setting value L2 is output, but the setting value is
is selected to be large compared to the set value L2, and the specific A
-FI Select setting value L2 only when extracting a packet from IFO, and use setting value L2 at other times.

Therefore, the A-FIFO connected to a specific communication path that needs to reduce the probability of packet discard is configured to accept more packets, and the other A-FIFOs are
For FO, priority control of packet exchange for a specific communication channel can be realized by increasing the probability of packet discard.

In addition, in the upper tide, the upstream transfer circuit preferentially controls the exchange of A.
- Although only one FIFO is used, this can be further expanded so that the upstream transfer circuit has a separate B-F for each A-F I FO.
It is also possible to have a FON product capacity threshold level.

The above explanation was given for the uplink transfer circuit, but the same applies to the downlink transfer circuit (by comparing the packet storage capacity in the -F I FO and the threshold level,
Packet transfer control from the FO can be performed. In this case as well, the downlink transfer circuit may have a different C-FIFO storage capacity threshold level for each B-FIFO.

〔Effect of the invention〕

As explained above, according to the method of the present invention, the probability of discarding a packet input from a specific A-FI FO is reduced in the high-speed bucket 1 to switch configured by arranging FIF○ memories in a grid pattern. Therefore, for special packets such as control packets between adjacent exchanges, the probability of packet discard can be reduced, and control between packet exchanges can be made more reliable.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing an example of the configuration of a transfer circuit in an embodiment of the present invention, and FIG. 3 is a diagram showing the conceptual configuration of a conventional packet switching system. It is. 21-Control unit, 22-Address counter, 23-Transfer unit, 24-Address analysis unit, 25-Comparator, 26-Switch, 27, 28-Threshold level setting unit Factors showing the old configuration of the principle of the present invention' M1 Figure/-1\gi

Claims (1)

[Claims] A predetermined number of output terminals of a first FIFO memory provided for each input communication path are multiplex connected to the first bus, and a second FIFO memory provided for each output communication path is connected to the first bus in multiple ways. A predetermined number of input terminals are multiplex connected to the second bus, and the first bus and the second
A third FIFO memory is provided at each intersection with a bus, and the packets of the first bus are stored and transferred to the corresponding second bus. a first FIF provided and connected to the first bus;
A packet in the O memory is extracted and transferred to a third FIFO memory corresponding to the destination, and a second transfer circuit is provided for each second bus to transfer the packet to a third FIFO memory connected to the second bus.
In a packet switching device that extracts a packet from a FIFO memory and transfers it to a second FIFO memory corresponding to a destination, the first and second transfer circuits select one of a plurality of threshold levels. Threshold level generation means (101) that selects and outputs a threshold level; Comparison means (102) that compares the storage capacity in the FIFO memory on the output side with the output threshold level; Packet transfer means (103) that extracts packets and transfers them to the output side FIFO memory
and, if the comparison result of the comparison means (102) is that the storage capacity in the output side FIFO memory does not exceed the output threshold level, the packet transfer means (103) is caused to transfer the packet, and the input side control means (104) for controlling the threshold level generating means (101) so as to make the threshold level different when the FIFO memory stores packets from a specific input end; A packet priority control method characterized by comprising: