JPS6298829A - Synthesizer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to phase-locked digital synthesizers particularly intended for use in burst mode communication systems.

Invention In accordance with the present invention, there is provided a phase-locked digital synthesizer including a voltage controlled oscillator feeding a frequency divider, the output of the frequency divider being provided to a phase sensitive detector which also receives an input from a reference oscillator, The output of is fed back to a voltage controlled oscillator by a feedback loop to achieve phase lock, such that a frequency divider receives an input from a logic circuit to control the division ratio of that frequency divider; The logic circuit is stimulated by a control signal that is also used to select one of a plurality of loop filters connected for selective use in a feedback loop from the detector to the voltage controlled oscillator;
The selected loop filter is appropriate for the stimulated divider ratio.

Preferably, a complementary timing signal is provided from the reference oscillator to the logic circuitry to ensure that the controlled divide selection occurs simultaneously with the rising edge of the reference signal.

In burst mote communication systems, phase loss digital synthesizers are used at terminals that communicate with similar terminals by time-sharing a single frequency channel. This channel is typically 5
It alternately transmits at a frequency of 0.000 Hz for about 1 mm7 bits/count, the transmit terminal sending bursts of modulated carriers to the receive terminal. When one terminal transmits, the other terminal receives, and vice versa. Each terminal has two loop filters that alternately feed the voltage controlled oscillator, one filter being in the loop during transmit mode and the other filter being in the loop during receive mode. The frequency of the voltage controlled oscillator therefore changes on each transition between receive mode and transmit mode. Although the frequency of a voltage controlled oscillator changes quickly, there is a finite amount of time for the frequency change to occur. This introduces a loop position error along with the frequency pulling introduced by the upper/lower transmitter capability, which is equal to the voltage, 'l; II
It may be several cycles at the i1 oscillator frequency.

This error may be a transient frequency error that occurs immediately after each transition between the receive mode and the transmit mode, and is then picked up by the feedback action of the loop.

To compensate for this loop phase and frequency error, the phase-locked digital synthesizer preferably includes compensation means for correcting the loop phase error arising from changes in the divider ratio, the compensation means comprising changes in the divider ratio. comparator means for comparing the phase of the output of the frequency divider with the phase of the reference signal at the sampling time after a predetermined number of basic cycles from and incrementing or decrementing depending on the phase comparison; means for generating a correction signal and for applying a correction signal to the frequency divider to adjust the frequency division ratio such that the output of the frequency divider tends to be in phase with the reference signal at the sampling time; means.

The predetermined number of cycles is preferably two, since all loop phase errors occur in the first and second cycles of the reference signal after the change in the divider ratio.

In one embodiment, the correction signal is provided to the frequency divider to adjust the "new" division ratio to be dominant over the first reference cycle after a change in the division ratio.

In other preferred embodiments, a correction signal is provided to the frequency divider to adjust the frequency division ratio between the beginning of the reference cycle and the sampling time prior to the change in the frequency division ratio.

The phase detector may be an edge-triggered phase detector that detects the rising edge of the pulse train from the frequency divider and reference oscillator.

When the synthesizer is used in a burst mode communication system, a change in the division ratio corresponds to a transition from receive mode to transmit mode, and vice versa.

The invention will be described below by way of example with reference to the accompanying drawings, in which: FIG.

DETAILED DESCRIPTION OF THE INVENTION Phase-lock synthesizers are a well-known technique for accurate frequency generation that is widely used in modern wireless communication systems. A number of proposed new communication systems are based on so-called burst-mode duplexing, which is effectively achieved by time-sharing full-duplex channels or single frequency channels (in "half-duplex" mode). (duplexing) is used. Each terminal transmits alternately on the channel at a rate of typically 509 Hz, and each sends bursts within 1 millisecond Vj of the length of the modulated carrier when the other is in receive mode. While one terminal is transmitting, the other is receiving, and vice versa. Also, while each is in receive mode, any data originating from the user is stored for transmission in the next transmission burst.

For such burst mode terminals, it is convenient and economical to utilize a common frequency source in both transmit and receive modes.

However, most wireless transceiver architectures then require switching the frequency source between modes. For example, it may be necessary to switch between a channel frequency in transmission and an intermediate frequency of +/- the channel frequency in reception.

Traditional phase-locked synthesizer architecture or
As shown in the figure. A voltage control oscillator (V CO) 1 covers the desired frequency range and divides its output frequency by an integer N''CC by a digital frequency divider 2, the ratio N can be changed externally. The output, like the output of the reference oscillator 4, is also fed to a phase sensitive detector (PSD) 3. The output of the phase detector is filtered by a loop filter 5 and the resulting voltage is It is well known that a loop will lock when the two signals entering the phase detector are of the same frequency and in phase (with appropriate selection of the phase detector).

It occurs if the VCO output frequency is Fv and the reference frequency is Fr, or when Fv-NXFr.

Thus, Fv can be set to a precise value in integer steps of Fr by varying N.

The phase-locked loop described above, whose loop transfer function is defined by the conversion gain of the VCO and phase-sensitive detector and the transfer function of the loop filter 5, forms a feedback control system.

In fact, the selection of the loop filter's bandwidth and selectivity depends on the frequency switching speed, the stability of the loop, and the spurious sidebands on the generated carrier caused by the subfrequency components insufficiently suppressed by the loop filter. and sensitivity to external influences such as mechanical vibrations. If a typical burst mode wireless system has a channel spacing of 100 KHz, the natural frequency of a typical loop is between 2 and 5 KHz.

And following a frequency step initiated by a change in the output frequency divider ratio of a few milliseconds, a settling time will be experienced to settle to a new value. Such performance can be achieved for the type of burst mode system parameters described above, with a burst length of 1 millisecond.
Totally inappropriate.

FIG. 2 shows a new form of phase-locked synthesizer that overcomes this problem.

Here, the output of vcoa is divided by a frequency divider 7 which provides control logic 8 for rapidly changing the division ratio.

The output of the frequency divider is also PSD9 as well as the reference oscillator 10.
to be sent to. The output of the PSD is transferred by an analog changeover switch 11 to one of two identical loop filters 12 and 13 realized as a filter/hold circuit.
Switched. These outputs are further fed to an analog changeover switch 14 where one is selected and fed to the VCOB.

Logic signal TR is applied to control circuit 8, changeover switches 11 and 14, and two filter hold circuits 12 and 13. The TR signal is fed via inverter 15 to filter and hold circuit 12 and logic 8.

When TR is low, a divider ratio of eg N1 is selected and the loop is completed via filter 13 in "filter" mode. (By the way, filter 12
is in "hold" mode on it. ) When TR goes high, the divider ratio N2 is selected and the filter 13 is placed in a "hold" mode, storing the output voltage present just before the low-to-high transition of TR. Changeover switch 1
1 and 14 now select filter 12 and it is put into "filter" mode to close the loop.

It is clear that while T'R is either "high-j" or "low", the loop can settle to either frequency N4XFr or N2XFr. The control voltages required to set the two further VCO frequencies are stored sequentially in two filter-and-hold circuits, and thus the synthesizer can, in principle, almost immediately adjust to the required frequency following the TR&transition. 1il capability and the loop's normal channel change settling time is no longer a factor. Since this is strictly accurate, one more measure should be incorporated.

In the circuit arrangement of FIG. 2, if one filter, say 12, is selected at a given time, and the system is balanced, then there is a common edge triggered phase detector, a frequency divider and a The rising edges of the pulse train from the oscillator to the PSD will line up in time. In addition, the 5-2 filters on the other hand maintain loop balance at slightly higher frequencies with different division ratios. T? If you have one gun (let's assume this).

Now, if the state of signal TR changes partially between nine successive rising edges of the reference oscillator output,

In conventional variable ratio frequency dividers, the programmed division ratio may be changed at any time, but the actual division ratio will not change until immediately after the next output pulse is generated. Thus, different filters with different stored voltages and therefore higher frequencies have already been selected between the reference signal edges backed up by the TR signal.
The next output pulse from the variable ratio divider will occur somewhat earlier than the reference pulse. Thus, the winching action induces a phase error into the loop, the magnitude of which depends on the difference between the two programmed frequencies and the time relationship between the TR transition and the reference signal rising edge. . The error would later be removed by the loop(') servo action, but in doing this a transient frequency error would be created.

It can be shown that this phase error and frequency transient can be avoided by ensuring that the TR signal changes synchronously with the rising edge of the reference signal, and the reference signal in FIG. The dashed connection between oscillator 10 and control logic 8 indicates that reference timing information is needed by the control logic for this purpose. In the context of the previously mentioned burst mode communication systems, this means that the length of the burst must be an integer multiple of the reference frequency period.

Many different configurations are possible for the filter hold circuit. Some of these are shown in FIG.

FIG. 3(a) shows an example of a conventional activated Lugg-Het filter that is widely used in synthesizer design. R1, C1 and A form a conventional operational amplifier integrator at low frequencies, while resistor R2 introduces a compensating phase lead at higher frequencies to improve the stability limits of the loop.

In FIG. 3(b), switch S1 is introduced to isolate capacitor C when in "hold" mode. Such a circuit is similar to filter 12 in FIG.
Or it was possible to form 2 out of 13.

Switches S2 and S3 in FIG. 3(b) are each
It forms half of the unipolar changeover switches 14 and 11 in FIG.

In all these configurations, the logic-controlled analog switch can be very conveniently implemented as a CMOS bidirectional switch.

FIG. 3(C) shows that the two capacitors C1 and C2 are
3 shows a simpler configuration included in the feedback path of the operational amplifier with associated switch elements S1 and S2; By this measure, separate changeover switches may be eliminated. Also shown in the dotted connection line is capacitor C3, which may be included to introduce a high frequency roll-off to the open loop response to reduce reference frequency noise feedthrough. However, the inclusion of this capacitor may introduce a frequency transient immediately after the switching operation, if any voltage is applied to 03 just before. Figure 3(d) shows two resistors R1, R2 or R in series with a capacitor.
1, R2-, so that each feedback network is completely isolated when the series switch S1 or S2 is actuated.

Figure 3(e) shows what to do with series switches S4 and S5.
2 shows a passive form of a lag/lead circuit incorporating two storage capacitors C4, C5.

In wireless systems, such as the Senji Telemetry Transceiver, a fast switching synthesizer is also required, but the time spent on each frequency can be much longer than with the above mechanism, typically ranging from a few seconds to several seconds. Good up to a minute. In such a case, the capacitor (Ii-) would not actually hold the voltage due to leakage current5, and an alternative arrangement would be to digitize the voltage and ``hold'' it when in ``filter'' mode. and restore it to analog form when needed via a digital-to-analog converter. With careful design, a digital-to-analog converter can also can be used, thus reducing errors during the digitization and analog restoration process.

FIG. 4 shows a block circuit diagram of a phase wack digital synthesizer according to the present invention and intended for use in burst mode communication systems. A voltage controlled oscillator (VCO) 110 receives input from a feedback loop 112. The output of the VCO is a digital frequency divider 11.
4, which divides the frequency of the VCO's output by an integer N.

The integer represents the division ratio and can be changed by control logic 116. The output of frequency divider 114 is fed to a phase sensitive detector 118, which is also fed the output of a reference oscillator 120 having a base frequency fO. The phase sensitive detector 118 is connected to one or the other of the two filters and the hold circuit 126 by means of changeover switches 122 and 124.
．． 128 to the input of voltage controlled oscillator 110.

The TR logic symbol at point 130 is low when the terminal is in receive mode and high when the terminal is in transmit mode. The terminal remains in each mode for 1 millisecond before switching modes. While the terminal is in receive mode, any data coming from that user is stored for transmission in the next transmit burst. The TR logic signal is fed to circuit 126 and control logic 116 via inverter 132 and to switch 122.12.
4 and directly to circuit 128.

When the TR signal is low, control logic circuit 116 selects the divider ratio N1, and the feedback loop is completed via filter and hold circuit 126. When the TR signal is high, the division ratio N2 is selected and the filter 12
6 is placed in a hold state to store the output voltage present immediately before the transition, and filter and hold circuit 128 is placed in a feedback loop in place of filter and hold circuit 126. Switching of circuits 126.128 is performed by switches 122.124.

Phase detector 118 is edge triggered, ie, it is sensitive to the rising edge of the pulse train from frequency divider 114 and reference oscillator 120. The TR signal is generated by the oscillator 120
oscillator 120 and control logic 116 are coupled for this purpose.

Therefore, the length of the burst (ie, the amount of time it takes for a terminal to transmit or receive) must be an integer multiple of the cycles of the reference frequency fO from the reference oscillator 120.

In the preferred embodiment, reference oscillator 120 is 100 KHz.
and the frequency F1 of the VCO during receive mode
is 800 MHz and the frequency F2 of the VCO during transmit mode is 810 MHz. At that time N1 is 800
0, and N2 is 8100. Division ratio N1 or N
2 is set by the register feeding the counter. The required frequency division ratio N1 or N2 is determined by the control logic circuit 11.
6 into a register and then the division ratio N1 or N2 is applied to a counter each time it decays to zero. Therefore, during the receive mode, at the beginning of the cycle of the reference frequency fO, the divider ratio of 8000 will be loaded into the counter from the register. The counter will then decrement to zero, at which point a rising pulse edge will be detected by phase sensitive detector 118. When the counter reaches zero, the new divide ratio Nl (or N2 if the terminal is going into transmit mode) will be loaded into the counter from the register.

FIG. 5(a) shows a typical transition of logic signal TR from receive mode to transmit mode at time t1. The vertical lines in FIG. 5 represent the edges of the reference frequency fO, and therefore the temporal spacing of these lines is such that fO is 1Q.
Since it is QKHz, it is 10 milliseconds.

FIG. 5(b) shows how the VCO frequency theoretically changes instantaneously from Fl to F2 when Fl-NIXfO and F2-N2XfO.

Figure 5(c) shows the actual profile of the VCO frequency change, where it takes a finite time for the frequency to change from Fl to F2, and then there is an overshoot, and after time t1, the frequency changes to F2 for 2 reference cycles
This indicates that the system will settle back up to the maximum.

Convenience of analysis -] 2. Changes in VCO frequency are shown in Figure 5 (d
) is idealized as a rectangular overshoot with maximum frequency error εH2 and length δ seconds.

FIG. 5(e) shows the transient change in transmitter power and shows that the new value is achieved after two cycles of the reference frequency.

Because the VCO frequency does not change at the instant of time t1 (5th
Figure (C)) and the transmitter power is above/just above (Figure 5(e)).
), a phase loop error is introduced. After the frequency division from the frequency divider 114, as shown in FIG. 5(f),
Appears in the VCo edge signal. It is noted that initially the divided VCO edge signal is in sync with the reference edge, but during the next few reference cycles the VCO edge signal is out of phase with the reference edge signal. Will.

FIG. 5(f) also shows which division ratio N1 or N2 prevails during each reference cycle. If the error during the transition results in an overshoot that is positive as shown in FIG. 5(d), there are too many pulses and after time t1 during the first reference cycle. , the counter is 81
It will be observed that it counts down from 00 and then reaches zero before the corresponding reference edge. vice versa,
If the rectangular overshoot is negative, then there are insufficient pulses and the counter reaches zero too late and just after the reference edge rather than before, as shown in Figure 5(f). A divided VCO edge pulse will be generated.

Figure 5(g) shows how compensation is achieved. After two reference cycles from transition time t1, the phases of the two inputs to phase sensitive detector 118 are compared at sampling time t2. This phase comparison is accomplished by a phase sensitive detector 134 shown in FIG. Detector 13
4 feeds the upper/ball counter 136, the output of which is fed to the control logic circuit 116 to change the frequency division ratio. If the phase error detected by the phase sensitive detector 134 is
If within cycle 140 immediately before time t2, the correction signal in the form of the divide ratio offset Δ is incremented across. If the phase error is within cycle 142 continuing immediately after time t2, Δ is decremented by one. The counter offset Δ is the burst-only first reference period;
That is, during the first reference cycle following the transition at time t1, it is added to the divider ratio N2. Therefore, at time t1 the counter is loaded with N2+Δ, which is the divided vC
This has the effect of bringing the O edge into synchronization with the reference edge at time t2 and thereafter during this burst. Δ is stored from transition to transition, and after adjustment at time t2, the adjusted and updated Δ is the first one following the next transmit/receive transition.
may be added to N2 at the beginning of the reference cycle.

As shown in FIG. 4, the value of Δ is calculated by a first command digital control loop that includes a detector 134 and a counter 136. The adjustment or offset Δ is the sampling time t occurring at the second reference edge after each transition.
is incremented or decremented according to the phase error at 2. Δ
When the digital control loop controlling the adjustment is balanced, the phase error will be within + or -1 vCO cycle.

The performance of the compensation mechanism shown in FIG. 5 may not be acceptable for all applications. The alternative compensation mechanism shown in FIG. 6 provides clearer identification. FIG. 6(a) again shows the change in the TR logic signal upon transition from receive mode to transmit mode. The vertical line in FIG. 6 represents the basal edge, as previously discussed in FIG.

FIG. 6(b) shows a theoretical VCO frequency with a continuing overshoot ε for a time δ.

FIG. 6(c) shows the transmitter power transient that occurs immediately after each receive/transmit transition. The two inputs to the phase-sensitive detector 118 are sampled again at time t2, which corresponds to the reference edge of the second node of the transition. The divide ratio offset Δ is decremented by one if the phase error occurs within cycle 44, and the offset Δ is incremented by one if the phase error occurs within cycle 146. However, in FIG. 6 the Δ offset is introduced twice. the first time during the last reference cycle 148 of the receive burst to set the divider 114 to N1-Δ, and the second time during the first VCO counter cycle 150 of the transmit burst. 114 is introduced to set N2+Δ. Still other differences that FIG. 6 has with respect to that of FIG. It is to be taught.

The system of FIG. 6 is configured such that after the R/T transition at time t1,
is analyzed by counting the number of VCO cycles that enter detector 114 before the base edge of . The counter 82 at the reference edge is N2+Δ-(N2XfO+ε)δ-N2X f'0(1/f'0+Δ/NIXfO-6)
−Δ−εδ−N2×Δ/Nl −Δ(L−N2/N1)−εδ.

Now, εδ is the position I/th error (within a cycle) as described above. Therefore, for zero phase error, Δ(1−N
The formula: l/N2)-εδ is obtained.

However, N2-N1+NI.

Here, N1 is the intermediate frequency offset (represented as a number of reference frequencies). Therefore, Δ(1-(N1+NI)/N1)-εδ becomes Δ--
The formula εδXNI/NI is given.

In this case, fo=100KHz, N=8550 (average)
, NI=100 (approximate number for an intermediate frequency of 10,7 MHz), so that Δ−85.5εδ, where of course the nearest integer value of Δ should be obtained.

Now, it can be seen that for a phase error of about one cycle, Δ needs to be on the order of 85. Furthermore, the phase adjustment caused by a unit increment of Δ is approximately 1/85 cycle or 4.2 degrees. phase error,
and hence the transient change in peak frequency is therefore the fifth
This would be 85 times less than in the illustrated embodiment.

As indicated above, the value of Δ is determined by the counter 136 due to the phase error at the second reference edge following the R/T transition, as indicated by the first order digital loop.
Increment or decrement.

Identical compensation is required at each receive and transmit frequency transition, requiring the second stored value of Δ to be interleaved with that of the first.

FIG. 7 shows a block circuit diagram of a synthesizer for achieving the compensation shown diagrammatically in FIG. Parts of FIG. 7 that are similar to those of FIG. 4 have the same reference numerals.

In FIG. 7, the feedback loop 112 includes two capacitors C1 selectively and alternately connected within the feedback loop by switches S3 and N4 connected to intensity control logic 152 to which the TR signal is applied.
and C2. As mentioned above, the signal from feedback loop 112 is provided to VCOIIO which is connected to frequency divider 114. Switch S1 has a frequency division ratio Ni
or N2, the numbers N1 and N2 are in each store 154.156. Switch S2 is for each counter 1
Select Δ1 or Δ2 (or neither) from 5g, 160.

The two's complement number 162 is either Δ1 or Δ2 or the number N1 or N
2 or subtracted from N1 or N2. Digital summer 164 provides the selected division ratio to frequency divider 114 at any correction Δ1 or Δ2.

The analog output of the position sensitive detector 113 is fed to the feedback loop 112 via switch S5. Switch S5 allows the output of detector 118 to be isolated from loop 112 for a short period of time, as shown in FIG. 6(e), while the division ratio is varied.

[Brief explanation of drawings]

FIG. 1 shows a known synthesizer. FIG. 2 does not show a synthesizer according to the invention. FIG. 3 shows various loop filter embodiments for use in the synthesizer of FIG. 2. FIG. 4 is a diagram of another embodiment. FIG. 5 is a timing diagram illustrating the operation of the embodiment of FIG. 4. FIG. 6 is a diagram of still another embodiment. Fig. 7 is a block circuit diagram of the embodiment of Fig. 6. In the figure, 1, 6, 110 are voltage controlled oscillators;
, 114 is a frequency divider, 3, 9, 118, 134 is a phase sensitive detector, 4, 10, 120 is a reference oscillator, 5 is a loop filter, 8 is a control logic, 1]. 14. 122, 124 are analog changeover switches; 12.
13, 1.26, 128 are filter halt circuits, 1
5,132 is an inverter, 112 is a feedback loop, 116 is a control logic circuit, 136.158, 1.60
is a counter, 140,142.144,146,148
is a reference cycle, j50 is a voltage controlled oscillator counter cycle, 152 is a sequence control logic, 154 and 156 are stores, and 164 is a digital summator. Patent Applicant Libara Developments Ltd. Engraving of plot (no change in content) - Produced by Loaf n Yushiki Sha C1 Dimensions for procedural amendment (Method) October 17, 1985 Patent Application No. 182606 of 1985 3. Relationship with the case of the person making the amendment Patent applicant address United Kingdom, Nis W 1P, 4 Kyu Nis London, Milpin Ku (no street address) Milbank Tower, floor 10 Name Rivera Develops Management Ltd. Representative: Gris Kant 4, Agent address: 2-8-1 Hirano-cho, Higashi-ku, Osaka, Hirano-cho Yachiyo Building Telephone: Osaka (06) 222-0381 (main)
6. 3. of the application subject to amendment. Column of address of patent applicant, drawing 7, contents of amendment (1) II-3. The address of the patent applicant is ``Floor 10, Millbank Tower, Milbank, Conton, United Kingdom, Niss W. 1P, 4 K.N.S., United Kingdom''. Kiyu Nis, London, Miloire 10J and correction t. For this purpose, we will submit a newly prepared correction application on a separate sheet. (2) The drawing drawn in black ink is shown in the attached sheet. Please note that there are no changes to the content. Amendment of the above procedure dated October 17, 1986

Claims (9)

[Claims] (1) A phase-locked digital synthesizer with a voltage-controlled oscillator feeding a frequency divider, the divider output being fed to a phase-sensitive detector that also receives an input from a reference oscillator, and the output of the detector being phase-locked. A frequency divider receives an input from a logic circuit to control the division ratio of the frequency divider, and the logic circuit is assisted by a control signal. ,
The control signal is also used to select one of a plurality of loop filters connected for selectable use in the feedback loop from the detector to the voltage controlled oscillator, and the selected loop filter is facilitated. A phase-locked digital synthesizer that is suitable for divided ratios. (2) A synthesizer as claimed in claim 1, wherein a reference timing signal is fed from a reference oscillator to the logic circuit, ensuring that selection of the controlled frequency divider occurs simultaneously with a rising edge of the reference signal. . (3) Compensating means is provided to correct errors in the loop phase resulting from changes in the frequency divider ratio, and the compensating means is configured to compensate for errors in the loop phase resulting from changes in the frequency divider output phase and the frequency divider ratio. comparator means for comparing the phase of the reference signal at a sampling time after a number of reference cycles; and means for generating an incremental or decrement correction signal depending on the phase comparison; and means for applying a correction signal to the divider to adjust the divider ratio so as to tend to bring the output of the divider into phase with the reference signal at the sampling time. The synthesizer according to item 1 or 2. (4) The synthesizer according to claim 3, wherein the predetermined number of cycles is two. (5) A correction signal is provided to the frequency divider so as to adjust the division ratio that is dominant over the first reference cycle after the next change in the division ratio. 4. The synthesizer according to item 4. (6) A correction signal is provided to the divider so as to adjust the divider ratio between the beginning of the reference cycle and the sampling time before the next change in the divider ratio. The synthesizer according to item 4. (7) Any one of claims 3 to 6, wherein the phase detector is an edge-triggered phase detector that detects the rising edge of the pulse train from the frequency divider and the reference oscillator. Synthesizer described. (8) A synthesizer according to any of the preceding claims, wherein a change in the division ratio corresponding to a transition from a receive mode to a transmit mode is used in a burst mode communication system, and vice versa. (9) two correction signals are obtained, stored, and updated, the first correction signal correcting the loop phase error resulting from the change in divider ratio that occurs during the transition from receive mode to transmit mode; 9. The synthesizer according to claim 8, wherein the second correction signal corrects a loop phase error resulting from a change in frequency division ratio that occurs upon transition from transmit mode to receive mode.