JPS629844U

JPS629844U -

Info

Publication number: JPS629844U
Application number: JP9850085U
Authority: JP
Priority date: 1985-06-28
Filing date: 1985-06-28
Publication date: 1987-01-21

Description

[Brief explanation of the drawing]

第１図はこの考案によるデジタルプリンタの一
実施例を示した概略的なブロツク線図、第２図は
第１図に示されている中心値設定スイツチの具体
的な構成例を示す図、第３図は同じく第１図に示
されているランク幅設定スイツチの具体的な構成
例を示す図、第４図は第１図のＣＰＵに含まれて
いる度数算出手段の概略的なブロツク線図、第５
図はこの考案例によるヒストグラムのプリント例
を示す図である。図中、１はマイクロコンピユータ、３はＣＰＵ
、４はＲＡＭ、５はＲＯＭ、６は中心値設定スイ
ツチ、７はランク幅設定スイツチ、９はプリント
ヘツド、１０は基準データ発生器、１１はコンパ
レータ、１２は制御パルス発生器、１３はデコー
ダ、１４はメモリセル、１５はアンドゲートであ
る。 FIG. 1 is a schematic block diagram showing an embodiment of the digital printer according to this invention, FIG. 2 is a diagram showing a specific configuration example of the center value setting switch shown in FIG. 1, and FIG. 3 is a diagram showing a specific configuration example of the rank width setting switch also shown in FIG. 1, and FIG. 4 is a schematic block diagram of the frequency calculation means included in the CPU of FIG. 1. , 5th
The figure is a diagram showing an example of printing a histogram according to this example of the invention. In the figure, 1 is a microcomputer, 3 is a CPU
, 4 is a RAM, 5 is a ROM, 6 is a center value setting switch, 7 is a rank width setting switch, 9 is a print head, 10 is a reference data generator, 11 is a comparator, 12 is a control pulse generator, 13 is a decoder, 14 is a memory cell, and 15 is an AND gate.

Claims

[Scope of utility model registration request]

a center value setting switch; a rank setting switch for setting the number of output ranks and the width of each rank;
It is characterized by including a frequency calculation means for allocating the measurement data supplied from the measuring device into each rank and calculating the frequency thereof, and printing the frequency value of each rank outputted from the frequency calculation means as a histogram on recording paper. digital printer.