JPS6292671A - Image recorder - Google Patents

Abstract

PURPOSE:To record a half tone at a high speed by providing a memory where preliminarily determined application time data for each gradation is stored, a counter which counts a preset data value, and a load signal shift register and supplying power to a recording element while the counter counts the preset value. CONSTITUTION:When the first half tone data PiX1-PiX3 are inputted to an application time data ROM 27, a load signal LOAD is inputted to a shift register 28 from a terminal 22. A clock signal CLK is inputted to the shift register 28 also from a terminal 21 simultaneously, and the first application time data DAT1-DAT4 are preset to a counter 29a. Hereafter, the n-th data DAT1-DAT 4 are preset to a counter 29n similarly. Power is supplied to a heating resistor 32 while flip flops 30a-30n are set through a driver 31. After this power supply, the similar operation is repeated to record half-tone images.

Description

[Detailed description of the invention] Industrial applications The present invention relates to an image recording apparatus that performs halftone recording.

BACKGROUND OF THE INVENTION FIG. 3 is a circuit diagram showing a schematic configuration of an example of a conventional halftone recording apparatus. This device consists of a line memory 1, an address counter 2, a gradation counter 3, halftone data read out from the line memory 1 (hereinafter referred to as DAT), and the output of the gradation counter 3 (hereinafter referred to as this). CMP), the value of I) ATm is CMP.
Below the signal c for recording when the value of MP is greater than the value of MP, this is P.
i
An applied pulse width generation circuit 6 outputs a strobe signal c (hereinafter referred to as STB) that latches PiX transferred to the thermal head (to be described later), a signal input terminal 6 that inputs KNB, and a signal input that inputs STB. Terminal 7 and P
A signal input terminal 8 for inputting iX, a signal input terminal 9 for inputting PiX transfer lock (hereinafter referred to as CLK), a heating resistor 1o, a driver 11 for energizing the heating resistor 1o, AND gate 12 and latch circuit 1
3, shift register 14, power supply terminals 16 and 16
, a recording power source 17, and these heating resistors 10. The thermal head 18 includes a driver 11, an AND gate 12, a latch circuit 13, and a shift register 14.

Next, the operation of this device will be explained. First, DATA is read out from the line memory 1 by the address counter 2 and is input to the comparator 4. The output CMP of the gradation counter 3 is initially set to ``0'', and therefore, as the output of the comparator 4, if DATA is @1'' or higher, it is transferred to the shift register 14 as PiX ``H''. . After the transfer ends, the address counter 2 outputs a transfer end signal (hereinafter referred to as TNSO), the applied pulse width generating circuit 6 detects this, outputs STB, and stores PiX in the latch circuit 13. After the storage is completed, the applied pulse width generation circuit 5 outputs ENB, which is the applied pulse width corresponding to the gradation level "1", and performs the first recording. At this time, the gradation counter 3 is incremented by TNSO, and CMP becomes '1'.Subsequently, the same DATA as the previous time is read out from the line memory 1, and this time, if the DATA is '2' or more, the PiX ”
The signal is transferred to the shift register 14 as "H".

Thereafter, in the same way, the applied pulse width generation circuit 5 detects the TNSO signal and outputs STB after confirming the completion of the previous application, and also outputs ENB, which is the applied pulse width corresponding to the gradation level "2". Then perform the second recording.

Similarly, the gradation levels ``'3'', '4''...
A recording operation is performed up to the determined gradation level, and a halftone image is recorded.

Problems to be Solved by the Invention However, with this configuration, the image signal is read out from the line memory as many times as the number of gradations required, and after comparing it with the recording level, the recording signal is transferred to the thermal head. Since this operation requires time, there is a problem in that it becomes an impediment to improving the recording speed.

Such problems occur for the following reasons. That is, the characteristic between color density and application time in thermal paper is not linear, and if the application time is the same for each gradation, a satisfactory halftone image cannot be obtained. Therefore, it is necessary to set and correspond to a unique application time for each gradation. In other words, it is necessary to prepare as many application times as the number of gradations, and drive each heating resistor independently with an application time corresponding to the gradation data. As a result, in the conventional thermal head 18 as shown in FIG. 3, which has a general structure, it is necessary to transfer PLX to the thermal head 18 for the number of gradations.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide an improved image recording apparatus that can perform halftone recording without hindering the increase in recording speed.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a memory that stores predetermined application time data for each gradation;
a counter that presets data read from the memory and counts the preset value using a basic clock signal; a shift register that inputs a load signal for sequentially presetting data to the counter; and a shift register that inputs a load signal for sequentially presetting data to the counter; and an application time control means for energizing the recording element for a period of time.

According to the above-described configuration, the present invention reads out predetermined application time data from the memory based on the value of the halftone data, and sequentially presets this data in the counter using the load signal output from the shift register. A basic clock signal is input to this counter, and counting starts after the preset is completed. Since the heat generating resistor is intermittent during the time during which the counter counts the preset value, data only needs to be transferred once, making it possible to speed up halftone recording.

Embodiment FIG. 1 shows an electrical circuit diagram of a schematic configuration of an image recording apparatus according to an embodiment of the present invention. In the figure, reference numeral 20 is a signal input terminal for inputting a recording start signal 5TART, and 21 is a signal input terminal for inputting a clock signal CLK that is synchronized with halftone data signals PiX1 to PiX3 and transfers a load signal LOAD, which will be described later, to a shift register 28. Terminals 22 each represent a signal input terminal to which a load signal LO D of a preset value of counters 29a to 29n, which will be described later, is input. Further, reference numeral 23 denotes a signal input terminal for inputting MCI, which is a basic clock signal of the counters 29a to 29n; 24.2
5.26 is a signal input terminal into which the halftone data signal PiX1.2.3 is input. Each terminal 24, 25, 26 is connected to an application time data ROM 27 which stores application time data DAT1-4 corresponding to each gradation in advance and outputs it to counters 29a-n. The shift register 28 to which the terminals 21 and 22 are connected is preset by the load signals LDa to n, and counts its preset value by the basic clock signal MCI. The clip-flops 30a-n connected to the counters 29a-n receive a recording start signal 5TA.
RT and set by the carry signal of counter 2 g a ”-n. Flip-flop 3
During the time when 0 is set, a recording power source 35 is connected between the resistor 32 and the driver 31 via recording power terminals 33 and 34 in order to drive the heating resistor 32, which is a recording element, by the driver 31. ing.

Regarding the image recording device configured as described above.

The operation will be explained below. Here, since the input of halftone data is 3 bits, an example is shown in which halftone recording of eight gradations is performed. The halftone f-total PiX1.2.3 input from the signal input terminals 24, 25, and 26 is stored in the application time data ROM 27 as 4-bit application time data DAT1 to DAT1.
Converted to 4.

The application time data DAT1 to DAT4 are stored in the counters 29a to 29a.
Since this is a preset value of n, the lower the gradation, the larger the value. For example, at level "1", the data is "IC", and at level "'2", the data is "C".

......At level "8", the data is 0. On the other hand, when the first halftone data PiX1 to 3 are input to the application time data ROM 27, as shown in FIG. The load signal LOmD is also input from the terminal 22 to the shift register 28. At the same time, the clock signal CLK is also input from the terminal 21 to the shift register 28, and the load signal LDa is output from the shift register 28, and the first application time data DAT1~ 4 is preset in the counter 29a.Next, when the second halftone data PiX1 to PiX3 is input, the load signal output of the shift register 2nd day shifts from LDa to I and Db by the clock signal CLK. The nth application time data DAT1 to DAT4 are preset to the counter 29b.
AT1 to AT4 are preset to the counters 29n, and when all the counters 29a%n are preset, the recording start signal 5TART is sent to the flip-flops 30a to 30n.
n and these are set. counter 2 at the same time
9a to 9n start counting in response to the basic clock signal MCI. When the counter 29a%n completes each count according to the preset value, it outputs a carry signal to reset the flip-flop 30a%n. The heating resistor 32 is energized through the driver 31 for a period of time during which the flip-flop 30 a % n is set. Thereafter, when this energization ends, similar operations are repeated to record a halftone image.

Although the case of 8-gradation recording is shown here, it is clear that the present invention is not limited to this.

Of course, by increasing the number of bits of input halftone data, the number of tones to be recorded increases. In such a case, or when controlling the application time for each gradation more precisely, increase the number of output bits of the application time data ROM 2a, and accordingly increase the number of preset bits and count bits of the counter 29a%n. This can be adjusted by increasing the period of the basic clock signal MCI input to the counters 29a to 29n. Furthermore, it is of course possible to perform divisional recording of one line.

Effects of the Invention As is clear from the above description, the present invention includes a memory storing predetermined application time data for each gradation, presetting data read from this memory, and using the preset value as a basic clock signal. , a shift register that sequentially outputs a load signal to preset data to the counter, and an application time control means that energizes the recording element during the time that the counter counts the preset value. This method has the advantage that data transfer is only required once, and halftone recording can be performed at high speed.

[Brief explanation of drawings]

Fig. 1 is an electrical circuit diagram of a schematic configuration of an image recording apparatus showing an embodiment of the present invention, Fig. 2 is a timing chart of the main parts, and Fig. 3 is an implementation of a conventional image recording apparatus. FIG. 2 is an electrical circuit diagram of a schematic configuration showing an example.

Claims (1)

[Claims] A memory that stores data on an application time determined by the coloring density and application time characteristics of the recording paper corresponding to the halftone data, and a preset value of the application time data read out from the memory using the halftone data. a counter that counts based on a basic clock signal; a shift register that inputs a load signal for presetting the application time data to the counter; and an application time control that energizes the recording element during the time that the counter counts the preset value. An image recording device having means.