JPS6286598A - Memory circuit - Google Patents

Abstract

PURPOSE:To simplify a constitution and enable a high density integration by constituting a memory part by a capacity part and a precharge transformer and an information selecting part by two serial transistors. CONSTITUTION:When a passing signal inversion P moves to a grounding potential, a (p) type precharging transistor 29 of a memory part 32 is turned on, a capacity body 31 formed by a semiconductor substrate of a memory part 22 is precharged to a positive voltage VPP. Then, when a selecting signal L1 is inverted to H, an (n) type transistor 22 turned on by supplying the data 1 or the like of an information selecting part 21 and an (n) type transistor 25 serial therewith are turned on and the capacity body 31 is grounded. Accordingly, an output of an inverter 30 is inverted to a positive potential and it is held. Similarly to the case when the data D2, D3 or the like are '0', a memory circuit has a simple constitution of the reduced number of elements and a high density integration can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory circuit, and particularly to a memory circuit suitable for highly integrated semiconductor devices.

[Prior art]

FIG. 3 is a logic circuit diagram of a conventional memory circuit, where 1 indicates an information selection section and 2 indicates a storage section. The information selection unit 2 receives the information signal DI+D! at one input. *DS is
AND circuits 3 and 4.5 to which selection signals L1 t L2 and L3 are respectively applied to the other input;
The storage unit 2 is composed of a NOR circuit 6 to which an output of 4.5 is applied, and a NOT circuit 7 to which a passing signal P is applied, and a NOR circuit 6 that conducts or conducts the output of the NOR circuit 6 based on the output of the NOT circuit 7. A transmission circuit 8 to be cut off, two knot circuits 9 and 10 arranged in series that sequentially invert the output of the transmission circuit 8, and an input to the knot circuit 9 that conducts or cuts off the output of the knot circuit 10 based on a passing signal P. and a transmission circuit 11 for returning the signal. The output of the storage section 2 is obtained from between the NOT circuits 9 and 10.

Next, with reference to FIG. 4, we will explain the effect when (1,010) is applied to the information signal DI +D2+D3 and the selection signals L, L, L sequentially change from "0" to "L". The explanation is as follows. First, when I"l becomes "1", the AND circuit 4.5 remains at the logic "0", but the AND circuit 3 shifts to "1", and the output of the NOR circuit 6 shifts to "0" ( time tr).

Next, time t! When the passing signal P shifts to "0",
The transfer circuit 8 is turned on by the output of the NOT circuit 7, the output of the NOR circuit 6 is inverted by the NOT circuit 9, and the logic rlJ is outputted (time tz).

This output is inverted by the knot circuit 10, and the passing signal P is
With the transition to "1", the transfer circuit 11 is turned on, which is fed back to the NOT circuit 9, and the transfer circuit 8 is turned off, so the output remains at logic "1".

Subsequently, when sLl shifts to "0" and L2 is inverted to "l", the output of the NOR circuit 6 becomes "1", and when the passing signal P becomes "0" at time t5, the output of the NOR circuit 6 becomes It is inverted by the NOT circuit 9, and "0" is output and held. The same applies to the subsequent transition of sLs from "0" to "l".

FIG. 5 shows another conventional example in which the output of the NOR circuit 6 is stored in the stray capacitance between the transfer circuit 12 and the NOT circuit 13 instead of the self-holding circuit formed by the NOT circuit 1O and the transfer circuit 11. , the output is held even after the passing signal P changes to "1", and the operation shown in FIG. 6 is the same as that in FIG. 5, so a description thereof will be omitted.

[Problem that the invention seeks to solve]

In the conventional storage circuit described above, since the signal to be stored in the storage section 2 is selected by a combination of the selection signals L1 to L3 and the information signals D1 to D3, a large number of logic circuits are required.
Since each logic circuit must be composed of a plurality of transistors, the number of transistors constituting the memory circuit increases, and there is a problem in that a large area is required to integrate this on a semiconductor substrate.

[Means for solving problems]

The present invention precharges a capacitor with a first reference potential via a precharge transistor, and then selects a first transistor and a second transistor that are arranged in series between the capacitor and the second reference potential. The capacitor is driven by a signal and an information signal, and when selected by a selection signal, the capacitor is maintained at the first reference potential or shifted to the second reference potential depending on the response of the information signal. do.

〔Example〕

FIG. 1 is a first embodiment of the present invention, and shows an example integrated on a semiconductor substrate. The information selection unit 21 includes n-channel MOS transistors (hereinafter referred to as nMOS) 22 and 23°24 connected in parallel to the ground potential, and nMO8.
nMO825, 26, 2 connected in series with 22-24
7, and the gates of nMO822-24 are
An information signal D 1 *D 2 +D3 is applied.

On the other hand, the selection signal IjltL2*L3 is applied to the gates of nMO825-27,
825 to 27 are all connected to a p-channel type MOS transistor (hereinafter referred to as pMO8) 29 via a wiring 28.
connected to the drain of

The source of 9MO829 is connected to the positive voltage source vDD, and the drain of 9MO829 is further connected to the inverter 3.
0 to the output section.

Since the aforementioned wiring 28 is disposed on the oxide film grown on the surface of the semiconductor substrate, the capacitor 31 is connected to the semiconductor substrate.
is formed. These 9MO829° inverter 30
．． The capacitor 31 constitutes a storage section 32 as a whole.

Next, the operation will be explained with reference to FIG. For ease of understanding, the information signals D1 to D3 are assumed to be (110, O). First, when the passing signal P shifts to the ground voltage (time tl
), the pMO829 is turned on, and the capacitor 31 has a substantially positive voltage vD.
Precharged to D. After the passing signal P shifts to a positive voltage, when Ijl shifts to a positive voltage (time t2), nMO
825 is turned on.

Here, since the nMO 822 is turned on by the information signal D1=1, the capacitor 31 is grounded and has a ground potential.

Therefore, the inverter 30 is inverted and becomes a positive voltage (
r l J), hold this. Next, at time t3, even if L2 is precharged again and shifts to a positive voltage at time t4, since D220, the nMO 823 remains in the off state and the capacitor 31 maintains the positive voltage. Therefore, inverter 30 maintains the ground voltage (roj) and D
2=0 is reflected. D320 is the same as D220, so the explanation will be omitted.

FIG. 7 shows a second embodiment, in which the information selection section 21 is 9MO8.
41 to 46, and the precharge transistor is nM.
It is composed of O847. Therefore, the information selection section 21
The power supplies connected to the storage section 32 and the storage section 32 are reversed, so that the passing signal P and the selection signals L1 to L3 are in opposite phases (see FIG. 8). However, since the operation is similar to that of the first embodiment, the explanation will be omitted.

〔effect〕

As described above, according to the present invention, the storage section is composed of a capacitor section and a precharge transistor, and the information selection section is arranged in series between the capacitance section and the second reference potential, and the selection signal and the information selection section are arranged in series between the capacitance section and the second reference potential. Since it is composed of two transistors that open and close depending on the signal, the structure is simple and can be integrated at high density on a semiconductor substrate.

[Brief explanation of drawings]

Fig. 1 is an electric circuit diagram of the first embodiment, Fig. 2 is a timing chart diagram of the first embodiment, Fig. 3 is an electrical circuit diagram of the conventional example, Fig. 4 is a timing chart diagram of the conventional example, and Fig. 5 is a timing chart diagram of the conventional example. Figure 6 is an electric circuit diagram of another conventional example, Figure 6 is a timing chart diagram of another conventional example, Figure 7 is an electric circuit diagram of the second embodiment, and Figure 8
The figure is a timing chart diagram of the second embodiment. 22-24.41-43...second transistor, 25-27.44-46...first transistor. 31...°...Capacitor, 29.47...Precharge transistor. Agent Patent Attorney Susumu Uchihara LrLzLs P Figure 1::;) t, tz tlt< Figure 2 tt b 1d4tc Figure 4 Figure 5 Figure 7

Claims (1)

[Claims] In a storage circuit having an information selection section that selects an information signal based on a selection signal, and a storage section that stores information represented by the information signal selected by the information selection section, the storage section stores information. The information selection section is configured of a capacitance section and a precharge transistor that precharges the capacitance section to a first reference potential, and the information selection section is arranged in series between the capacitance section and the second reference potential and is opened and closed by a selection signal. What is claimed is: 1. A memory circuit comprising a first transistor that is opened and closed by an information signal and a second transistor that is opened and closed by an information signal.