JPS628655A - Line folding test system - Google Patents
Line folding test systemInfo
- Publication number
- JPS628655A JPS628655A JP60146455A JP14645585A JPS628655A JP S628655 A JPS628655 A JP S628655A JP 60146455 A JP60146455 A JP 60146455A JP 14645585 A JP14645585 A JP 14645585A JP S628655 A JPS628655 A JP S628655A
- Authority
- JP
- Japan
- Prior art keywords
- line
- transmitter
- receiver
- short
- hybrid circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Facsimiles In General (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は折返し試験方式に関し、特にλ線式通信回線を
使用する７アクシミ１Ｊｉｉの回線折返し試験に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a loopback test method, and more particularly to a line loopback test of a 7-axis 1Jii using a λ-ray communication line.
従来の技術
従来、多くのファクシミＩＪｆｆｌｄは適用回線として
一般公衆電話回線を利用している。従って、回線は一線
式回線であり、通信方式は通常半二重通信方式が採用さ
れている。ファクシミリ装置には送信機と受信機とが組
込まれているが送信機の送信出力と受信機の受信入力は
ハイブリット回路で結合され、２線式回線と結合されて
いる。ハイブリット回路は送信機よりの出力信号を回線
に伝達し、回線からの受信信号を受信機入力に伝達し、
さらに送信機の出力信号を受信機入力に伝達させない様
だするものである。BACKGROUND OF THE INVENTION Conventionally, many facsimile IJfflds have used general public telephone lines as applicable lines. Therefore, the line is a single-line line, and the communication method usually employs a half-duplex communication method. A facsimile machine incorporates a transmitter and a receiver, and the transmission output of the transmitter and the reception input of the receiver are coupled by a hybrid circuit and connected to a two-wire line. The hybrid circuit transmits the output signal from the transmitter to the line, transmits the received signal from the line to the receiver input,
Furthermore, the output signal of the transmitter is prevented from being transmitted to the receiver input.
発明が解決しようとする問題点
上述したように、従来のファクシミリ装置においては、
ハイブリット回路があるために、送信機出力を受信機入
力に与えることができないので、一線式回線の回線折返
し試験が実施できないという欠点があった。Problems to be Solved by the Invention As mentioned above, in the conventional facsimile machine,
Since there is a hybrid circuit, it is not possible to apply the transmitter output to the receiver input, so there is a drawback that a line loop test of a single line line cannot be performed.
本発明は従来の技術に内在する上記欠点を解消する為に
なされたものであり、従って本発明の目的は、２線式回
線の回線折返し試験を容易にしかも的確に実施すること
を可能とした新規な回線折返し試験方式を提供すること
にある。The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the conventional technology, and therefore, an object of the present invention is to make it possible to easily and accurately carry out line loopback tests on two-wire lines. The objective is to provide a new line loopback test method.
問題点を解決するための手段
上記目的を達成する為に、本発明による回線折返し試験
方式は、−線式回線を使用するファクシミＩＪ装置にお
いて、送信機と、受信機と、前記送信機の出力と前記受
信機の入力とに接続され一線式回線とを結合する・・イ
ブリッド回路と、前記ハイブリット回路の２１ｆａ式回
線側を短絡する折返し試験用短絡手段とを具備して構成
され、回線折返し試験時には前記−線式回線を前記折返
し試験用短絡手段で短絡することにより前記送信機の出
力を前記受信機の入力に与えることを特徴とする。Means for Solving the Problems In order to achieve the above object, the line return test method according to the present invention provides a facsimile IJ apparatus that uses a -wire type line, which includes a transmitter, a receiver, and an output of the transmitter. and a hybrid circuit connected to the input of the receiver to couple the single-wire line, and short-circuiting means for loopback testing that shorts the 21FA line side of the hybrid circuit. In some cases, the output of the transmitter is provided to the input of the receiver by short-circuiting the negative line type line with the return test short-circuiting means.
実施列
次に本発明をその好ましい一実施例について図面を参照
して具体的に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.
第１図は本発明の一実施例を示すブロック構成図である
。FIG. 1 is a block diagram showing one embodiment of the present invention.
第１図において、参照番号１０／は送信機、１０コは受
信機、１０３はハイブリット回路、１ｏｔＩはコ線弐回
線端子、／（Ｈは折返し試験用回線短絡プラグをそれぞ
れ示す。In FIG. 1, the reference number 10/ is a transmitter, 10 is a receiver, 103 is a hybrid circuit, 1otI is a second line terminal, and /(H is a return test line short-circuit plug.
送信機１０／の送信出力はハイブリット回路１０．３に
与えられる。受信機１０ユの受信入力はハイブリット回
路１０３より与えられる。ハイブリット回路１０３は、
送信機１０／の送信出力と受信機１０２の受信入力を結
合して一線式回線とし、２線式回線端子ＩＯ’ｌを介し
て通信回線と結合さぞている。The transmission output of transmitter 10/ is given to hybrid circuit 10.3. The reception input of the receiver 10 is provided by a hybrid circuit 103. The hybrid circuit 103 is
The transmission output of the transmitter 10/ and the reception input of the receiver 102 are combined to form a one-wire line, which is connected to a communication line via a two-wire line terminal IO'l.
通常の動作の場合には、送信機１０／と受信機１０コは
半二重通信制御により交互に回線を使用して相手側ファ
クシミ！Ｊ’！電と通信を行っている。送信機／ＩＩと
受信機１０２の回線接続切替間両は行なわれず、ハ・イ
ブリッド回路１０３によって単に送イ１機１０／と受信
機１０コは電気的に回線と接続されている。In normal operation, the transmitter 10 and receiver 10 alternately use the line under half-duplex communication control to send faxes to the other party! J'! It communicates with electricity. There is no line connection switching between the transmitter/II and the receiver 102, and the transmitter/II and the receiver 10 are simply electrically connected to the line by the hybrid circuit 103.
次に回線折返しの場合について説明する。Next, the case of line loopback will be explained.
回線折返し試験を実施する嚇合には１．２線式回線を短
絡するために、折返し試検用回線短絡プラグ１０Ｓを２
線式回線端子ＩＯ’ｌに実装する。ハイブリット回路１
０３はハイブリット回路１０３より回線側を見て、ハイ
ブリット回ｕ １０．３のインピーダンスに等しいイン
ピーダンスの回線が接続されている場合には送信機ｉｏ
ｉの送信出力を受信機ｉｏ−の受信入力に伝達しない。In order to short-circuit the 1.2-wire line when conducting a line return test, connect the line shorting plug 10S for the return test.
Mount it on the wire line terminal IO'l. Hybrid circuit 1
03 looks at the line side from the hybrid circuit 103, and if a line with an impedance equal to the impedance of the hybrid circuit u10.3 is connected, the transmitter io
Do not transmit the transmit power of i to the receive input of receiver io-.
回線側のインピーダンスがハイブリット回路１０３のイ
ンピーダンスと不整合の場合には、送信機１０／の送信
出力の一部が受信機ＩＯ−の受信入力に廻シ込む。この
廻り込む量は、回線が開放状態か短絡状態のときに最大
となる。前述の様に、一線式回線端子１０４Ｉは折返し
試験用回線短絡プラグｌｏｓによって短絡されている。When the impedance on the line side is mismatched with the impedance of the hybrid circuit 103, a part of the transmission output of the transmitter 10/ flows into the reception input of the receiver IO-. This amount of looping is greatest when the line is open or short-circuited. As described above, the single-wire line terminal 104I is short-circuited by the return test line short-circuit plug los.
従って、受信機１０λの受信入力には送信機１０／の送
信出力が入力される。Therefore, the transmission output of the transmitter 10/ is input to the reception input of the receiver 10λ.
発明の詳細
な説明したように、本発明によれば、−線式回線を短絡
することにより、ハイブリット回路を介して送信機出力
を受信機入力に与えることができ、−線式回線の折返し
試験を容烏に実施できる効果が得られる。DETAILED DESCRIPTION OF THE INVENTION According to the invention, as described, the transmitter output can be applied to the receiver input via a hybrid circuit by shorting the wire line, and the loopback test of the wire line can be performed. It is possible to achieve the effect of easily implementing the
第１図は本発明の一実施例を示すブロック構成図である
。
１０／・・・送信機、ｉｏコ・・・受信機、１０３・・
・ハイブリット回路、ＩＯ’ｌ・・・−線式回線端子、
１０５・・・折返し試験用回線短絡グ２グFIG. 1 is a block diagram showing one embodiment of the present invention. 10/...transmitter, IO code...receiver, 103...
・Hybrid circuit, IO'l...-wire type line terminal,
105... Line short circuit for return test G2G
Claims (1)
機と、受信機と、前記送信機の出力と前記受信機の入力
とに接続され２線式回線とを結合するハイブリット回路
と、前記ハイブリット回路の２線式回線側を短絡する折
返し試験用短絡手段とを具備し、回線折返し試験時には
前記２線式回線を前記折返し試験用短絡手段で短絡する
ことにより前記送信機の出力を前記受信機の入力に与え
ることを特徴とした回線折返し試験方式。A facsimile device using a two-wire line includes a transmitter, a receiver, a hybrid circuit connected to an output of the transmitter and an input of the receiver to couple the two-wire line, and a hybrid circuit of the hybrid circuit. and short-circuiting means for short-circuiting a two-wire line for short-circuiting a loopback test, and at the time of a line-folding test, by short-circuiting the two-wire line with the short-circuiting means for loopback testing, the output of the transmitter is connected to the input of the receiver. A line loopback test method that is characterized by giving
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60146455A JPS628655A (en) | 1985-07-05 | 1985-07-05 | Line folding test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60146455A JPS628655A (en) | 1985-07-05 | 1985-07-05 | Line folding test system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS628655A true JPS628655A (en) | 1987-01-16 |
Family
ID=15408025
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60146455A Pending JPS628655A (en) | 1985-07-05 | 1985-07-05 | Line folding test system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS628655A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7280572B2 (en) | 2002-03-25 | 2007-10-09 | Sanyo Electric Co., Ltd. | Semiconductor laser beam device |
| US10241413B2 (en) | 2014-02-20 | 2019-03-26 | E I Du Pont De Nemours And Company | Composite printing form precursor and method for preparing a printing form precursor for treatment |
-
1985
- 1985-07-05 JP JP60146455A patent/JPS628655A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7280572B2 (en) | 2002-03-25 | 2007-10-09 | Sanyo Electric Co., Ltd. | Semiconductor laser beam device |
| US7889770B2 (en) | 2002-03-25 | 2011-02-15 | Sanyo Electric Co., Ltd. | Semiconductor laser device |
| US10241413B2 (en) | 2014-02-20 | 2019-03-26 | E I Du Pont De Nemours And Company | Composite printing form precursor and method for preparing a printing form precursor for treatment |
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