JPS628584B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic code lock for a safe which generates an unlock code by pressing a push button switch and is unlocked when the correct unlock code is generated.

One possible method for improving the safety of a safe with an electronic code lock is to increase the number of digits in the unlock code in order to reduce the probability that the unlock codes coincide with each other and the safe is unlocked by chance. In order to further increase this safety, it is possible to unlock the door only by using two different unlock codes instead of using one type of unlock code. In this case, rather than having one manager memorize two types of unlock codes, it is better to have two managers memorize one type of unlock code that is different from each other, and have them unlock the lock separately. This is desirable from the standpoint of crime prevention.

Therefore, the present invention proposes an electronic code lock for a safe that emits an unlock signal only when two different correct unlock codes are applied. Furthermore, the present invention provides a circuit that combines components that can be used in common when performing an unlocking operation using two unlocking codes, such as an unlocking code input section and a circuit for verifying the unlocking codes, even when the circuits are combined into one. This invention proposes an electronic code lock that can effectively perform unlocking operations using two unlock codes. Furthermore, the present invention proposes an electronic code lock that can be switched as necessary to issue an unlock signal when verification of both or one of two different unlock codes is completed.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments of the present invention shown in the accompanying drawings. In the drawings, members having the same function are indicated by the same reference numerals.

First, the code lock according to the present invention is unlocked by two managers A and B using different 8-digit A unlock code and 8-digit B unlock code.

An unlocking signal is generated when the unlocking codes of both managers A and B match respective preset unlocking codes.

FIG. 1 is a basic block diagram showing an example of an unlock code matching circuit used in the code lock of the present invention. FIG. 2 is a block diagram showing one embodiment of the code lock of the present invention. FIGS. 3 and 4 are block diagrams showing other embodiments of the code lock of the present invention. FIG. 5 is a block diagram having a switching member for the AND system and the OR system. FIG. 6 is a circuit diagram more specifically representing the block diagrams shown in FIGS. 1 and 4. FIG.

First, the block diagram shown in FIG. 1 will be explained. Reference numeral 11A denotes a circuit that performs a verification operation for a set unlock code with respect to the A unlock code when performing an unlock operation using the A unlock code, and is called an A channel selection circuit. Reference numeral 11B denotes a circuit that performs a verification operation for the setting release code with respect to the B unlocking signal when performing an unlocking operation using the B unlocking code, and is referred to as a B channel selection circuit. A channel selection circuit 11A and B channel selection circuit 11B constitute a channel selection circuit. 20 is an unlocking code input section which is provided externally and has 10 push button switches for generating codes 1, 2, ..., 9, 0, and includes 10 output leads corresponding to the switches. It is. 30 is an unlock code matching circuit that outputs a signal indicating a match when one of the preset A unlock code or B unlock code matches the code applied to the unlock code input section 20. . This unlock code matching circuit 30 includes an unlock code setting circuit 32 that holds preset A unlock code and B unlock code.
and a coincidence detection circuit 38 that compares the input unlock code from the unlock code input section 20 with the corresponding set unlock code.
, a level register 33 as a shift section that defines the comparison digit, and a shift circuit 34 that shifts the level register 33 in response to a key operation in the unlock code input section 20. The unlocking code setting circuit 32 responds to the outputs of the A channel selection circuit 11A and the B channel selection circuit 11B, and outputs the corresponding setting A unlocking code and setting B unlocking code, respectively. At that time, the unlocking code setting circuit 32
In response to a digit designation signal from the level register 33 as a shift unit, the code of the designated digit is sequentially output to any of the ten output lines 0 to 9. level·
The register 33 is a type of shift register in which only one cell among a plurality of cells has a different theoretical value (for example, "1") from the other cells, and the cell with "1" moves in accordance with the clock. say something The coincidence detection circuit 38 is, in principle, the same as the unlock code setting circuit 32.
This is a circuit that detects whether each digit signal matches between the 10 parallel outputs and the 10 parallel outputs of the unlock code input section 20. If they do not match, it outputs a mismatch signal and sets the level. - Clear register 33. The shift circuit 34 detects a change in signal level appearing on any one of the ten output lines by key operation of the unlocking code input section 20, and generates a short rectangular pulse. This rectangular pulse is applied to the clock input of level register 33 and moves the theoretical value "1" to another cell within level register 33. Due to this movement, the digit designation signal output from the level register 33 designates the next digit, and the unlocking code setting circuit 32 outputs a signal for the next digit. Repeat this action,
When the level of the level register 33 reaches the final stage, the set unlock code and input unlock code match for all digits, and the release code matching circuit 30 outputs a match signal.

In the present invention, a shift circuit 34 is provided to shift the level register 33, so that unlocking is possible even if it takes too long to input a code in the unlock code input section 20. but,
In such a case, it is preferable to reject the unlocking operation. For this purpose, the operation of the shift circuit 34 is monitored, and when the output pulse interval of the shift circuit exceeds a certain period of time, the level register 33 is set. A clear signal may be supplied to the clear input. This can be achieved with a simple charge/discharge circuit.

Next, the embodiment shown in FIG. 2 will be described. A
The relationships among the channel selection circuit 11A, the B channel selection circuit 11B, the unlock code input section 20, and the unlock code collation circuit 30 are the same as in the first illustrated embodiment. The A unlocking gate 40A opens upon receiving the output of the A channel selection circuit 11A, and allows the signal from the unlocking code matching circuit 30 to pass through. Further, the B unlock gate 40B is connected to the B channel selection circuit 1.
It opens when it receives the output of 1B, and the unlock code verification circuit 3
Pass the signal from 0. A signal holding circuit 50
A receives the A signal from the A unlocking gate 40A,
This circuit continues to output a signal corresponding to the A signal for a certain period of time. Further, the B signal holding circuit 50B
This circuit receives the B signal from the unlock gate 40B and continues to output a signal corresponding to the B signal for a certain period of time. However, the A signal and B signal are
This indicates that the unlocking code has been verified and matched, and that the B unlocking code has been verified and matching. The signal holding circuit 50 includes the A signal holding circuit 50A and the B signal holding circuit 50B, but it is sufficient to hold the signal that has passed through at least one of the A unlocking gate 40A and the B unlocking gate 40B. . In other words, when operating the A unlock code first and the B unlock code later, the A signal of the A unlock gate 40A is
You only need to hold it until the unlock code operation is completed.
It is not necessary to hold the B signal passing through the B unlock gate 40B. The final stage gate 60 emits an unlock signal when it receives both the A signal and the B signal.

The operation of the second illustrated embodiment will be explained. First, when the A manager operates the unlocking operation using the A unlocking code, when the A channel selection circuit 11A is activated,
The part of the electronic code lock of the present invention relating to the member for the A-unlocking code becomes operable, and the A-unlocking gate 40A is opened. Next, the release code input section 20
When the correct A unlock code is input from the A unlock code, the unlock code verification circuit 30 outputs a signal indicating that the input unlock code is correct, and the A signal from the A unlock gate 40A is sent to the A signal holding circuit 50A. The A signal holding circuit 50A continues to supply the A signal to one input of the final stage gate 60. Here, the unlock code verification circuit 30
Even if outputs the signal, the B unlock gate 40B
is not opened and therefore does not output the B signal. Next, when the B manager performs a release operation using the B release code, the B channel selection circuit selects the B channel, that is, the operation of the A channel selection circuit 11A is switched to the operation of the B channel selection circuit 11B.
Then, the part of the electronic code lock of the present invention relating to the member for the B unlocking code is activated, and the B unlocking gate 40B is opened. Next, when the correct B unlock code is input from the unlock code input section 20, the unlock code collation circuit 30 outputs a signal in the same way as in the case of the A unlock code, and the B signal from the B unlock gate 40B is terminated. Applied to another input of stage gate 60. Since the A signal has already been applied to the final stage gate 60, the final stage gate 60 issues an unlock signal. This unlocking signal is amplified and causes a current to flow through a solenoid (not shown) or the like, thereby shifting the lock device (not shown) from a locked state to an unlocked state. Furthermore, if a current member such as a motor that opens and closes the safe door is driven by this unlocking signal, it becomes extremely convenient in conjunction with the remote operability of the electronic code lock. Furthermore, since the signal holding time of the signal holding circuit 50 is set constant, after this certain period of time has elapsed, even if the second person in charge applies the correct unlocking code, the unlocking signal will not be generated, so safety is compromised. Sufficient security will be provided.

Next, FIG. 3 will be explained. The configuration shown in FIG. 3 is almost the same as that shown in FIG. 2, except that the signal holding circuit in the configuration shown in FIG. 2 is configured in a different manner. The retention time control circuit 52 is an A channel selection circuit 11A or a B channel selection circuit 11B.
This is a circuit that receives an output from the circuit and continuously outputs an output signal for a certain period of time while receiving this output and after it ceases to receive this output. The continuous generation time of the output signal in the holding time control circuit 52 can be adjusted from the outside. The A signal gate circuit 51A operates the A unlock gate 40 while receiving the output signal from the holding time control circuit 52.
When receiving the A signal from A, the holding time control circuit 52 outputs a signal corresponding to the A signal, and even if the A signal from the A unlocking gate 40A is subsequently cut off.
As long as it receives an output signal from the final stage gate 60
This is a circuit that continues to send a signal corresponding to the A signal. When the B signal gate circuit 51B receives the B signal from the B unlocking gate 40B while receiving the output signal from the holding time control circuit 52, it outputs a signal corresponding to the B signal, and then the B unlocking gate circuit 51B outputs a signal corresponding to the B signal. Even if the B signal from the gate 40B is cut off, this circuit continues to send a signal corresponding to the B signal to the final stage gate 60 as long as it receives the output signal from the holding time control circuit 52.

The operation of the configuration shown in FIG. 3 will be explained. First, when the unlocking operation by the A manager using the correct A unlocking code is completed, the A signal is generated from the A unlocking gate 40A. In addition, the retention time control circuit 52 in this case
By receiving the output of the channel selection circuit 11A, the output signal is sent to the A signal gate circuits 51A and B.
It is supplied to the signal gate circuit 51B. As a result,
The A signal gate circuit 51A supplies the A signal to the final stage gate 60.
Send out a signal that corresponds to the signal. Next, Manager B uses A to unlock the door using B's unlock code.
The operation of the channel selection circuit 11A is stopped, and the operation of the B channel selection circuit 11B is started. During this switching, the holding time control circuit 52 temporarily loses its input signal, but continues to generate its output signal for a short period of time. Therefore, during the short period of time after the A signal is no longer emitted from the A unlock gate 40A, the B channel selection circuit 11B
As long as the A signal gate circuit 51A operates,
The signal corresponding to the A signal continues to be sent to the final stage gate 60. And B with the correct B unlock code
When the unlocking operation is completed, the B unlocking gate 40B outputs the B signal, and the B signal gate circuit 51B receives the output signal from the holding time control circuit 52 and continues the signal corresponding to the B signal to the final stage gate. Continue sending to 60. In response to the signal corresponding to the A signal and the signal corresponding to the B signal, the final stage gate 60 issues an unlocking signal. On the other hand, when the operation of the B channel selection circuit 11B is stopped and the generation of the output signal from the retention time control circuit 52 is stopped after a predetermined period of time has elapsed, the A
Neither the signal corresponding to the A signal from the signal gate circuit 51A nor the signal corresponding to the B signal from the B signal gate circuit 51B is supplied to the final stage gate 60.
The final stage gate 60 no longer outputs the unlock signal.

Next, FIG. 4 will be explained. The configuration shown in FIG. 4 is different from the configuration shown in FIG. 3 by adding an interlock circuit 12 downstream of channel selection circuits 11A and 11B for locking signals indicating their operating states. This interlock circuit 12
After operating one of the channel selection circuits 11A and 11, the signal state is maintained for a certain period of time, and during that time, the signal state is not changed even if the other channel selection circuit is operated. Therefore, the cancellation operation once started will not be disturbed by an erroneous operation of the channel selection circuit.

Next, the configuration example shown in FIG. 5 will be explained. A
The AND method is a method in which an unlock signal is issued only when the unlock code and the B unlock code match, and the unlock signal is issued when one of the A unlock code and the B unlock code matches. The method of emitting this signal will be called the OR method. FIG. 5 shows an example of a switching circuit of both types. The first switch 71 for switching connects the unlocking code verification circuit 30 and the unlocking gate 4.
0A and 40B, the common pole is connected to the output of the unlocking code verification circuit 30, and one terminal, that is, the D terminal is connected to the input of the A unlocking gate 40A and the input of the B unlocking gate 40B. connected to the points. Also, one terminal of the second switch 72 for switching,
In other words, connect the D terminal to the output of the final stage gate 60,
The remaining terminal S terminal is connected to the remaining terminal S terminal of the first switch 71, and the second switch 7
2, the unlocking signal is supplied to subsequent circuits, devices, etc. from the energized state. Unlock code verification circuit 3
If the output of 0 and the output of the final stage gate 60 have different polarities, an inverter 73 may be inserted between the S terminal of the first switch 71 and the S terminal of the second switch 72. Here, the first switch 71 and the second switch 72 are designed to work together, and when one common pole is connected to the S terminal or the D terminal,
The other common pole is also connected to the S terminal or the D terminal, respectively. If you want to operate in the AND method, switch both the first switch 71 and the second switch 72 to the D terminal, and if you want to operate in the OR method, switch both the first switch 71 and the second switch 72 to the S terminal. Bye. FIG. 5 shows the case where the OR method is selected.

Next, the present invention will be explained with reference to a more concrete circuit diagram shown in FIG. 111A is a switch for operating the A channel selection circuit 11A, and 111B is a switch for operating the B channel selection circuit 11B.
This is a switch for operating the In the unlock code input section 20, 200, 201, ..., 20
Reference numeral 9 is a push button switch for issuing an unlock code; when the button 200 is pressed, an unlock code of 0 is generated, when the button 201 is pressed, 1, . . ., when the button 209 is pressed, an unlock code of 9 is generated. 210, 211, . . . , 219 are inverters. The shift circuit 34 is basically a circuit that takes the logical sum of all output lines of the unlocking code input section 20 and generates a short pulse based on a change in the resultant value of the logical sum. That is, shift circuit 3
4 supplies a short pulse to the level register 33 every time the push buttons 200, . . . , 209 are pressed. Level register 33 is clocked and shifted by this pulse. 35 is a gate that generates an output when either the A channel or the B channel is selected and the selected state is maintained. 36 is a clock gate which is opened in the presence of the output of channel gate 35 and sends the pulses of shift circuit 34 to level register 33. 37 is a waiting time adjustment circuit after a malfunction, and this time can be changed by changing the value of a volume 371 or a capacitor 372. If you press the wrong unlock code, the output of the comparator circuit 38 becomes high, the transistor 373 becomes conductive, and the capacitor 372 is discharged, so the clear gate 39
A clear signal is applied to level register 33 via. As a result, level register 33 is returned to its initial state. The input of the unlock code is ignored until the clear signal disappears, and the capacitor 372 must be charged to restore the normal state. This time becomes the waiting time. In the figure,
The A unlock code is 12345678, and the B unlock code is 09876543.

The interlock circuit 12 includes a latch circuit that responds to the switch operation of the push button 111A of the A channel selection circuit 11A, and a B channel selection circuit 11B.
A latch circuit that responds to the switch operation of the push button 111B, and a latch circuit that forces both latch circuits to the initial state if the next key operation is not performed even after a certain period of time after each key operation on the unlock code input section 20. Contains a clear circuit for recovery. This clear circuit includes a capacitor 121, a gate 122, a transistor 123
and a resistor 126, the operation of which will be described later. Since the outputs of both latch circuits are coupled to the clear input of level register 33 via gates 35 and 39, interlock circuit 12
In the initial state, the level register 33 is always in a clear state.

Next, the operation of the embodiment shown in FIG. 6 will be explained. First, let us consider the case where manager A performs an unlock operation using unlock code A. When the push button 111A is pressed, one input of the gate 122 becomes a logic low (hereinafter referred to as "L"), so its output becomes a logic high (hereinafter referred to as "H"), the transistor 123 becomes conductive, and the capacitor 121 discharges, one input of the gate 124 becomes L, and together with the L input by pressing the push button 111A, the inverter 12
The output of 5 is set to H. Once set in this manner, even if the push button 111B is subsequently pressed by mistake, the interlock circuit 12 will not change the output of the inverter 125, so that once the A unlocking operation is started, it cannot be prevented. On the other hand, when the verification of the A unlock code or the B unlock code is completed and an output signal is generated in the unlock code verification circuit 30, current rapidly flows from the output of the circuit 30 to the capacitor 121 via the resistor 41 and charges the capacitor 121. . Therefore, the interlock circuit 12 is reset,
Therefore, level register 33 is also cleared. Also, while the capacitor 121 is being discharged,
That is, when one of the channel selection circuits 11A and 11B is operating, the input of the retention time control circuit 52 becomes L, and the transistor 521 becomes conductive.
Capacitor 522 is discharged. Therefore, the retention time control circuit 52 transmits the H signal to the gate circuit 51.
A, 51B. Moreover, capacitor 121
Even if the channel selection circuit 11 is charged, that is, the channel selection circuit 11
Even if the operation of A and 11B is canceled, the holding time control circuit 52 continues to generate the H signal for a certain period of time determined by the resistor 523 and the capacitor 522.

Furthermore, if the individual buttons 200, . . . , 209 of the unlock code input unit 20 are not operated within a predetermined time after the push button 111A is pressed, the level register 33 is cleared. The operation will be explained below. When push button 111A is pressed, one input of gate 122 becomes L as described above, so its output becomes H, transistor 123 becomes conductive, capacitor 121 is discharged, and one input of gate 124 becomes L. However, when the push button 111A is released, both inputs to the gate 122 become H, so the output of the gate 122 becomes L, the transistor 123 becomes non-conductive, and the capacitor 121 is charged via the resistor 126. Therefore, push button 1
If no operation is performed after pressing 11A, one input of the gate 124 becomes H after a predetermined time, the output of the inverter 125 becomes L, and the gate 3
5 becomes L, and a clear signal is applied to the level register 33 via the clear gate 39. As a result, level register 33 is returned to its initial state.

After pressing the push button 111A, any of the push buttons 200, ..., 2 of the unlocking code input section 20 is pressed within a predetermined time.
When 09 is pressed, the output of the shift circuit 34, which is the other input of the gate 122, becomes L, and as described above, the output of the gate 122 becomes H, the transistor 123 becomes conductive, the capacitor 121 is discharged, and the gate 124 One input of is maintained low.

With the above operation, the push buttons 200, ..., 209
If the button is not pressed for more than a predetermined period of time or is left unused, all circuits will return to their initial state. This predetermined time can be set as desired by changing the capacitance of the capacitor 121 and the resistance value of the resistor 126.

When all of the 8-digit A unlocking codes are verified, an A signal, which is an L signal, is generated from the A unlocking gate 40A, and this signal and an H signal from the circuit 52 are sent to the two A signal gate circuits 51A. Since it is applied to the input, an H signal is generated at the output of the A signal gate circuit 51A. When the unlocking operation is subsequently performed using the B unlocking code, the A unlocking gate 40A generates an H signal, but as long as the holding time control circuit 52 continues to send the H signal, the A signal gate circuit 51A Generating H signal. In addition, A signal gate circuit 51A
For the combination of inputs, it is possible that the output of the A unlocking gate 40A is an L signal and the output of the circuit 52 is an L signal, and in this case, an unlocking signal is generated without an unlocking operation. There is no problem because the L signal, which is the verification end signal, will not be emitted from the A unlocking gate 40A without an unlocking operation. As mentioned above, when the verification of the A unlock code is completed, the H signal is generated in the A signal gate circuit 51A, and when the verification of the B unlock code is completed, the H signal is also generated in the B signal gate circuit 51B, and at this time, the H signal is generated in the B signal gate circuit 51B. A release signal is generated at the stage gate 60. Since the present invention is as described above, it has the following effects. Have two people manage two different unlock codes,
Since the unlocking code can be executed, the possibility of internal crime is drastically reduced. Also, if necessary, AND
This is convenient because the method and OR method can be changed freely. Furthermore, the unlocking operation can be performed reliably by using an unlocking code matching circuit that generates the same signal when two different unlocking codes are verified. Therefore, the unlock code verification circuit can be constructed inexpensively and simply. Furthermore, since there is an interlock circuit, the unlocking operations of manager A and manager B are not interfered with by malfunction of the channel selection circuit. In addition, if the holding time of the signal holding circuit is set to a short time, one manager may forget that the lock was unlocked, and the other manager may unlock the door after a long period of time has elapsed. This has the effect of eliminating the negative effects of unlocking the door.

[Brief explanation of the drawing]

Fig. 1 is a basic block diagram showing an example of an unlocking code matching circuit used in the code lock of the present invention, Fig. 2 is a block diagram showing an embodiment of the code lock of the present invention, and Figs. 3 and 4 respectively. A block diagram showing another embodiment of the code lock of the present invention, FIG. 5 is a block diagram having a member for switching between AND system and OR system, and FIG. 6 is a block diagram shown in FIGS. 1 to 4. FIG. 3 is a circuit diagram showing the circuit more specifically. 11A...A channel selection circuit, 11B...
B channel selection circuit, 12...Interlock circuit, 20...Unlocking code input section, 30...Unlocking code verification circuit, 40A...A unlocking gate, 40B...
...B unlocking gate, 50...Signal holding circuit, 50A
...A signal holding circuit, 50B...B signal holding circuit, 51A...A signal gate circuit, 51B...B
Signal gate circuit, 52... Retention time control circuit, 6
0... Final stage gate, 71... First switch, 72
...Second switch.

Claims (1)

[Scope of Claims] 1. A channel selection circuit for selecting an unlocking operation using an unlocking code A or an unlocking operation using an unlocking code B; an unlocking code input section for inputting an unlocking code by external operation; an unlocking code setting circuit that presets an unlocking code and an unlocking code B; and an unlocking code setting circuit that presets an unlocking code and an unlocking code B; a shift unit that compares the lock code digit by digit and outputs a matching signal when the input unlock code and the set unlock code all match; and the input unlock code signal and the corresponding digit. a circuit that clears the shift section when the set unlock code and the unlock code do not match; a circuit that shifts the digit of the shift section each time the unlock code input section inputs an unlock code; The selected channel is maintained as long as each digit of the unlock code is inputted in the unlock code input section within a predetermined time after the channel selection operation in the channel selection circuit, and the input operation is performed within the predetermined time. an interlock circuit that is reset to the initial state and clears the shift section when the shift section is not present; and a circuit that issues an unlock signal in response to a match signal from the shift section and a signal of a selected channel from the channel selection circuit. An electronic code lock for a safe, comprising the following.