JPS6285369A - Data transferring system between processors - Google Patents

Abstract

PURPOSE:To shorten the processing time for data transfer by constituting the titled system so that the data which has been written in a buffer memory means through a register by the first processor can be received through a register by the second processor. CONSTITUTION:Plural processor modules PM1-PMm are connected to each other by a common bus 1. Each module is constituted of a processor CPU 3, a local memory LM 4 for storing a program for prescribing an operation of the processor and a work data at the time of an operation of the processor, an FIFO buffer device BF 5 which is used for transferring a data to other processor module, and a local bus LB 13 for connecting them. According to this constitution, the next data can be transferred from a transfer side processor without waiting for the end of a processing to the transfer of a receiving side processor, and the data transfer processing time can be shortened, therefore, a throughput of an inter-processor communication is raised.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for transferring data frames between a plurality of processors, and particularly to an inter-processor data transfer method suitable for a system in which data frames are transferred asynchronously.

[Background of the invention]

Conventionally, as a data transfer method between multiple processors,
For example, Intel's MIP system is known. In this method, two processors transfer data via a shared memory, and the shared memory is provided with a plurality of data transfer areas and registration pointers and takeout pointers to these data transfer areas. The processor on the data transfer side finds the address of the data transfer area to which data should be written next from the contents of the registration pointer, writes the transfer data to the data transfer area corresponding to this address, and then writes the registration pointer. Update. On the other hand, the processor on the data receiving side finds the address of the data transfer area from which data should be extracted next from the contents of the fetch pointer, fetches the transferred data from the data transfer area corresponding to this address, and then updates the fetch pointer. do.

Both processors can know whether the data transfer area is full or empty by comparing the registration pointer and the retrieval pointer. However, this Intel MIP
This method has the advantage of being able to transfer the next data without waiting for the receiving processor to finish processing the transferred data, but it also has the advantage of being able to transfer the next data without waiting for the receiving processor to finish processing the transferred data. Since the process of updating the registration/extraction pointer is required, there is an inconvenience that the process takes a long time.

On the other hand, as another method that can reduce the processing time, there is a method described in Japanese Patent Laid-Open No. 58-97944, for example. In this method, a FIFO queue is prepared in hardware separate from the shared memory, and only the address of a data transfer area in the shared memory is transmitted via the FIFO queue. However, this method also has the drawback that overhead is generated in the process of extracting the data transfer area from the empty data transfer area queue in the shared memory.

[Purpose of the invention]

An object of the present invention is to enable, when transferring data between processors, the next data to be transferred without waiting for the receiving processor to finish processing the transferred data, and to shorten the processing time for data transfer. The object of the present invention is to provide an inter-processor data transfer method.

(Summary of the Invention) To achieve the above object, the multiprocessor of the present invention
The system is first. a second processor; a first register into which data can be written by the first processor;
a second register that can read data from the second processor; a first-in, first-out type buffer memory means for taking in data and outputting data to a second register in response to an instruction from the second processor; The second processor receives data written to the buffer memory means via the second register.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of a multiprocessor system to which the present invention is applied, in which a plurality of processor modules PM-1 to PM-m are connected to each other by a common bus 1. As shown in FIG.

Each processor module includes processor (CPtJ) 3,
Progera 11 that defines the operation of the processor and local memory (LM) 4 for storing work data during processor operation. It consists of a poorest-in-first-out (FIFO) buffer device 5R (BF) 5 used for data transfer with other processor modules, and a local bus (LB) 13 that connects them.

FIG. 2 shows an example of the configuration of a FIFO buffer device. The buffer device 5 has an address decoder 6 and a 12° command/
Status registers 7 and 11, data register 8-
1 to 8-n, and 10-1 to 10-n, FIFO memories 9-1 to 9-n, data input signal lines 100 and 107 from the address decoder to the register, and data output signal lines 101 and 107 from the address decoder to the register. 108,
Data input signal lines 103-1 to 103-n from address decoder to data register, register to FI
Data input signal lines 104-1 to 104-n to FO,
FIFO full signal line 105 from FIFO 9-1 to register 7, FIFO empty signal from FIFO 9-1 to register 1]-! 106. Data input signal fi109-1 to data register from register 11 to data register
09-n, data output signal lines 11, 1-1 to 111-n from register to PIFO, data output signal lines 102-1 to 102-n from register 7 to data register,
It is composed of data output signal lines 110-1 to 110-n from the address decoder to the data register.

FIG. 3 shows a memory map in the above system. 1
00H to 100H+ Address n (n is the maximum value of transfer data frame) is processor module/l/PM-1
Destination transmission area, 200H to 200H+n address is P
This is the transmission area for M-2.

These areas are accessed via common bus 1.

1000H"1O000H+ n address is processor
This is the reception area of the module and is accessed via the local path 13. The command/status register 7 is allocated to the first byte of the transmission area addressed to the processor module, and the data register 8 is sequentially allocated to the second and subsequent bytes. On the other hand, the first byte of the reception area of each processor module contains the command/
The status register 11 is allocated, and the data register 10 is sequentially allocated to the second and subsequent bytes. FIG. 4 shows the bit allocation of the command/status register 7. 2° is a data input bit, and when the CPU writes this bit "1", signal lines 102-1. ~10
2-n and 104-1 to 1, 04-n flow, and the contents of data register 8 enter FIFO memory 9. The second bit is a full bit, and when there is no empty area in the FIFO memory 9, a signal flows to the signal line 105 and the bit becomes "1". 2z is a bit indicating that it is in use, and data register 8
Used for exclusive write control to.

FIG. 5 shows the bit assignments of the command/status register 11.

20 is a data output bit, and the CPU sets the bit to 1.
When writing, signal lines 109-1 to 109-n and 111
Signals flow from -1 to 111-n.

Data is sent from the FI I/O memory 9 to the data register 10. The 21st bit is an empty bit, and becomes rlJ when there is no data in the FIFO memory 9.

Next, the operation of the above-mentioned apparatus will be explained by taking as an example the case where data is transferred from processor module PM-1 to PM-2. FIG. 6 shows an operation flowchart of the processor CPU3-1 included in PM-1 during transmission processing. First, CPU3-1 confirms that the data register of the other processor module PM-2 is not in use. 6. Specifically, it is determined whether the 2z bit (in-use bit) of the command/status register at address 200H is "0". If the result of this determination is "1", wait until it becomes "0", and if it is "0", set it to "1" and move on to the next operation. Note that this rOJ check and "1" set operation must be performed exclusively, and test and
Do it as a set.

Next, the 21 bits (full bit) at address 200H are
Check to see if there is free space in the FIFO memory. If it is "1", wait until it becomes "0".

If it is "0", write the transfer data to address 201H-200H+n, then write the 20 bits of number 200H (
Data is sent to the FIFO memory by writing a '1' to the data input bit).

FIG. 7 shows the reception processing flow of the CPU 3-2 included in the processor module PM-2 on the receiving side. The CPU on the receiving side first checks the 21 bits of the command/status register at address 1000H and determines whether there is data in the FIFO memory.

If it is "1", wait for this to become rOJ,
If it is "0", write 1 to the 20-bit data output bit at address 100OH, and after loading the data from the FIFO memory to the data register,
+ Performs reception processing of data in the data register at address n.

According to this embodiment, the next data can be transferred from the transfer side processor without waiting for the receiving side processor to finish processing the transferred data, and the data transfer processing time can be shortened, thereby increasing the throughput of inter-processor communication. be able to.

〔Effect of the invention〕

As described below, according to the present invention, it is possible to transfer the next data from the transfer side processor without waiting for the receiving side processor to finish processing the transfer data, and also to perform inter-processor data transfer with a short processing time. You can build a multiprocessor system with high data transfer throughput.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a multiprocessor system. Part 2 is a configuration diagram of a FIFO buffer device, Figure 3 is a memory map of a multiprocessor system, Figure 4 is a bit assignment diagram for command/status 7, and Figure 5 is a diagram of command/status 7.
Bit allocation diagram of status register 11, Figure 6 is a flowchart of transmitting side CPC processing, Figure 7 is receiving side CP
A processing flowchart of U is shown. 1... Common bus, 2... Processor module,
3...CPU, 4...Local memory, 5...
Buffer FIFO device, 6...Address decoder, 7
...Command/Status register, 8...Data register, 9...FIFOllo...Data register, 11...Command/Status register, 12.
...Address decoder, 13...Local bus.

Claims (1)

[Claims] between first and second processors, a first register to which data can be written by the first processor, a second register to which data can be read from the second processor, and a space between the first and second registers; a first-in, first-out device that operates to take in data in the first register in response to an instruction from the first processor and output data to the second register in response to an instruction from the second processor. buffer memory means of the form, such that the second processor receives, via the second register, data written by the first processor to the buffer memory means via the first register. A data transfer method between multiple processors characterized by the following.