JPS6285016U - - Google Patents

Info

Publication number
JPS6285016U
JPS6285016U JP17712885U JP17712885U JPS6285016U JP S6285016 U JPS6285016 U JP S6285016U JP 17712885 U JP17712885 U JP 17712885U JP 17712885 U JP17712885 U JP 17712885U JP S6285016 U JPS6285016 U JP S6285016U
Authority
JP
Japan
Prior art keywords
output terminal
terminal
signal
power supply
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17712885U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17712885U priority Critical patent/JPS6285016U/ja
Publication of JPS6285016U publication Critical patent/JPS6285016U/ja
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例におけるミユーテイ
ング装置のブロツク図、第2図は本考案の他の実
施例のミユーテイング装置の回路図である。 1……ラツチ回路、2……制御端子、3……出
力端子、4……電源端子、5……スイツチ回路、
51……セツト用スイツチ、52……リセツト用
スイツチ、7……信号減衰回路、8……信号入力
端子、9……信号出力端子。
FIG. 1 is a block diagram of a muting device according to one embodiment of the present invention, and FIG. 2 is a circuit diagram of a muting device according to another embodiment of the present invention. 1... Latch circuit, 2... Control terminal, 3... Output terminal, 4... Power supply terminal, 5... Switch circuit,
51...Set switch, 52...Reset switch, 7...Signal attenuation circuit, 8...Signal input terminal, 9...Signal output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 制御端子にセツト及びリセツト用スイツチ回路
が接続され、出力端子が高レベルもしくは低レベ
ルに切換り、又電源端子の電圧解除により出力端
子がリセツトきれるラツチ回路とその出力端子に
セツトもしくはリセツト状態を表示する表示器と
同じく出力端子に信号を減衰させる手段とが接続
されたミユーテイング装置。
A set and reset switch circuit is connected to the control terminal, and the output terminal is switched to high or low level, and a latch circuit that resets the output terminal when the voltage of the power supply terminal is released, and the set or reset status is displayed on the output terminal. A muting device that has a signal attenuating device connected to its output terminal as well as a display device that outputs a signal.
JP17712885U 1985-11-18 1985-11-18 Pending JPS6285016U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17712885U JPS6285016U (en) 1985-11-18 1985-11-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17712885U JPS6285016U (en) 1985-11-18 1985-11-18

Publications (1)

Publication Number Publication Date
JPS6285016U true JPS6285016U (en) 1987-05-30

Family

ID=31118038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17712885U Pending JPS6285016U (en) 1985-11-18 1985-11-18

Country Status (1)

Country Link
JP (1) JPS6285016U (en)

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