JPS6284919A - Machining condition detecting method and its device for electric discharge machine - Google Patents

Abstract

PURPOSE:To enable machining condition to be expressed in a pattern convenient for use, by showing a normal discharge condition by a proportion, in which a number of normal discharges are generated in a predetermined time, while the other condition by a proportion in which a time of said other condition appears in a predetermined time. CONSTITUTION:A power supply unit 19 in a machining circuit 3 charges capacitors Cd1Cn with predetermined voltage of a DC power supply 11 by actuating a base driving circuit 17, and predetermined electric discharge machining is performed by an insulation breakdown of opposed electrodes 9. And a machining condition detecting circuit 5 detects a normal discharge by a predetermined drop of interpole voltage VG, waiting for the capacitors being charged after their normal discharge and detecting a condition of the interpole voltage to be in high, intermediate and low potentials. By these detec tion signals, an information output circuit 7B shows a normal discharge condition by a proportion, in which a number of normal discharges are generated in a predeter mined time, while an abnormal condition of no discharge, contamination, short-circuit, etc. by a proportion of a time, said abnormal condition appears, to the time of the other condition in a predetermined time. In this way, a machining condition can be expressed in a pattern convenient for use.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a machining state detection method and apparatus for an electrical discharge machining apparatus having a capacitor discharge circuit.

[Description of prior art]

Conventional so-called non-storage electrical discharge machining apparatuses that do not have a capacitor in their discharge circuits are equipped with a machining state detection device that can effectively detect machining states. As an example of this, the pulse voltage applied between the electrodes via the transistor switch circuit is compared with the ilt\- potential, and the appropriateness of the discharge state is detected when the voltage between the electrodes is at a predetermined potential, and the detection signal is There is an example in which a processing pulse power source, an inter-electrode prevention device, a processing fluid supply device, a state control device, etc. are properly controlled based on the above (Japanese Patent Publication No. 47-50277).

However, in conventional electrostatic or electromagnetic energy storage type electrical discharge machining apparatuses having a capacitor in the discharge circuit, a machining state detection method and apparatus that can effectively detect the machining state have not been developed.

Energy storage type electrical discharge machining equipment is required for electrical discharge machining of superalloys, for example, at 150A! It has the advantage of being able to easily obtain a peak current with a high output of ￥ degrees with a relatively small-scale and inexpensive circuit. Therefore, if this energy storage type electrical discharge machining device can be equipped with a machining state detection device that can effectively detect the machining state, the energy storage type electrical discharge machining device can perform advanced electrical discharge machining on highly flexible workpiece materials. This means that an electrical discharge machining device can be provided.

In addition, the electrical discharge machining state detection device not only outputs the current state of the inter-electrode voltage as detection information, but also detects predetermined machining states such as normal discharge state, non-discharge state, contamination state, short circuit state, etc. based on this current state. If it can be expressed in a form that is convenient for use, it will be possible to judge the machining state easily and accurately, and it will also be possible to efficiently operate the υ1m equipment, such as the gap control equipment U, etc.

[Purpose of the invention]

In view of the above points, the present invention effectively detects the machining state of an energy storage type electrical discharge machining device, and determines a predetermined machining state such as a normal discharge state, a non-discharge state, a contaminated state, or a short circuit state based on this current state. It is an object of the present invention to provide a method and apparatus for detecting the machining state of an electric discharge machining apparatus that can be expressed in a form that is convenient for use.

[Summary of the invention]

In order to achieve the above object, the present invention detects a state of normal discharge when a voltage signal between electrodes of an electrical discharge machine having a capacitor discharge circuit drops by a predetermined value,
Detection of other states is performed by waiting for the capacitor to be charged after normal discharge, and the normal discharge state is determined by the ratio of the number of normal discharges occurring within a predetermined time to the standard. The other states are expressed as a percentage of the time during which that state appears within a predetermined period of time relative to other states.

Further, the machining state detection device of the electric discharge machining apparatus includes a signal comparison section that compares the machining voltage signal of the electric discharge machining apparatus having a capacitor discharge circuit with a reference potential, and a signal comparison section that compares the machining voltage signal of the electric discharge machining apparatus having a capacitor discharge circuit with a reference potential. a first machining state detection section that detects a state of discharge; a detection prohibition section that prohibits detection of other machining states until the capacitor is charged after the detection section detects a state of normal discharge; an M2 machining state detection section that detects another machining state based on the comparison result of the signal comparison section on the condition that detection is not prohibited by the M2 machining state detection section;
The number of normal discharges detected by the state detection section is counted for a predetermined period of time, this count is calculated as a ratio to the standard, and the second
and an information output circuit that accumulates the occurrence time of other machining states detected by the detection unit for a predetermined period of time and calculates this cumulative time as a ratio to other processing states, and the detected information is conveniently used. I expressed it in a form and output it.

[Explanation of Examples]

An embodiment of this invention will be described below.

Figure 1 is a block diagram showing the electric circuit of an electrostatic discharge discharge machining device, Figure 2 is a circuit diagram of the machining state detection circuit, and Figure 3 is a circuit diagram of the machining state detection circuit.
The figure is a time chart showing signal states of various parts, FIG. 4 is a circuit diagram of the abnormal discharge prevention circuit, and FIG. 5 is a circuit diagram of the information output circuit.

As shown in FIG.
, T2, and T3, and the circuit 5 and four terminals T4, T5, To, and T3.
The abnormal discharge prevention circuit 7A and the information output circuit 7B are connected through the circuit 7. Abnormal discharge prevention circuit 7
A is connected to the terminal T8, and the terminal T8 is connected to the base drive circuit 17.

The processing circuit 3 includes a series circuit formed by a counter electrode (processing gap) 9, a processing DC power source 11, a current limiting resistor 13, and a power transistor 15, and a base drive circuit 17 connected to the base of the power transistor 15. , and an energy storage type power supply unit 19 connected in parallel with the counter electrode 9.

The base drive circuit 17 outputs a pulsed base voltage signal VB as shown in FIG. 3(b), and makes the power transistor 15 conductive when this signal is at a high level. The power supply unit 19 is configured by connecting n series circuits of relays (RY1 to RYn) and capacitors (C1 to Cn) in parallel, and its capacity can be changed by switching and controlling the n relays RY1 to RYn. It's Toshide. Then, the power supply unit 19 receives a predetermined voltage from the DC power supply 11 through the operation of the base drive circuit 17, stores a predetermined electric energy, and releases the energy between the electrodes 9 at once due to dielectric breakdown of the electrodes 9. Perform electrical discharge machining.

The voltage between electrodes VGAD of the processing circuit 3 is connected to the terminal T+.

It is given to T2. The base voltage VB output from the base drive circuit 17 is applied to the terminal T3 as a base voltage signal VB.

As shown in FIG. 2, the machining state detection circuit 5 includes a signal comparison section 21, a first machining state detection section 23, and a detection prohibition section 25.
and a second machining state detection section 27.

The signal comparator 21 includes a voltage level converter 29 connected to terminals TI and T2, and two comparators 31' and 33 connected to the converter 29.

The voltage level converter 29 inputs a voltage between electrodes VGAI) through a high impedance, and is proportional to the voltage between electrodes VGAI), and has a voltage level that is proportional to the voltage between electrodes VGAI) and whose maximum amplitude does not exceed the maximum input range of the comparators 31 and 33. outputs a voltage signal VG. The comparators 31 and 33 input the input electrode voltage signal VG,
Two high and low levels of reference potentials V+ and V2 are compared, and comparison result signals C81 and C82 which become high level when the inter-electrode voltage signal VG is greater than the reference potentials V+ and V2 are output, respectively.

The first machining state detection unit 23 detects the state of normal discharge, and as shown in the figure, includes an inverter 35, a monostable multivibrator 37, and three Nant gates 39, 41.4.
It consists of 3 and.

The monostable multivibrator 37 inputs the comparison result signal C81 of the high potential comparator 31, and is triggered by the comparison result signal C81 becoming low level when the inter-electrode voltage signal VG becomes lower than the reference potential V1. As shown in a) and (C), the discharge prediction signal Ex is applied for a preset time T1.
Output SPK. The time T1 is experimentally determined as the time required for the electrode-to-electrode voltage to reach approximately zero potential from the charging potential. Note that the actual discharge time depends on the capacitor capacity ω
If it is constant, then it is almost constant. This emission measurement department @EX
The SPK predicts that normal discharge will soon occur and serves as a signal that regulates the end point of normal discharge.

The inverter 35 receives the comparison result signal C8 from the low potential comparator 33.
Enter 2 and invert it.

The three Nant gates input the output of the monostable multivibrator 37 and the output of the inverter 35 to their input terminals,
It outputs a signal SP which becomes low level when both signals are at high level. That is, the Nantes gate 39 is shown in FIG.
The discharge prediction signal Ex SPK shown in C) is at a high level, and the electrode gap voltage signal VG is based on r! When the P-potential is less than 2 below the potential, a signal SP is output at a low level indicating that discharge has actually started.

The Nant gate 43 receives this signal SP at one input terminal, and outputs a normal discharge detection signal SPK which becomes high level as this signal @SP becomes low level.

The Nant gate 41 inputs the normal discharge detection signal SPK and the discharge prediction signal EXSPK, and outputs a signal that becomes low level when both signals are at high level, and when the discharge prediction signal ExSPK goes to high level. A low level signal is output to the Nant gate 43 for a certain period of time. The Nant gate 43 is set to a low level when two low-level human input signals are both set to a high level, in other words, when the discharge prediction signal EXS1K is set to a low level and the comparison result signal @C82 is set to a high level. It comes to be

Therefore, the first machining state detection section 23 outputs the normal discharge detection signal SPK as shown in FIG. The falling point indicates the end point of normal discharge. The normal discharge detection signal @SPK is output from the terminal T7 and is used by the abnormal discharge prevention circuit 7A and the information output circuit 7B.

The detection prohibition section 25 prohibits detection of other machining states under predetermined conditions, and includes two Nantes gates 45, 47, a presettable counter 49, and three inverters 51.
53.55.

The Nant gate 45 has a base voltage signal VB at its input terminal.
and the output Q of the presettable counter 49 is input. The presettable counter 49 inputs the normal discharge detection signal SPK to a preset input terminal, and inputs the output of the Nant gate 45 to another input terminal. Therefore, the four presettable counters count the number of pulses of the inverted signal of the base voltage signal VG in synchronization with the rise of the normal discharge detection signal SPK, and keep their output at high level until the counted value becomes the same as the set data. Outputs a signal to

The inverter 53 inverts the output of the presettable counter 49 and keeps the output low while the output Q of the presettable counter 49 is at a high level. Since the Nant gate 47 inputs the output of the inverter 53 to its input terminal, in synchronization with the rise of the normal discharge detection signal SPK, the output is kept at a low level for a predetermined time TTAB determined by the data setting of the presettable counter 49. This will be the case. On the other hand, an inverted signal of the base voltage signal VB is input from the inverter 51 to the other input terminal of the Nant gate 47. Therefore, the Nant gate 47 sets its output to high level while the presettable counter 49 is outputting a high level signal, and otherwise outputs the base voltage signal ■
8 will be output immediately.

The inverter 55 inverts the signal output from the Nandt gate 47 and outputs it.

Therefore, as shown in FIG. 3(e), the detection prohibition unit 25 forcibly sets the base voltage to a low level for a predetermined time (section) TT A B in synchronization with the rise of the normal discharge detection signal SPK. Outputs the inverted signal. Hereinafter, this signal will be referred to as a detection prohibition signal TAB. Detection prohibited part @TA
B is supplied to a second machining state detection section 27, which will be explained below, and serves to regulate detection of other machining states.

The second machining state detection unit 27 detects whether the machining voltage signal VG is above the reference potential V1 (VG > V+), in the middle (V, + ≧VC>■2), or below the reference potential V2. (Vo≦V2) is detected. The second machining state detection unit 27 includes a monostable multivibrator 57 and three Nant gates 59, 61, and 63.
, two flip 70 knobs 65, 67, three inverters 69, 71, 73, and three AND gates 7.
5.77.79.

The monostable multivibrator 57 inputs the base voltage signal vn, and in synchronization with the rising edge of this signal VB, only 50 to 1
A pulse signal P having a frontage level of 00 n5ec is output.

The Nant gate 59 inputs the comparison result signal F''1cs1 and the base voltage signal VB, and outputs an inverted signal of the base voltage signal @VB while the comparison result signal C8I is at a high level.

The flip-flop 65 connects the set terminal S to the Nant gate 5.
The output of the multivibrator 57 is inverted and inputted to the reset terminal R. Therefore, the flip-flop 65 is set by a high level signal of the base voltage signal VB on the condition that the comparison result signal C8I is at a high level, and then reset by a high level pulse signal inputted to the reset terminal. The output Q1 is kept at high level until the next high level signal of the pulse is input to R.

The flip-flop 65 is cleared by the next high-level signal of the pulse input to the reset terminal R. At this time, if a high-level signal is supplied to the set terminal S, the flip-flop 65 is cleared as the pulse becomes low level. It is set immediately and makes its output high level. The effect of outputting a high-level signal from the flip-flop 65 in this way is that the comparison result signal C81 is repeated in a high-level circle. The flip-flop 65 sets its output to low level when the signal applied to the set terminal S becomes low level and then the signal applied to the reset terminal becomes high level.

The AND gate 75 inputs the output signal Q1 of the flip-flop 65 and the detection prohibition signal TAB to its input terminal, and as shown in FIG. A high potential detection signal VHP is outputted from the terminal T4.

The Nant gate 61 inputs the comparison result signal C82 of the low potential comparator 33 and the base voltage signal VB, and similarly to the Nant gate 59, while the comparison result signal C82 is at a high level, in other words, the voltage between electrodes is Signal VG is reference potential■
2, an inverted signal of the base voltage signal VB is output.

Similar to the flip-flop 65, the flip-flop 67 operates based on the pulse signal output from the monostable multivibrator 57 while the comparison result signal O82 is at a high level, in other words, the electrode-to-electrode voltage signal VG is at the reference potential ■.
From the time when the interelectrode voltage signal VG becomes larger than 2, the voltage signal VG becomes less than the reference potential ■2, and then the monostable multivibrator 57
The signal Q that remains high level except for a minute time between pulses until the next low level pulse signal is output.
Outputs 2.

The inverter 71 inverts this signal Q2 so that the electrode-to-electrode voltage signal VG is not greater than the reference potential v2, that is, the reference potential V
A signal indicating at a high level that the value is 2 or less is output.

The Nant gate 79 inputs the signal output from the inverter 71 and the detection prohibition signal TAB, and performs the process as shown in FIG. 3(0).
As shown in FIG. 3, the low potential detection signal VLP, which becomes high level when both signals are high level, is output to the terminal T6.

The inverter 69 outputs the output signal Q1 of the flip-flop 65.
Invert. The Nant gate 63 inputs this inverted signal and the output signal Q2 of the 7-lip 70-tube 67, and outputs a signal that becomes low level when both signals are at high level.

Therefore, the Nant gate 63 outputs a signal that becomes low level when the inter-electrode voltage signal VG is below the reference potential V+ and greater than the reference potential 2, that is, when the inter-electrode voltage signal VG is at the intermediate potential. .

The inverter 73 inverts the output signal of the Nandt gate 63 and outputs a signal that becomes high level when the voltage between electrodes VG is at an intermediate potential. Nant gate 77 is inverter 7
3 and the detection prohibition signal TAB are input, and as shown in FIG. 3 (h), an intermediate potential signal VMP that becomes high level when both signals are at high level is output to terminal T5. do.

As described above, the machining state detection circuit 5 shown in FIG.
Seed detection signals SPK, VHP, VM P.

VLP will be output. The contents of these detection signals can be summarized as follows.

(2) As shown in FIG. 3(d), this detection signal SPK rises synchronously when the voltage between electrodes VG becomes equal to or lower than the reference NQV2, and rises for a predetermined time T1 or the voltage between electrodes VG
This is a signal that falls synchronously when V becomes higher than the reference potential V2, and becomes high level once for a time T2 per normal discharge.

■ Tsubo H This detection signal VHP is as shown in Fig. 3 <r>.
When the interelectrode voltage signal VG is larger than the reference potential V+, that is, when VG>V+, it is a pulse-like signal that is output except for the charging time TTAR.

The pulse waveform is an inverted version of the waveform of the base voltage signal VB. That is, if the base voltage signal j%Vs is used as a clock signal, the high potential detection signal VHP also becomes a clock signal.

■ 1 ・・L: ”VMP This detection signal VvP is, as shown in FIG.
When 1≧VG>V2, this is a pulse-like signal that is output except for the charging time TTAB.

The contents of the pulse waveform are similar to the high potential detection signal VHP.

■ t L = Shiko's detection signal is as shown in Figure 3 ((J)), when the electrode voltage signal @Valfi is less than the reference potential v2, that is,
This is a pulse-like signal that is output except for the charging time TT A B when VG≦V2. The contents of the pulse waveform are the same as those of the detection signals VHP and VMP.

As shown in FIG. 4, the abnormal discharge prevention circuit 7A includes an OR gate 81, a preset counter 83, and a monostable multivibrator 85.

The OR gate 81 inputs high potential and intermediate potential detection signals and normal discharge detection signals V) (P, VM P, and SPK, respectively, and when a high level signal appears in any of these input signals, a high level signal is output. Output.

The preset counter 83 connects the preset terminal PE to the OR gate, and connects the clock input terminal GK to the terminal T6.
and connect the data setting terminal PD to the data input terminal T.
+o, and when a high level signal appears on the preset terminal PE, the setting data is preset, and then,
Count the number of pulses input to the clock input terminal CK,
When the count value exceeds the set data, a count over signal CO that becomes high level is output.

The monostable multivibrator 85 inputs the count over signal CO, and outputs an interrupt signal INT that becomes high level for a predetermined time when this signal CO becomes high level. The interruption signal INT is a signal for temporarily bringing the base voltage VB to a low level.

As described above, the abnormal discharge prevention circuit 7A outputs the interruption signal INT from the monostable multivibrator 85 when the machining state continues and is in a short circuit state, in other words, when a harmful current is about to be applied to the machining process. It becomes like this. When this interruption signal NT is output, the base drive circuit 17 temporarily turns off the power transistor 15, and the charging of the capacitors C1 to On is temporarily interrupted.

In this way, the abnormal discharge prevention circuit 7A can effectively remove the current harmful to electric discharge machining, so it is possible to set the optimum current density in response to changes in the machining area, thereby preventing damage to the electrode or the machined product. do not have.

Furthermore, machining of so-called bite portions and through-machining, which may result in an extremely small machining area, improves machining and finishing at the separation portions.

As shown in FIG. 5, the information output circuit 7B is composed of four counters 87, 89, 91, 93, a microprocessor 95, a memory 97 storing a processing program, and an interrupt timer 99. ing. The information output circuit 7B outputs the detection signals VHP, VM P, VL PSS
Input PK and check the no-discharge state, electrode contamination state, short-circuit state,
It outputs the normal discharge state in a form that is convenient for use.

Each of the counters 87 to 93 receives the processing state detection signals VHP, VMP, and VL PSSPK as information sources, and counts the number of pulses of the signals input within a predetermined time T. The count values of counters 87 to 93 are n+, n2+03. Suppose that N. Note that the pulse input to the counter 93 is once per normal discharge (see Fig. 3(d)), but the pulse input to the counter 93 is once per normal discharge (see Fig. 3(d)).
．． The number of pulses input to 91 is such that one or more pulses are input at once when the electrode-to-electrode voltage signal VG enters a predetermined potential region (see Figure 3 ('), (g>, (h)). .

The microprocessor 95 controls the counter 87 at every predetermined time T.
93 is read, and the following steps 2 to 3 are performed based on the program stored in the memory 97.

■, '%SPK
The processing microprocessor 95 reads the contents of the counter 93 based on the interrupt signal from the timer T, and calculates the ratio of the counted value to the standard [%5PKJ] using the following formula.

%5PK= (N/Ns xloo)・・・・・・(1
) Here, N is a count value and NS is a standard value in an ideal state.

The standard value NS in an ideal state is obtained by dividing the measurement time T by one charge/discharge cycle TC as Ns = T/TC. Here, the charge/discharge cycle TC is defined as the capacity of the capacitor is C1, the current limiting resistance value for charging the capacitor is R1, the off time of the base voltage VB is Ton, and the off time is Ton.
F r-, the correction value of the capacitor charging time constant can be determined by the following equation, if the standard discharge time per normal discharge of A1 is Tdis.

Tc-A-c-R-(Ton+TOFF)/7o
r1+Tdi3 (2) The first term on the right side indicates the time required to charge the voltage between electrodes (VGAI) to 63% of the predetermined voltage when A=1. In this example,
The no-load voltage was 100 volts, the high potential reference potential was 60 volts, and A=1.4. At this time, the first term on the right side of equation (2) represents the time required to charge to approximately 75% of the no-load voltage. The discharge time T dis is a value determined by the capacitor capacity 1c and the impedance of the discharge circuit.

This value is stored in memory in advance, and the capacitor 0
It is preferable to read a predetermined value according to the combination of 1 to Cn.

If the value "%5PKJ" determined by the above equation (1) is larger than 100, the microprocessor 95 sets it to 100 and temporarily stores the determined value.

The microprocessor 85 reads the contents of the counters 87, 89, and 91 based on the interrupt signal from the timer 99, and calculates the following equation.

n = n 1 + n 2 + n 3 ...
(3)%0PN=(n 1/n)<100-%5P
K)・・・・・・(4) %POL= (n2/n) (100-%
5PK)・・・・・・(5) %5HT= (n 3/n ) (100-%
5PK)......(6) Here, [%○PNJ represents the percentage of no discharge state, [%POLJ represents the percentage of contaminated state, [%○PNJ]
5HTJ represents the percentage of short circuit state.

m, L nim 匪m The microprocessor 95 calculates the value [%
5PKJ, ``%○PNJ, [%POLJ, ``%5HTJ
output to a predetermined device. The predetermined devices include a display device, a gap control device, a machining fluid control device, and other adaptive control devices (not shown).

In the example of a display device, normal discharge, no discharge, contamination, and short circuit are displayed in the order of ioo, o, o, o, 80°10.5.5, or 60.10, 10.20. Therefore, the operator can accurately grasp the machining status by looking at these displays.

Also, in the example of a gap control device, ``Based on %0PNJ,
For example, if this value is small, it is possible to shorten the gap and increase the processing speed.

Furthermore, it is possible to control the base drive circuit 17 based on %POLJ and insert a minute discharge interruption portion in the middle of machining until %POLj reaches a predetermined small value.

Furthermore, temporary interruption control similar to that performed by the abnormal discharge prevention circuit 7A based on "%5HTJ" is also possible.

〔Effect of the invention〕

As described above, according to the present invention, the current state of the energy storage type electrical discharge machining device is effectively detected, and based on this current state, a predetermined machining state such as a normal discharge state, a non-discharge state, a contaminated state, a short circuit state, etc. be able to express it in a form that is convenient for use.

[Brief explanation of drawings]

The drawings all show examples, and Fig. 1 is an overall diagram showing the electric circuit of the electrical discharge machining device, Fig. 2 is a circuit diagram of the machining state detection circuit, and Fig. 3 shows the signal status of each part of the machining state detection circuit. In the time chart shown, Figure M4 is a circuit diagram of the abnormal discharge prevention circuit, and Figure 5 is a circuit diagram of the information output circuit. 1... Electric discharge machining device 3... Machining circuit 5... Machining state detection circuit 7A... Abnormal discharge prevention circuit 7B... Information output circuit 21... Signal comparison section 23... First machining State detection section 25...Detection prohibition section 27...Second machining state detection section Va...Extreme fill pressure signal VB...Base voltage signal ExSPK...Discharge prediction signal SPK...Normal discharge detection signal TAB...Detection prohibition signal VHP...High potential detection signal VMP...Intermediate potential detection signal VLP...Low potential detection signal rNT...Interruption signal %SPK...Discharge data %OPN...None Discharge data %POL...Contamination data %SHT...Short circuit data 91:-:Go1be:Representative Patent attorney Yasu Miyoshi Man's employment,',
Knee:, - Zenjo Procedures Net 17 Official Book (Spontaneous) May 1986/Fuday Director General of the Japan Patent Office Michibe Uga 1, Indication of the case Japanese Patent Application No. 60-222794 2, Name of the invention
Machining state detection method and device for electric discharge machining equipment 3,
Relationship with the case of the person making the amendment Patent applicant address (residence) 20 OTr Ishida, Isehara City, Kanagawa Prefecture Name (name) AMADA Co., Ltd. Representative Ten 1) Mizoyo 4, Agent address 105 Minato-ku, Tokyo Toranomon 1-2-3
No. Toranomon No. 5th Floor, Building Tel: Tokyo (504> No. 3075) 5. Full text of the specification subject to amendment. 6. As per group by content of amendment. 7. List of attached documents, full text of revised specification.
1 or more copies Description 1. Title of the invention: Method and device for detecting machining status of an electrical discharge machining device 2. Claims (1) A voltage signal between electrodes of an electrical discharge machining device having a capacitor discharge circuit has a predetermined drop. By doing this, the state of normal discharge is detected, and other states are detected when the capacitor is charged after this normal discharge, and the state of normal "discharge" is detected when the capacitor is charged. The number of normal discharges that occur within a certain period of time is expressed as a percentage of the standard, and other states are expressed as the percentage of the time when that state appears within a predetermined period of time relative to other states of the pond. A method for preventing abnormal discharge in an electrical discharge machining device characterized by: (2) a signal comparison unit that compares an inter-electrode voltage signal of an electrical discharge machining device having a capacitor discharge circuit with a reference potential; a first machining state detection section that detects a normal discharge state; and a detection prohibition section that prohibits detection of other machining states until the capacitor is charged after the detection section detects a normal discharge state. and a second machining state detection section that detects another machining state based on the comparison result of the signal comparison section on the condition that the prohibition section does not prohibit detection; The number of normal discharges that occur during a predetermined period of time is counted, and this coefficient is determined as a percentage of the standard, and the occurrence times of other machining states detected by the second detection section are accumulated for a predetermined period of time, and this cumulative QL time R'J is calculated.
An abnormal discharge prevention device for an electrical discharge machining machine, comprising: an information output circuit that calculates the ratio of the current state to that of other states. 3. Detailed Description of the Invention [Field of the Invention] The present invention relates to a machining state detection method and apparatus for an electrical discharge machining apparatus having a capacitor discharge circuit. [Description of the Prior Art] Conventional so-called non-storage electric discharge machining apparatuses that do not have a capacitor in the discharge circuit are equipped with a machining state detection device that can effectively detect the machining state. As an example of this, the pulse voltage applied between the electrodes via a transistor switch circuit is compared with a reference potential, and the appropriateness of the discharge state is detected when the voltage between the electrodes is at a predetermined potential. Based on this, there is an example in which a machining pulse power source, an electrode gap control + wave device, a machining fluid supply device, and a state control device are properly controlled (Japanese Patent Publication No. 47-50277). For the electrostatic type and electromagnetic type energy storage type electrical discharge machining equipment shown on the right, a machining state detection method and device that can effectively detect the machining state have not been developed. It has the advantage of being able to easily obtain a high-output peak current of, for example, 150 A, which is required in electric discharge machining of cemented carbide, etc., with a relatively small-scale and inexpensive circuit. If the device can be equipped with a machining state detection device that can effectively detect the machining state, it is possible to provide an energy-storage electrical discharge machining device that can perform advanced electrical discharge machining on highly flexible workpiece materials. In addition, the electrical discharge machining state detection device not only outputs the current state of the inter-electrode voltage as detection information, but also determines the normal discharge state, non-discharge state, contamination state, short circuit state, etc. based on this current state. If the machining state of the machine can be expressed in a form that is convenient for use, the machining state can be easily and accurately judged, and adaptive control devices such as gap control devices can be operated efficiently. [Object of the invention] In view of the above points, the present invention effectively detects the machining state of an energy storage type electrical discharge machining device, and determines a predetermined machining state such as a normal discharge state, a non-discharge state, a contaminated state, or a short circuit state based on this current state. It is an object of the present invention to provide a method and device for detecting the machining state of an electrical discharge machining apparatus that can be expressed in a form that is convenient for use. The state of normal discharge is detected when the inter-electrode voltage signal of the electric discharge machining device having the fil electric circuit drops by a predetermined value, and the state of the song is detected when the capacitor is charged after this normal discharge has occurred. Detect it by holding the
The state of normal discharge is expressed as a ratio of the number of normal discharges occurring within a predetermined time to the standard, and the other states are expressed as the ratio of the time when that state appears within a predetermined time to other states of the cell. I tried not to express it. In addition, the machining state detection device of the electric discharge machining device is equipped with a capacitor M.
a signal comparison section that compares a predetermined voltage signal of the electric discharge machining device having an electric circuit with a reference potential; and a first machining state detection section that detects a state of normal discharge when the voltage signal between electrodes drops by a predetermined amount. , a detection prohibition section that prohibits detection of the machining state of the battery after the detection section detects a state of normal discharge until the capacitor is charged; a second machining state detection section that detects another machining state based on the comparison result of the comparison section; and ff1t.
The number of normal discharges detected by the first state detecting section is counted for a predetermined period of time, and this S1 number is calculated as a ratio of 1 to the standard, and the occurrence time of the machining state of the song detected by the second detecting section is calculated for a predetermined period of time. The present invention includes an information output circuit for calculating the cumulative time as a percentage of the cumulative time in other states, and outputs the nine detection reports in a format convenient for use. [Description of Embodiment] An embodiment of the present invention will be described below. Figure 1 is a block diagram showing the electric circuit of an electrostatic discharge discharge machining device, Figure 2 is a circuit diagram of the machining state detection circuit, and Figure 3 is a circuit diagram of the machining state detection circuit.
The figure is a time chart showing signal states of various parts, FIG. 4 is a circuit diagram of the abnormal discharge prevention circuit, and FIG. 5 is a circuit diagram of the information output circuit. As shown in FIG. 1, the electric discharge machining apparatus 1 includes a machining circuit 3 for performing electric discharge machining, and this circuit 3 and three terminals T+.
, T2, and a machining state detection circuit 5 connected via T3.
and the circuit 5 and the four terminals T4, T5, Ta, Ty
The abnormal discharge prevention circuit 7A and the information output circuit 7B are connected through the circuit. Abnormal discharge prevention circuit 7A
is connected to the terminal T8, and the terminal T8 is connected to the base drive circuit 17. The processing circuit 3 includes a series circuit formed by a counter electrode (processing gap) 9, a processing DC power source 11, a current limiting resistor 13, and a power transistor 15, and a base drive circuit connected to the base of the power transistor 15. 17, an energy storage type power supply unit 19 connected in parallel with the counter electrode 9;
It consists of The base drive circuit 17 outputs a pulsed base voltage signal VB as shown in FIG.
The power transistor 15 whose ei is at a high level is made conductive. The power supply unit 19 is a relay (RYl to RY
n ) and capacitors (C1 to Cn) are connected in parallel, and n relays RYI to RYn are connected in parallel.
By controlling the switching, the capacity can be changed. Then, the power supply unit 19 receives a predetermined voltage from the DC power supply 11 through the operation of the base drive circuit 17, stores a predetermined electrical energy, and releases the energy between the electrodes 9 all at once due to the dielectric breakdown of the electrodes 9. Perform electrical discharge machining. The voltage between electrodes VGAp of the processing circuit 3 is the terminal TI. It is given to T2. The base voltage Va output from the base drive circuit 17 is applied to the terminal T3 as a base voltage signal VB. As shown in FIG.
5 and a second machining state detection section 27. The signal comparison section 21 is composed of a voltage level converter 29 connected to terminals T+ and T2, and two comparators 31 and 33 connected to this converter 29. The voltage level converter 29 inputs the inter-electrode voltage VGAD through a high impedance, and is proportional to the inter-electrode voltage VaAp, and has a voltage level that does not exceed the maximum input range of the comparators 31 and 33 even at the maximum amplitude. outputs a voltage signal VG. Comparators 31 and 33 compare the input interpole voltage signal VO with two high and low levels of reference potentials V+ and V2, and when the interpole voltage signal VG is greater than the first reference V+ and V2, it becomes high level. Comparison result signals C81 and C82 are output, respectively. The first machining state detection unit 23 detects the state of normal discharge, and as shown in the figure, includes an inverter 35, a monostable multivibrator 37, and three Nant gates 39, 41, 4.
It consists of 3 and. The stable multi-bye break 37 inputs the comparison result signal C81 of the high potential comparator 31, and is triggered by the fall of the comparison result signal C81 when the voltage signal VG becomes lower than the reference potential V+. ), as shown in (C), the discharge prediction signal Ex is applied for a preset time T1.
Output SPK. The time T1 is experimentally determined as the time required for the voltage to reach approximately zero potential from the charging potential due to normal discharge. Note that the actual discharge time is approximately constant if the number of capacitors is 8 ports. The inverter 35 receives the comparison result signal C8 from the low potential comparator 33.
Enter 2 and invert it. The Nant gate 39 inputs the output of the monostable multivibrator 37 and the output of the inverter 35 to its input terminals,
It outputs a signal QSP which becomes low level when both signals are at high level. That is, the Nantes gate 39 is shown in FIG.
When the discharge electron temperature measurement MEx SPK shown in C) is at a high level and the interelectrode voltage signal vah<base ring potential V2 or less, a signal SP indicating at a low level that discharge has actually started is sent. Output. The Nant gate 43 receives this signal SP at one input terminal, and outputs a normal discharge detection signal SPK which becomes high level as this signal SP becomes low level. The Nant gate 41 inputs the normal discharge detection signal SPK and the discharge prediction signal ExSPK, and outputs a signal that becomes low level when both signals are at high level, and when the discharge prediction signal EXSPK goes to high level. A low level signal is output to the Nant gate 43 for a certain period of time. The Nant gate 43 operates when two low-level human power signals are both set to high level, in other words, the discharge prediction signal Ex SP
When K is set to a low level and the comparison result signal C82 is set to a high level, it is set to a low level. Therefore, the first machining state detection section 23 outputs the normal discharge detection signal SPK as shown in FIG. 3(d). The normal discharge detection signal SPK is output from the terminal T7 and is used by the abnormal discharge prevention circuit 7Δ and the information output circuit 7B. The detection prohibition section 25 prohibits detection of other machining states under predetermined conditions, and includes two Nant gates 45, 47, etc., a presettable counter 49, and three inverters 51, .
53.55. The Nant gate 45 has a base voltage signal v8 at its input terminal.
and the outputs Q of four presettable counters are input. The presettable counter 49 inputs the normal discharge detection signal SPK to a preset input terminal, and inputs the output of the Nant gate 45 to another input terminal. Therefore, the presettable counter 49 starts counting the number of pulses of the inverted signal of the base voltage signal VG in synchronization with the rise of the normal discharge detection signal SPK, and keeps its output at a high level until this counted value becomes the same as the set data. Outputs the signal. The inverter 53 inverts the output of the presettable counter 49 and makes the output low level while the output Q of the presettable counter 49 is at high level. Since the Nant gate 47 inputs the output of the inverter 53 to its input terminal, in synchronization with the rise of the normal discharge detection signal @SPK, the predetermined time TT A B determined by the data setting of the presettable counter 49 is reached. On the other hand, the inverted signal of the base voltage signal VB is input from the inverter 51 to the other input terminal of the Nant gate 47. Therefore, the Nant gate 47 outputs the presettable counter 49 to a high level. While the level signal g is being output, the output is set to high level, and at other times, the base voltage signal VB is output.The impark 55 inverts and outputs the signal output from the Nandogoos 1 to 47. Therefore, as shown in FIG. 3(e), the detection prohibition unit 25 forcibly maintains the low level for a predetermined time (section) TTAB in synchronization with the rise of the normal discharge detection signal SPK. An inverted signal of the base voltage signal is output.Hereinafter, this signal will be referred to as a detection prohibition section jThTAB.The detection prohibition signal TAB is supplied to the second machining state detection section 27, which will be explained below, and is used to detect other machining states. The second machining state detection unit 27 determines whether the machining voltage signal VO is above the reference potential V1 (VG>V+) or in the middle (V
+≧VG>V2) or below the reference potential ■2 (VG≦V2). The second machining state detection unit 27 is a monostable multivibrator 5
7, three Nant gates 59.61.63, two negative logic input horn flip-flops 65.67, six three inverters, 7L73, and three AND gates 75.77.79. It consists of The monostable multivibrator 57 inputs the base voltage signal QVn, and synchronizes with the rise of this signal
A pulse signal P having a frontage level of 000 SeC is output. The Nant gate 59 inputs the comparison result signal C81 and the base voltage signal @VB, and outputs a low level pulse when the comparison result signal C81 is at a high level and the base voltage signal VB is at a high level. The flip-flop 65 connects the set terminal S to the Nant gate 5.
9, and the output of the multivibrator 57 is input to the reset terminal R. Therefore, the flip-flop 65 is set by the high level signal of the base voltage signal VB on the condition that the comparison result signal O81 is at the high level, and the flip-flop 65 is set by the high level signal of the base voltage signal VB on the condition that the comparison result signal O81 is at the high level. During this period, the output QI is set to high level. The flip-flop 65 is cleared by the next pulse low-level signal input to the reset terminal R, but if a 1-cor level signal is applied to the reset terminal S, the flip-flop 65 will not be reset and its output will be set to a high level. shall be. This operation of outputting a high level signal from the flip-flop 65 is repeated while the comparison result signal C81 is at a high level. The flip-flop 65 sets its output to the a-level when the signal applied to the set terminal S becomes high level and then the signal applied to the reset terminal becomes low level. The AND gate 75 inputs the output signal Q1 of the flip-flop 65 and the detection prohibition signal TAB to its single input, and as shown in FIG. 3 ( ), both signals are at high level. The high potential detection signal Vl (which becomes high level during
Output P to terminal T4. The Nant gate 61 inputs the comparison result signal C82 of the low potential comparator 33 and the base voltage signal VB, and similarly to the Nant gate 59, while the comparison result signal C82 is at a high level, in other words, the voltage between electrodes is While the signal VGIfi is greater than the reference potential V2, an inverted signal of the base voltage signal VB is output. Similar to the flip-flop 65, the flip-flop 67 is operated based on the pulse signal output from the monostable multivibrator 57 while the comparison result signal C82 is at a high level, in other words, the inter-electrode voltage signal Va is at the base r%. From the point in time when the potential is greater than V2, the electrode-to-electrode voltage signal VG becomes IJ.
Until the quasi-potential becomes lower than the quasi-potential V2 and the next low-level pulse signal is output from the monostable multivibrator 57, a high-level signal Q2 is output. The inverter 71 inverts this signal Q2 and outputs a signal indicating at a high level that the inter-electrode voltage signal Va is not greater than the reference voltage fi2V2, that is, less than the bowl quasi-potential V2. The AND gate 79 inputs the signal output from the inverter 71 and the detection prohibition signal TAB,
As shown in FIG. 3, the low potential detection signal VLP, which becomes high level when both signals are high level, is output to the terminal T6. The inverter 69 outputs the output signal Q1 of the flip-flop 65.
Invert. The Nant gate 63 receives this inverted signal and the output signal Q2 of the flip-flop 67, and outputs a signal that becomes low level when both signals are at high level. Therefore, the AND gate 63 operates as long as the electrode-to-electrode voltage signal VG is less than or equal to the reference potential V1 and greater than the reference potential V2.
That is, it outputs a signal that becomes low level when the electrode-to-electrode voltage signal Va is at an intermediate potential. The inverter 73 inverts the output signal of the Nandt gate 63 and outputs a signal that becomes high level when the electrode voltage signal QVG is at an intermediate potential. AND gate 77 is inverter 7
3 and the detection prohibition signal TAB are input, and as shown in FIG. 3(h), the intermediate potential signals Vi and IP, which are at high level when both signals are at high level, are input to terminal T5. Output to. As described above, the machining state detection circuit 5 shown in FIG.
The seed detection signals SPK, VuP, VMP, and VLP are output. The contents of these detection signals can be summarized as follows. ■ As shown in Fig. 3(d), this detection signal SPK indicates that the voltage between electrodes VG has decreased from the state where V'G>Vl to Vl>VG. A predetermined time T from the moment
This is a signal that becomes high level when V 2 > Va within 1, becomes low level after T 1 k, and becomes high level once for time T2 per normal discharge. ■ 1. ,' and 1/n middle 2V11 PThis detection signal V
) As shown in FIG. 3 ( ), when the electrode voltage signal VG is larger than the reference potential V1, that is, Va
At this time, it is a pulse-like signal that is output except for the charging time TTAB. The pulse waveform is an inverted version of the waveform of the base voltage signal V[+. ■ 1" Gokoki PM This detection signal VvP is, as shown in FIG. 3 (h), when the electrode voltage signal VG is at the intermediate potential, that is,
When ≧VG>V2, this is a pulse-like signal that is output during the charging time TTA [except for 1]. The contents of the pulse waveform are similar to the high potential detection signal VHP. ■ 7' 2qVLP This detection signal is detected when the electrode voltage signal VG is below the reference potential ■2, that is, VG≦■, as shown in Fig. 3 (G).
2, it is a pulse-like signal that is output except for the charging time TT A I'3. The content of the pulse waveform is the detection signal V
It is the same as lIP, V~IP. As shown in FIG. 4, the abnormal fl electricity prevention circuit 7Δ is
It is composed of an OR gate 81, a preset counter 83, and a monostable multivibrator 85. The OR gate 81 inputs high potential and intermediate potential detection signals and normal discharge detection signals Vu P, VM P, and SPK, respectively, and outputs a high level signal when a high level signal appears in any of these input signals. do. The Brisera 1-counter 83 connects the preset terminal PE to the OR gate, and connects the clock input terminal CK to the terminal T.
6, connect the data setting terminal PD to the data input terminal Too, and when a high level signal appears at the preset terminal PE, prehit the setting data, and then set the pulse input to the clock input terminal OK. It counts the number and outputs a count over signal CO which becomes high level when the counted value exceeds the set data. The stable multi-bye break 85 inputs the count over signal CO and outputs an interruption signal QINT that is triggered when the signal C becomes high level and remains high level for a predetermined period of time. The interruption signal INT is a signal for temporarily bringing the base voltage VEI to a low level. As described above, the abnormal discharge prevention circuit 7A outputs the interruption signal qINT from the monostable multivibrator 85 when the machining state continues and is in a short circuit state, in other words, when a harmful current is about to be applied to the machining process. It becomes like this. When this interrupt signal INT is output, the base drive circuit 17 temporarily disconnects the power transistor 15.
The battery will now turn off, and charging of the capacitor +701 to on will be temporarily suspended. In this way, the abnormal discharge prevention circuit 7Δ can effectively remove the current harmful to electrical discharge machining, so it is possible to set the optimum current density according to the change in the machining area λ1, thereby preventing damage to the electrode or the machined product. There is no. In addition, when machining so-called biting portions or through-cutting where the machining area may become extremely small as a result, the machining stability at the separation portion is improved. As shown in FIG. 5, the information output circuit 7B is composed of four counters 87, 89, 91, 93, a microprocessor 95, a memory 97 storing a processing program, and an interrupt timer 99. ing. The information output circuit 7B outputs the detection signals Vl-IP, VM P, VL P
, SPK are input, and the non-discharge state, electrode contamination state, short-circuit state, and normal discharge state are outputted in a convenient format. Each of the /J counters 87 to 93 inputs the machining state detection signals VHP, VMP, VLP, and SPK as information sources, and divides the number of pulses of the signals input within a predetermined time T, respectively. The count values of counters 87 to 93 are n+, n2. Assume that n:+,N. Note that the pulse input to the counter 93 is once per normal discharge (see Fig. 3(d)), but the pulse input to the counter 93 is once per normal discharge (see Fig. 3(d)).
9. The number of pulses input to 91 is such that one or more pulses are input at once when the electrode-to-electrode voltage signal VG enters a predetermined potential region (Fig. 3 ('), (9), (h) ).The microprocessor 95 registers the counter 87 at every predetermined time T.
93 is read, and the following processes 1 to 2 are performed based on the program stored in the memory 97. The microprocessor 95 reads the contents of the counter 93 in response to the interrupt signal from the timer T, and calculates 'IJJ@r%5PKJ for the standard Jtk value using the following equation. %5PK= (N/Ns Xl 00)・・・・・・(
1) Here, N is a count value and NS is a standard value in an ideal state. The standard value NS in the ideal state is obtained by dividing the measurement time T by one charge/discharge cycle TO as N5=T/Tc. Here, the charge/discharge cycle Tc is the 8K gold of the capacitor, the current limiting resistance value for charging the capacitor is R, the on time of the base voltage VB is Ton, and the off time is TOF.
F, the correction value of the capacitor charging time constant is Δ, and the standard discharge time for one normal discharge is Tdis, it can be found by the following equation. Tc=A−C−R・(Too +TOFF)−←T
dis (2) The first term on the right side indicates the time required to charge the voltage between electrodes VGAp to 63% of the predetermined voltage when A=1. In this example, the no-load voltage is 100 volts, and the high potential reference potential is 60 volts.
A=1.4. At this time, the first term on the right side of equation (2) represents the time required to charge to approximately 75% of the no-load voltage. The discharge time Tdis is determined by the capacitor IC and the impedance of the discharge circuit. This value is stored in memory in advance, and the capacitor C
It is preferable not to read a predetermined value depending on the combination of 1 to Cn. If the value ``%5PKJ'' calculated by the above equation (1) is larger than 100, the microprocessor 95 sets it to 100 and temporarily stores the calculated value. The J-85 reads the contents of the counters 87, 89, and 91 based on the interrupt signal from the timer 99, and calculates the following equation. n = n 1 + n 2 + n 3 ...
(3)%0PN=(n 1/n)(100-%5P
K)・・・・・・(4) %POL= (n2/n)(100-%5PK)・
...(5) %3l-IT=(n3/n)(100-%5PK
)...(6) Here, F%○PNJ represents the percentage of no discharge state, "%POLJ" represents the percentage of contaminated state, and "%POLJ" represents the percentage of contaminated state.
S l - I T J represents the short circuit rate. ■The microprocessor 95 is determined as described above.
r % S P K J, “%0PNJ, r % P
OL J, ``Output %5HTJ to a predetermined device.The predetermined device 2 is a display device (not shown) or Ii!l jJi
anti-I2II equipment, machining fluid control equipment, and other adaptive control 5A equipment. In the example of a display device, normal discharge, no discharge, contamination, and short circuit are displayed in the order of ioo, o, o, o, 80°10.5.5, or 60, 10.10.20. Therefore, the operator can accurately grasp the machining status by looking at these displays. Also, in the example of a gap control device, [based on %○PNJ,
For example, if this value is small, it is possible to shorten the gap and increase the processing speed. Furthermore, it is possible to control the base drive circuit 17 based on %POLJ and insert a minute discharge interruption part of 1Φ in the middle of machining until %POLJ reaches a predetermined small value. , "Abnormal discharge prevention circuit 7 based on %S1~ITJ
Temporary center control similar to that performed in A is also possible. [Effects of the Invention] As described above, according to the present invention, the current state of the energy storage type electrical discharge machining device is effectively detected, and based on this current state, the normal discharge state, non-discharge state, contaminated state, and short circuit state are determined. It becomes possible to express a predetermined processed shape fg in a form convenient for use. 4. Brief explanation of the drawings The drawings all show examples. Fig. 1 is an overall diagram showing the electric circuit of the electric discharge machining device, Fig. 2 is a circuit diagram of the machining state detection circuit, and Fig. 3 is the machining state detection circuit. FIG. 4 is a circuit diagram of the abnormal discharge prevention circuit, and FIG. 5 is a circuit diagram of the information output circuit. 1... Electric discharge machining device 3... Machining circuit 5... Machining state detection circuit 7Δ... Normal discharge prevention circuit 7B... Information output circuit 21... Signal comparison section 23... First Machining state detecting section 25...Detection inhibiting section 27...Second machining state detecting section VG...f to voltage signal VB...Base voltage signal Ex SPK...Discharge prediction signal SPK...Normal Discharge detection signal TAB...Detection prohibition signal V) IP...Pi potential detection signal VMP...Intermediate potential detection signal VLP...Low potential detection signal INT...Interruption signal %SPK...Discharge data % OPN...No discharge data %POL...Contamination data %SHT...Short circuit data

Claims (2)

[Claims] (1) The state of normal discharge is detected when the inter-electrode voltage signal of the electrical discharge machining device having a capacitor discharge circuit drops by a predetermined value, and other states are detected only after this normal discharge is performed. The state of normal discharge is expressed as a ratio of the number of normal discharges occurring within a predetermined period of time to a standard,
1. A method for preventing abnormal electrical discharge in an electrical discharge machining apparatus, characterized in that the other states are expressed as a ratio of the time during which the states appear within a predetermined period of time to other states. (2) A signal comparison unit that compares an inter-electrode voltage signal of an electric discharge machining device having a capacitor discharge circuit with a reference potential, and a first process that detects a normal discharge state when the inter-electrode voltage signal drops by a predetermined value. a state detection section; a detection prohibition section that prohibits detection of other machining states after the detection section detects a normal discharge state until the capacitor is charged; and a detection prohibition section that prohibits detection of other processing conditions until the capacitor is charged; As a condition, the number of normal discharges detected by the second machining state detection section that detects another machining state based on the comparison result of the signal comparison section and the first machining state detection section is counted for a predetermined period of time, and this coefficient is calculated. an information output circuit that calculates the cumulative time as a percentage of the standard, accumulates the occurrence time of other machining states detected by the second detection unit over a predetermined period, and calculates the cumulative time as a percentage of the other processing states;
An abnormal discharge prevention device for electrical discharge machining equipment, comprising: