JPS6284488A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve an action margin by driving a MOSFET short-circuiting a pair of bit lines at the 1st clock, precharging a precharging MOSFET at the 2nd clock delayed by the prescribed time and driving two boost circuit at the 3rd and fourth clocks. CONSTITUTION:When the operation enters a precharge period, a clocks is generated from a clock generator CGA to turn on the shorting MOSFET T1, and all pairs of bit lines are shorted. After the prescribed time expires, a CGB generates a clock, and precharges gate nodes N of precharge MOSFETs T2 and T3 at a VCC. After the prescribed time expires, a CGC at the side of the boost circuit 1 generates a clock, and the gate of the MOSFET T4C is boosted more than the VCC, and conducted. Then a capacitor C1C boosts the node N. After the prescribed time expires, a CGD at the side of the boost circuit 2 generates a clock to further boost the node N. In such a way each bit line is spirally charged up to a VCC level, and therefore a change in a current at the time of precharge is decreased to improve the action margin.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device that stores information in the form of charge in a capacitor, and particularly to improvements in its bit line precharge circuit.

[Technical background of the invention and its problems]

As semiconductor devices become more highly integrated, the chip size becomes larger and wiring such as AFI becomes longer and thinner. For this reason, the inductance of wiring tends to increase, and the resulting power supply noise has become a problem that cannot be ignored.

In particular, MOS dynamic RAM (dR
In AM), there is a big problem because the integration is significant. In addition, in the case of dRAM, the design rule is 0.7 to 0.
．． With the miniaturization of the 51zm element, the power supply voltage Voc
It is unavoidable to lower the voltage from the conventional 5V to, for example, about 3.3V. Then, in order to keep the access time at the same level as the conventional dRAM, the peak current increases accordingly. As a result, the current fluctuation dl/dt in the wiring increases.

The above problem will be specifically explained by taking the precharge operation of a 1M bit dRAM as an example. During the dRAM precharge period, bit lines, address buffers, decoders, peripheral clock generators, etc. are precharged, but the bit line precharge consumes the most current. Assume that 128 memory cells are connected to one bit line and that the chip uses a divided operation type.

The divided operation type is a method in which the memory array area of a chip is divided into multiple parts in order to reduce peak current and current consumption during access, and only the selected memory array area is operated when active. For example, in a chip with a four-array configuration, two array areas are selectively brought into operation. In this case, the number of bit lines charged during precharging is 2048. The capacitance of one bit line is approximately 500fF, and 5Q up to power supply voltage Vcc = 5V
Assuming that charging is performed in ns, the average current Il at that time is s = (2048x500 x 10-1' F x5
V) 150ns=102.4 (mA). This is the average current, the peak current is 200
mA or more and reaches its peak current in a short time of 10 ns, the current change di/dt is d r/d t −200 mA/1010 n5 = 20 (
/s). Suppose that the source power supply voltage Vss (=OV
) is 1-30 n +-1, the rise in Vss potential is L @d I/d t=30nHx20MA/s=0.
It becomes 6V. In reality, in addition to the bit lines, address buffers, decoders, peripheral clock generators, etc. are charged depending on the season, as described above, so dl/dt becomes very large depending on the timing.

Next, during precharging (N/dt increases, Vss
Specific problems when noise occurs in wiring will be explained using FIG. 5. The specifications of the 1M pit t-d RAM include a hidden refresh mode, in which refresh can be performed while reading or writing is being performed. For example, as shown in FIG.
In this mode, by toggling RAS while reading "0" or "0", the address counter inside the chip is activated and chip refresh is performed. Naturally, bit lines are charged and discharged during this refresh cycle. The noise during bit line breakdown is not very large, but the noise during bit line charging is large, especially when the output level of data out 0out when reading 0" is set to the value V specified by the specifications.
There is a problem that o L =0.4v is exceeded.

Also, according to the specifications of 1M bit dRAM, when entering the precharge cycle, after starting up CAS, topp = 1
It is determined that the data out DOut is set to Hi-z after 0 ns has elapsed. As shown in Figure 6, RAS is
If you start up and precharge earlier than AS, in this case too, without setting tOFF, the output level of data out [)Ollt when reading 0°° will be VoL.
-0.4V will be exceeded.

In order to solve this problem, a method has been considered in the past in which precharging of each part is performed in a distributed manner.

However, sufficient improvement has not yet been made regarding bit line precharging, which has a particularly large di/dt and has a large influence.

[Purpose of the invention]

The present invention is based on the above points, and provides a semiconductor memory device that can reduce dl/dt during bit line precharging, suppress power supply noise, and increase the margin of circuit operation. The purpose is to

[Summary of the invention]

The present invention first short-circuits the bit line pair to be charged at the time of BRITCH II and sets it to the (1, /2) Voc level, then precharges the gate of the bit line precharge MOSFET to the power supply voltage Voo, Further, a bit line precharge circuit is configured to sequentially boost the voltage of the gate of the precharge MOSFET to Vcc+α and Vco+β (where α<β). That is, the pin I/line precharge circuit included in the present invention has an M
A second clock that drives the gate of the OSFET with the first clock output from the first clock generator and generates a second clock that is delayed by a predetermined time from the first clock.
MOSFE for bit line precharging by generator
At least two boost circuits for precharging the gate of T to Vco and subsequently boosting the gate of the precharging MOS FET are connected to a third. A third clock generating a fourth clock. It is configured to be sequentially driven by a fourth clock generator.

〔Effect of the invention〕

According to the present invention, the paired bit lines are first short-circuited (1
/2) After setting Voc, precharge MOSFE
By increasing the voltage of the gate of T in stages, di/dt during bit line precharging can be effectively reduced. Therefore, according to the present invention, when reading data out at hidden refresh or when CAS is started earlier than RAS to perform precharging,
It is possible to suppress the rise of out and easily meet the specifications of 1M bit dRAM and the like. Further, according to the present invention,
Noise generated in the wiring of the train power supply as well as the source power supply is suppressed, and the dRAM circuit operating margin is improved.

[Embodiments of the invention]

The present invention will be explained in detail below.

FIG. 1 shows a schematic configuration of a dRAM according to an embodiment. 1. The memory array consists of a capacitor and a MOS on a semiconductor substrate using a well-known method.
It is constructed by arranging memory cells consisting of FETs in a matrix. In this example the memory array consists of two blocks MA1. This shows the case where it is divided into MA2. Wl,,r,...

WLn is a word line for selectively driving memory cells, and B
Ll, BLt, B1-1', Bl-t',...
・ is a bit line that exchanges information charges with memory cells. SA is a sense amplifier, RDt and RD2 are low
It is a decoder.

FIG. 2 shows a schematic configuration of the bit line precharge circuit section. A pair of 1-bit lines (BLs and IILl).

N4 is connected between Bl2 and B L2 , -, B l-n and BLn) to short-circuit these bit lines.
0SFETTI is connected. MO for these short circuits
The gates of the SFETTs are driven by a first clock generated by a first clock generator CGA. Further, each bit line is provided with bit line precharging MOSFETs T2 and T3 whose drains are connected to Vcc. The gate nodes N of these precharge MOSFETs T2 and T3 are charged to Vcc by a second clock generated from a second clock generator CGe with a predetermined time delay after the first clock. ing. Bit line precharge MOSFET-T2,
The gate red node N of T:l also has two booster circuits 1.
2 is provided. One booster circuit 1 is a MOS F
It is composed of ET-T4 c, Ts a, Ts c and a boosting capacitor C101C2C. This booster circuit 1 is driven by a third clock generator CGo which generates a third clock delayed by a predetermined time from the second clock. Another booster circuit 2 is a MOSFE
T-T4 o, Ts o.

It is composed of T0n and boosting capacitors CID and C2H. This booster circuit 2 is driven by a fourth clock generator COD that generates a fourth clock that is further delayed by a predetermined time from the third clock.

Here, the two back pressure circuits 1.2 and MOS for precharging
FET-T2, Ts gate (... Capacitors Cic and Can for boosting the node N are set such that the capacitance ratio is, for example, 1 in the front groove and 4 in the rear right. J: The bootstrap ratio of the booster circuit 1 driven first is set to, for example, 0.15, while that of the booster circuit 2 driven later is set to 0.6.

The precharge operation in the bit line precharge circuit configured as described above will be explained. When entering the precharge period, the first clock generator CGA first
A clock is generated, which causes the shorting MOSFET
-Tt is turned on, forming multiple pairs of bit lines RL1. Bl
-, B10°8L2, and so on are all short-circuited.

When active, each bit line pair, one of which was at V c c s and the other at Vss, is now all (1/2) Vc
It is set to c level. After this, for example, after 4 nsec has elapsed, a second clock is generated from the second clock generator CG e, and the precharge MO8FET-
The gate nodes N of T2 and T3 are precharged to Vcc. This starts precharging each bit line. At this time, precharge MOSFET-T2
, T3 are conductive in the pentode operating region, so the charging speed is not so fast. Next, for example, after 4 nsec has elapsed, the third clock generator CG on one booster circuit 1 side
A third clock is generated from c. Boosting capacitor CIC Niha LTVc via MOSFET-Ts o
The capacitor C20 is charged to Vcc by the MOSFET-Tr, o driven by the second clock. Therefore, by the third clock, MO
The gate of SFET-T4C is boosted to a voltage higher than Voo and becomes conductive, and precharge MO3FET-T2, T
The gate node N of No. 3 is boosted to Vca+α. As a result, MO8FET-, T2T for precharging
3 enters the triode operation region, and precharging of the bit line is accelerated. However, at this time, the bootstrap ratio of the capacitor C1c and the precharging MOSFETs T2 and T3 is approximately 0.1, and the boost level α of the gate node N is equal to the threshold of the precharging MOSFETs T2 and T3. vthPi! However, the charging of the bit line is still not that fast. After this, for example, after 4 nsea has elapsed, the fourth clock generator CGn on the other booster circuit 2 side generates the fourth clock. As a result, similar to the operation of back pressure circuit 1, the precharge MOS
FET-T2, T3 gate node N to Vco+β
Pressure increases to In this booster circuit 2, the bootstrap ratio is large, so β is large, and the gate node N is Vcc
The voltage is boosted to about 1.5 times. In this way, each bit line is precharged stepwise and charged to the Vcc level.

FIG. 3 shows a circuit configuration that is a more specific version of the circuit shown in FIG. In Figure 3, the pin 1-line precharge MOS
The gate node N of the FET is set to Vc.

a second clock generator CGB for charging the
and the booster circuit 1.2 are shown in detail. Other first. The third and fourth clock generators are ψ-order lock generators CGx, CG2,
It consists of a circuit in which... are connected in cascade in multiple stages.

The first stage clock generator CG1 corresponds to the first clock generator CG8 in FIG. 2, and the seventh stage clock generator CG7 corresponds to the third clock generator CG8.
Corresponds to generator CGc, and the ninth stage clock generator CG e is the fourth clock generator CG.
Corresponds to I). By selecting the output stage of the unit clock generators connected in multiple stages in this way, the delay time between locks can be set as required.

The second clock generator CGa is driven by the output clock of the third stage clock generator CG1. Since the configuration of the clock generator is well known, detailed explanation will be omitted.

The correspondence between FIG. 3 and FIG. 2 for the booster circuit 1.2 will be explained as follows. Capacitors M3 and M4 of booster circuit 1 in FIG. 3 correspond to capacitors CIC and C20 of booster circuit 1 in FIG. 2, respectively. Similarly, in the booster circuit 2, 4. Yapasita M6.

M7 corresponds to capacitors CID and C2D, respectively.

In addition, MOSFET-Q:13 of the booster circuit 1 in FIG.
Q: l 2 and Qst are MOSFET-T4 C, Tii c and Tsc of booster circuit 1 in FIG. 2, respectively.
corresponds to Similarly, in booster circuit 2, MOSFET-Q
4 a, Q42OJ, and Q41 are each MOSFE
T-T4 D , corresponding to Ts o and Tsn.

The operation of the bridge circuit configured in this manner will be described next. FIG. 4 shows the time chart. Before entering the precharge period,
2 is 'I+' level. During this time, MOSFET-
Capacitor M3 through Os 2 and Q42 respectively
Nodes J and M6 are precharged to Vcc. Also, the nodes of capacitors M4 and M7, that is, MOS
The gates of FET-Q39 and Q43 are MO
SFET-Qs4, Qs6 and Q44. Q45
niJ: short-circuited. Clocks φP1 and φp2
When the output clock φ1 (first clock) of the first-stage clock generator CG1 is generated, the short-circuit M of the bit line pair is generated as described above.
OSFET is driven.

When the output clock φ of the third stage clock generator CG3 rises, it drives the second clock generator CGe, and its output stage MO8FE is driven.
Bit line precharge MOSFE via T-020
Clock φ that charges the gate node N of T to Vcc
B (second clock) rises. At this time, in the booster circuit 1.2, MOSFET-Q3 s,
Q4t is turned on and capacitors M4 and M7 are charged. When the output clock φ7 (third clock) of the seventh stage clock generator CG7 rises,
On one side of the booster circuit 1, the drain and gate of MOSFET-033 are boosted to above Vcc via capacitors M3' and M4, and as a result, the level of clock ψB slightly exceeds Vcc via this MOS FET-033. Top 4. The ninth clock generator CG in history 9
When the output signal [ ] φ9 (fourth clock) rises, the capacitor Ms,
The drain and gate of MOSFET-043 are boosted through M7, and the level of clock φB is increased to a sufficiently high level through MOSFET-043.

As described above, according to this embodiment, as is clear from FIG. By stepping up the clock φB applied to the gate node N of the charging MO8FET in a stepwise manner, the bit line BL, l''31- is precharged in a stepwise manner.

Therefore, (N/dt at the time of bit line precharging becomes small, and the operating margin of dRAM can be greatly improved.

The present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the spirit thereof.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a schematic configuration of a dRAM according to an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of its bit line precharge circuit section, and FIG. 3 is a diagram showing the bit line precharge circuit section in more detail. FIG. 4 is a time chart for explaining its operation, and FIGS. 5 and 6 are waveform diagrams for explaining conventional problems. MAl, MA2...Memory array block, BL,
B1. ,...Bit line, WL...Word line, CG
A...first clock generator, CGB...
Second clock generator, CG c...Third clock generator, CG o...Fourth clock generator/generator, T1...M for short circuit
OSFET, T2, T3... MOSFET for bit line precharge, 1.2... Boost circuit.

Claims (2)

[Claims] (1) A memory array in which a plurality of memory cells each having at least a capacitor for accumulating information charges are arranged in a matrix on a semiconductor substrate, a plurality of word lines for selectively driving the memory cells, and a selected memory cell. In a semiconductor memory device in which a plurality of bit lines and a plurality of bit lines for exchanging information charges are integrated, a bit line precharge circuit has a first MOSFET gate that drives a MOSFET gate to short-circuit a pair of bit lines. A first clock generator that generates a clock, and an M for precharging each bit line.
a second clock generator that generates a second clock delayed by a predetermined time from the first clock that precharges the gate of the OSFET to the power supply voltage; and a second clock generator that generates a second clock that is delayed by a predetermined time from the first clock, and boosts the gate of each of the precharge MOSFETs above the power supply voltage. and third and fourth clock generators that sequentially generate third and fourth clocks delayed from the second clock, which sequentially drive at least two booster circuits for the purpose of Storage device. (2) The first to fourth clock generators use a circuit in which unit clock generators are connected in multi-stage cascade, and the delay time between each clock is set to a predetermined value by selecting the output stage thereof. A semiconductor memory device according to claim 1.