JPS628354A - Reproducing device - Google Patents

Abstract

PURPOSE:To control the relative speed between a tape and a head always at a constant value by measuring the period of a pulse signal proportional to the drive speed of a drum motor so as to decide acceleration or deceleration and to pass the relative speed through a setting value thereby bringing the mode to a drum servo using a recovery clock. CONSTITUTION:When a recording medium being at a constant feeding speed is brought into a high speed feeding, the drive speed of a drum is detected (27) by using a pulse signal proportional to the drive of a drum motor 36 to decide (28) acceleration or deceleration information, the information is fed to a drum drive circuit 34 thereby activating the servo making the relative speed constant when the relative speed reaches a setting value. Since no reproducing data is utilized, the servo is locked to a set relative speed without being affected by dropout or the like.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Field of industrial application B. Overview of the invention C. Prior art D. Problem to be solved by the invention E. Means for solving the problem (Fig. 1) F. Effect G. Circuit configuration of Example 01 (Fig. 1) G2 high-speed operation (Figures 2 and 3) Operation before synchronization of G3 playback data and clock (Figure 4) Operation after synchronization of G4 playback data and clock (Figures 5 to 7) G5 main circuit Example of configuration (Fig. 8) G6 main circuit operation (Fig. 9) Effect of the H invention A Industrial field of application This invention is suitable for use in cases where the relative speed of a tape and a head is controlled at a constant level. Regarding equipment.

B. Summary of the Invention The present invention provides a playback device that controls the relative speed of a tape and a head at a constant rate, detects the rotational speed of a drum, determines drum motor acceleration or deceleration information, and supplies this information to a drum drive circuit. By operating a servo that keeps the relative speed constant when the relative speed reaches a certain set value, the relative speed between the tape and the head can be controlled at a constant level without being affected by dropouts or the like.

C. Conventional technology Conventionally, in order to control the relative speed between the tape and the head, when the relative speed between the tape and the head is largely ahead of a certain set value, that is, when the playback data and the playback clock are not synchronized. The servo is applied by comparing the time width of a specific pattern included in the reproduced data, such as a 4T pattern, with a reference value, and the relative speed is pulled into a range in which the reproduced data and the reproduced clock are synchronized (
Patent Application No. 59-232077, etc.).

D Problems to be Solved by the Invention However, in the case of the conventional method as described above, since the reproduced data is essentially used to apply the servo, there is a drawback that it is susceptible to data loss such as dropout. Ta.

The present invention addresses these points and provides a playback device that can always draw the servo to a certain set relative speed without being affected by dropouts or the like.

E. Means for Solving the Problems The reproducing apparatus according to the present invention detects the rotational speed of the drum using a pulse signal related to the rotation of the drum motor (36) when the recording medium is fed at high speed as opposed to constant speed feeding. (2
7) Determine the acceleration or deceleration information of the drum motor (2B) L. This information is supplied to the drum drive circuit (34), and when the relative speed reaches a certain set value, the servo is activated to keep the relative speed constant. It is configured to work.

F Action The recording medium is fed at high speed compared to constant speed feeding. At this time, the rotational speed of the drum is detected by the period detection circuit (27) using a pulse signal (FG pulse) related to the rotation of the drum motor (36).The drum motor is then accelerated based on the detected rotational speed. The drum acceleration or deceleration determining means (28) determines whether the drum is accelerated or decelerated. This information is then supplied to the drum drive circuit included in the drum servo circuit (34) to drive the drum motor, and when the relative speed reaches a certain set value, a servo is activated to keep the relative speed constant. As a result, playback data is not used, so
The servo can always be pulled to a set relative speed without being affected by dropouts or the like.

G. Example Hereinafter, an example of the present invention will be described in detail with reference to FIGS. 1 to 9.

G1 circuit configuration Figure 1 shows the circuit configuration of this embodiment.
), where the analog signal is converted into a digital signal and then supplied to the recording signal generation circuit (5) via the contact a side of the switch circuit (4).

It is also possible to directly supply the digital signal from the terminal (6) to the recording signal generation circuit (5) by switching the switch circuit (4) to the contact side.

The recording signal generating circuit (5) performs signal processing such as adding an error correction code to the data, interleaving, or modulating the data based on the timing signal from the timing generating circuit (7). 8). This switch circuit (8) is connected to the rotating magnetic head (IIA).
), (IJ, B), and the half-rotation period including the tape contact period of the head (IIA) and the tape contact period of the head (IIB) are controlled by the switching signal from the timing signal generation circuit (7). It is switched alternately with a half-rotation period including a contact period. This timing generation circuit (7) generates a rotary head (IIA), (
11B) is supplied with a pulse of 3011z indicating the rotational phase of
) is also supplied (FC pulse). The signal from the switch circuit (8) switched by the switching signal from the timing generation circuit (7) is sent to the amplifier (9A),
(9B), each switch circuit (IO
A), (IOB) are supplied to the rotating heads (IIA"), (IIB) via the contact R side,
It is recorded on a magnetic tape (14) wound between reels (12) and (13). The switch circuits (IOA) and (IOB) are connected to the contact R side during recording, and are switched to the contact P side during playback.

In addition, (15A) and (15B) indicate the corresponding rotating heads (11^) and (IIB) when the playback switch circuits (IOA) and (IOB) are switched to the contact P side.
), and each output of these amplifiers (i5A) and (15B) is supplied to a switch circuit (16). Switch circuit (1
6) is a half-rotation period including the tape contact period of the head (IIA) and a head (IIB) similar to the recording time by a 30Hz switching signal from the timing signal generation circuit (7).
It is switched alternately with a half-rotation period including a tape contact period.

Then, the output signal switched by the switch circuit (16) is sent to the equalizer (17), comparator (18) and PLL1.
is supplied to the error correction circuit (20) through the line (19);
Errors are detected here, and error correction is performed as necessary. The signal is further supplied to a digital-to-analog converter (21), where the digital signal is converted into an analog signal, and then passed through a low-pass filter (22) and taken out as an original analog signal at an output terminal (23).

Furthermore, if it is desired to directly extract digital data, it can be derived from the output terminal (24) of the error correction circuit (20).

Additionally, a drum motor (36) is connected to the frequency generator (25).
) is generated, and an FC pulse proportional to the rotation speed is generated.
For example, the frequency is 2000 rpm when the rotation speed of the drum is 2000 rpm.
+ is 800Hz, and 4000rpm is 1600Hz.

The FG pulses from the frequency sporadic machine (25) are supplied to a period detection circuit (27), which detects the rotational speed of the drum by counting the period of the FC pulses with an appropriate lock. The rotational speed information from the period detection circuit (27) is supplied to drum acceleration or deceleration determining means (28), which determines the acceleration or deceleration information.

The determining means (28) includes a decoder (29) that decodes the first speed or lower, and a decoder (29) that decodes the second speed or lower.
30) and a decoder (31) that decodes the third speed and below.
), and these decoders (29), (30) and (
and a determination circuit (32) that determines acceleration or deceleration information based on the output from 31).
A mode switching signal for switching between a fast forward (FF) mode and a rewind (REW) mode is supplied from a terminal (33).

The output signal from the determination circuit (32) is supplied as acceleration or deceleration information to the drum drive circuit (not shown) of the drum servo circuit (34), and the drum servo circuit (34) causes the output signal to be output via the switch (35). rotating head (IIA)
) and (11B) to control a drum motor (36) that rotates a drum (not shown) to which it is attached.

Further, a frequency divider (37) is provided, whereby the reproduced clock generated from the reproduced data in the PLL circuit (19) is divided by a predetermined ratio.The output of the 0 frequency divider (37) is connected to the switch ( 38) to a frequency-voltage (F/V) conversion circuit (39), where the frequency signal is converted into a voltage signal. The switch (38) is the error correction circuit (20)
It is controlled by the error check output (FIG. 5B) generated by the circuit, and is turned on when it is at a high level, for example. The voltage signal from the conversion circuit (39) is supplied to one input side of the comparator (40) and compared with the reference voltage supplied from the reference voltage generation circuit (41) to the other input side. The comparison error signal from the comparator (40) is supplied as relative speed information to the drum servo circuit (42), and the drum servo circuit (42) controls the motor (36) via the switch circuit (35). Make it. In other words, there are two systems: a servo system using the drum servo circuit (34), etc., and a servo system using the drum servo circuit (42), etc.
These are appropriately switched depending on the relative speed, as will be described later.

A switching means (43) is provided to switch the switch circuit (35) provided on the output side of the drum servo circuits (34) and (42). This switching means (43) generates, for example, a low level signal and switches the switch circuit (35) into contact when the relative speed is much higher than the set value, that is, when the reproduced data and the reproduced clock are not synchronized. When the relative speed approaches the set value, that is, when the reproduced data and the reproduced clock are synchronized, a high level signal is generated and the switch circuit (35) is connected to the side A. Like switching (.

As an example of this switching means (43), for example, the counter (4
4), NAND circuit (45), inverter (46) and D
a circuit consisting of a type flip-flop circuit (47);
A signal (
switching pulse). The counter (44) is reset in synchronization with, for example, the fall of this signal, and the flip-flop circuit (47) latches the manual data. Also, the output terminal Q of the counter (44)
Each output of A and QB is supplied to each input terminal of a NAND circuit (45), and the output of the NAND circuit (45) is connected to an inverter (46).
The signal is supplied to the input terminal of the flip-flop circuit (47) via the input terminal and also to the enable terminal E of the counter (44). For example, when the signal supplied to the enable terminal E of the counter (44) is at a high level, a counting operation is performed, but when it is at a low level, a counting operation is started. The output of the output terminal Q of the flip-flop circuit (47) is then supplied to the switch circuit (35) as a switching signal.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to FIGS. 2 to 7.

G2 high-speed operation Now, when the mode of the playback device is fast forward mode or rewind mode, the trajectories of the heads (11^) and (IIB) become trajectories as shown by A and B in FIG. 2, respectively. In the figure, the broken line shows the head trajectory during fast forwarding, the solid line shows the head trajectory during rewinding, and H indicates the head (IIA).
(IIB) represents the rotation direction, and T represents the running direction of the tape (14). At this time, the head (IIA), (
As for the output of IIB), an output is obtained from the track where the 7 azimuths match, and no output is obtained from the track where the azimuth does not match, so as shown in FIG. 3, a signal with a waveform similar to a so-called solo bread ball is obtained. This signal is equalized (1
7).

By passing through the comparator (18), a rectangular wave signal is obtained at its output side. The period of this rectangular wave signal changes depending on the magnitude of the relative velocity. Therefore, as will be described later, by detecting the relative speed corresponding to the signal from the comparator (18) and applying servo to the drum motor (35) via the drum servo circuit (42) etc., depending on the magnitude of the relative speed. It is understood that the relative speed can be controlled constant.

G3 Operation before synchronization of reproduced data and clock Next, the operation when the relative speed is much higher than a certain set value, that is, when the reproduced data and the reproduced clock are not synchronized, will be explained. Now, the relative speed vR during fast forwarding and rewinding is calculated from the following equation.

#VD - nV7 decoction θ.

In the above formula, Vo is the rotational speed of the drum,
θ0 is the still angle, n is the tape double speed value, and vT is the tape speed at 1x speed. For example, vR=3.13349
(va/s), θo −6,36667(de
g), VT -8,15 (w/s), the relationship between the tape speed value n and the drum rotational speed VD is expressed as shown in FIG.

From FIG. 4, the rotation speed of the drum is 3283.96 rpm when n = 250, and 705.7 rpm when n = -250. Therefore, in order to draw the relative speed to a certain constant value when feeding the carpet, the drum rotation speed may be changed within the range of 2000 to 3284 rpm when n≦250. Further, in order to draw the relative speed to a certain constant value during rewinding, when n≧−250, the drum rotation speed may be changed within the range of 705 to 2000 rpm.

Therefore, in the period detection circuit (27), the drum rotation speed is detected by counting the FC pulses from the frequency generator (25), and this drum rotation speed information is decoded (29
) to (31) for decoding. For example, if the first speed in the decoder (29) is 705 rpm, the decoder (
Assuming that the second speed in the decoder (30) is 2000 rpm and the third speed in the decoder (31) is 3284 rpm, when the rotation is faster than 3284 rpm during fast forwarding, the output DO1 of the decoder (31) is "0".
30) output DO2 becomes “0” and 3284 rpm≧
□When π is rotating at V o > 200Orpm+, D01 becomes "1", Dot becomes "1-O", and 2
When rotating at 000 rpm≧□Vo, D O1π becomes rlJ and DO2 becomes “1”. Also, when rewinding, if the rotation is faster than 200 rpm, D 02
is "O", and when the output DO3 of the decoder (29) is rotating, D02 is rlJ, and Dol is π, DO2 is "l" and Do3 is "1".

These results are supplied to a decision circuit (32).

In response to a mode switching signal supplied from a terminal (33), the determination circuit (32) selects Dot in the fast forward mode.

D Deceleration when both O2 is rOJ, Dol is “IJID”
When O2 is "0", the previous state is maintained, Dol.

It is decided to accelerate when both D 02 are r I J, and in -10,000 rewind mode, DO2 and Dol are both r O
When J (7), deceleration, D O2 is "1", Do3 is "0"
”, retain the previous state, 002. Both Dol are “1”
Decide to accelerate when .

Based on this determination, the determination circuit (32) determines that when accelerating,
A signal of "1" is supplied to the drum servo circuit (34), and a signal of "0" for deceleration is supplied to the drum servo circuit (34), and the drum servo circuit (34) accelerates or decelerates the drum motor (36) in response to these signals. control.

During such an operation, the relative speed always passes a certain set value, and at this time the reproduced data is synchronized with the reproduced clock, so
At that point, the switch circuit (35) is switched to the contact side.

04% Operation after synchronization of raw data and clock The above is accelerated,
The servo system such as the drum servo circuit (34) that generates deceleration information will be explained next, and the servo system such as the drum servo circuit (42) that uses a reproduced clock will be explained next.

In the fast forward mode or the rewind mode, a solo bread ball-like RF waveform signal 31 as shown at 51 mA is obtained on the output side of the switch circuit (16) as described above. When this signal S1 passes through an equalizer (17) and a comparator (18), a rectangular wave signal (reproduced data) S3 as shown in FIG. 6A is obtained on the output side. This signal S
3 is supplied to the PLL circuit (19), and if the reproduced data is correct, a reproduced clock signal $4 synchronized with the reproduced data as shown in FIG. 6B is generated. It is determined whether the reproduced data is correct or not by generating an error check output signal S2 as shown in FIG. 5B in the error detection circuit (20). In other words, when the signal S2 is at a high level, the reproduced data is being reproduced. When this signal S2 is at a high level, the switch (,3
8) is closed, and the reproduced clock signal S5, shown enlarged in FIG. 7A, from the frequency divider (37) is supplied to the conversion circuit (39).

The conversion circuit (39) internally generates a sawtooth wave signal as shown by the solid line in FIG. It is sampled at the falling edge of the signal S6, and as a result, a signal Ss, which is converted from a frequency signal to a voltage signal, is derived from the output side of the conversion circuit (39) as shown by the broken line in FIG. 7B. The level of this signal S6 increases in proportion to the period of the signal S5. In other words, when the relative speed becomes faster, the period becomes shorter and the level of the signal S6 becomes smaller. Conversely, when the relative speed becomes slower, the period becomes longer and the level of the signal s6 becomes higher.

The voltage signal S6 from the conversion circuit (39) is sent to the comparator (40)
and is compared with a reference voltage from a reference voltage generation circuit (41). On the output side of the comparator (40), if the level of the signal S6 is greater than the level of the base $ signal, a positive comparison error signal is obtained, and conversely, if it is smaller, a negative comparison error signal is obtained. This comparison error signal is supplied to the drum servo circuit (42) as relative speed information.

Further, the counter (44) is reset in synchronization with the falling edge of the switching pulse, and sequentially counts the error check output signal S2 from the error correction circuit (20). During one cycle of the switching pulse, that is, the head CIA
), (IB), signal 8
When a predetermined number of 2's, for example 3, are counted, it is determined that the data is being reproduced correctly, and the counter (44) generates an output of [11] at the output terminals QA and QB. As a result, a low level signal is obtained on the output side of the NAND circuit (45), and this signal causes the counter (44) to stop counting. Further, the signal from the NAND circuit (45) is passed through the inverter (46) to the flip-flop circuit (47).
), and is latched at the falling edge of the next switch notching pulse. As a result, a high level signal is obtained at the output terminal Q of the flip-flop circuit (47), thereby switching the switch circuit (35) to the contact side.

Therefore, the output of the drum servo circuit (42) is
6), and the drum servo circuit (42) controls the motor (36) to accelerate when the comparison error signal is positive and to decelerate the motor (36) when it is negative. That is, the motor (36) is accelerated when the relative speed is lower than the set value, and decelerated when it is faster.

As a result, the relative speed between the rotary heads (18), (IB) and the tape (14) is controlled to be constant.

In this way, when the playback data is not synchronized with the playback clock and the relative speed deviates greatly from the set value, control is performed using a servo system such as the drum servo circuit (34) so that the playback data is synchronized with the playback clock. When the relative speed approaches the set value, control is performed using a servo thread such as the drum servo circuit (42), so that more precise and fine control of the relative speed is possible.

Note that in the above embodiment, the heads (IA) and (IB
) The reproduced data is determined to be correct when an error check output signal of 3 (ltll) is obtained during both scans of the head (IA).
, (IB) may be determined to be correct if an arbitrary number of error check output signals are obtained during one scan.

An example of the circuit configuration of the main part of G5 Fig. 8 shows an example of the specific circuit configuration of the period detection circuit (27) and the drum acceleration or deceleration determining means (28). In the figure, (50) is the frequency generator. (25)
(FIG. 1) is an input terminal to which the FG pulse from the input terminal (50) is applied, and the FG pulse from this input terminal (50) is supplied to an edge detection circuit (51) for detecting its edge, for example, a rising edge. Ru. A pulse signal from the edge detection circuit (51) is supplied to clear terminals CL of cascade-connected counters (52) and (53). The edge detection circuit (51) and counters (52) and (53) constitute a period detection circuit (27) (FIG. 1). Also,
The clock terminals of the counters (52) and (53) have terminals (5
4), a clock signal of a predetermined frequency, for example 10k)lz, is supplied.

The counter (52) has output terminals QA, Qs, Qc and QD, with weightings of 1, 2.4 and 8, respectively. In addition, the counter (53) also has output terminals QA+QB, Qc.
and QD with weightings of 16.32.64 and 12B, respectively. A carry terminal CA of the counter (52) is connected to an input terminal IN of the counter (53). The output terminal QC of the counter (52) is the decoder (29)
(FIG. 1) It is connected to one input end of a NAND circuit (55) corresponding to the decoder (30) (FIG. 1), and also connected to one input end of a NAND circuit (56) corresponding to the decoder (30) (FIG. 1). Further, the output terminal QO of the counter (52) is connected to the other input terminal of the NAND circuit (56), and an inverter (57) corresponding to the decoder (31) (Fig. 1)
connected to the input end of the Further, the output terminal QB of the counter (53) is connected to the other input terminal of the NAND circuit (55).

A NAND circuit (55) corresponding to a decoder (29) that decodes 705 rpa+ or less is a counter (52),
When (53) counts approximately 36 clocks from terminal (54) in one cycle of the FC pulse, it opens the gate and
A NAND circuit (56) corresponding to a decoder (30) that decodes 00 rpm or less has a counter (52) connected to a terminal (5).
When the clock from 4) is counted approximately 12 times in one cycle of the FC pulse, the gate is opened and the inverter (57) corresponding to the decoder (31) that decodes 3284 rpm or less.
) is designed to obtain an inverted output when the counter (52) counts the clock from the terminal (54) to about 8 (11) in one cycle of the FC pulse.

NAND circuits (55), (56) and inverters (
The output side of 57) is an R-3 type flip-flop circuit (58
).

(59) and (60) are respectively connected to the set terminals S, and each output terminal Q of the flip-flop circuit (5B), (59) and (60) is connected to the D-type flip-flop circuit (
61), (62) and (63), respectively. The output side of the edge detection circuit (51) is connected to the reset terminal R of the flip-flop circuits (58) to (60), and is also connected to the clock terminal of the flip-flop circuits (61) to (63) via the inverter (64). connected to.

The output side of the flip-flop circuit (6I) is an inverter (
R-3 type flip-flop circuit (66) through
is connected to the set terminal S of the flip-flop circuit (6
The output side of 2) is connected to the reset terminal R of the flip-flop circuit (66) and also connected to the set terminal S of the R-3 type flip-flop circuit (68) via the inverter (67). The output side of 63) is connected to the reset terminal R of the flip-flop circuit (68). Flip-flop times W (66) and (68)
The output sides of are connected to the input terminals of AND circuits (69) and (70), respectively, and the terminal (71) to which the mode switching signal is applied to the other input terminal of the AND circuit (69) is connected to the inverter ( 72) and the AND circuit (70)
A terminal (71) is directly connected to the other input end of the terminal.

The output terminals of the AND circuits (69) and (70) are connected to the input terminals of the OR circuit (73), and the output terminal (74) is taken out from the output terminal of the OR circuit (73).
This output terminal (74) is connected to the input side of the drum servo circuit (34) (FIG. 1). In addition, (58) to (73
) constitutes a judgment circuit (32) (Fig. 1).

G6 Main Part Circuit Operation Next, the operation of this circuit will be explained with reference to the signal waveforms shown in FIG. Now, from the terminal (50), F as shown in FIG. 9A is connected.
When the G pulse is supplied to the edge detection circuit (51), its rising edge is detected and the ninth
A pulse signal as shown in Figure B is obtained. The counters (52) and (53) are cleared by supplying this pulse signal to the clear terminals CL of the counters (52) and (53). From this point on, the counter (52)
, (53) counts the clock from the terminal (54). As a result, the count value corresponding to the length of one cycle of the FC pulse is displayed in the counters (52) and (53).
More can be obtained. That is, the rotational speed of the drum at the time of Renhui is detected.

When the rotation speed of the drum is 705 rpm or less, an output of "0" is obtained on the output side of the NAND circuit (55), and 2000 rpm is obtained.
If the rpm is below, the output side of the NAND circuit (56) will say “
If the output is 3284 rpa+ or less, a signal of 1-0 is obtained at the output side of the inverter (57) (FIG. 4C). AND circuit (55), (56)
When the output of the inverter (57) becomes IOJ, the output side of the flip-flop circuits (58) to (60) becomes “1”.
” signals are obtained (Fig. 4D). And this “
1'' signal is applied to the flip-flop circuit (61) at the time when the pulse signal from the edge detection circuit (51) is inverted by the inverter (64) and applied to the clock terminals of the flip-flop circuits (61) to (63). - (63), and the outputs of the flip-flop circuits (61) - (63) become "1" (Fig. 4E). In addition, R-3 at this time
The rational value table of type flip-flop circuits (58) to (60) is as shown in the following @1 table.

In Table 1, the outputs D O3' to D Ot' of the flip-flop circuits (61) to (63) are determined by the rotational speed of the drum and each 1
-The following changes occur depending on the mode (fast forward/rewind). In other words, in the fast forward mode, the rotational speed of the drum is 3284r
pm, the output D01' of the flip-flop circuit (63) and the output D of the flip-flop circuit (62)
02' are both "1", 2000-3284 rpm
In the range of , the output D Ot' is 10'', the output D O2
' is rlJ, and if the speed is below 2000 rpm, the output D
O1' and D02' are both 1-0. On the other hand, in the rewind mode, if the rotational speed of the drum is faster than 200 rpm, the output DO2 of the flip-flop circuit (62)
' and output D 03' of the flip-flop circuit (61)
are both "1", and in the range of 705 to 2000 rpm+m, the output D 02' is "0" and the output D 03' is "
1'', and when the speed is 705 rpm or less, both outputs D02' and DO3' become rOJ.

When these are arranged, it becomes as shown in Table 2 below.

The output of the flip-flop circuit (61) in Table 2 is connected to the inverter (6
The output of the flip-flop circuit (62) is supplied to the reset terminal R of the flip-flop circuit (66) through the inverter (67). 79717
The output of the flip-flop circuit (63) is supplied to the reset terminal R of the flip-flop circuit (68). The flip-flop circuits (66) and (68) operate according to the concrete value table shown in Table 1 above. However, in this case, there is no operation in which both the set terminal S and reset terminal of the flip-flop circuits (66) and (68) are "0" and the output terminal Q is "0".

Also, in fast forward mode, a high level “
1” signal is supplied, and in rewind mode, the low level “
0'' signal is supplied. Therefore, in the fast forward mode, the gate of the AND circuit (70) opens and the output of the flip-flop circuit (68) is passed through the OR circuit (73) to the output terminal (
74).

In other words, the output terminal (74) has a flip-flop circuit (
When the output of the output terminal Q of 68) is "1", acceleration information is obtained; when the output is "0", deceleration information is obtained;
When set to "Unchanged", the previous state is retained. In addition, in rewind mode, and times V! The gate of F (69) opens and the output of the flip-flop (66) is taken out to the output terminal (74) via the OR circuit (73). In other words, the output terminal (
74) is the output terminal Q of the flip-flop circuit (66).
When the output is "11", acceleration information is obtained, and the output is "α"
When , deceleration information is obtained, and when the output is "unchanged", the previous state is maintained.

H Effects of the Invention As described above, according to the present invention, the period of the FG pulse proportional to the rotational speed of the drum motor is measured, and from this period it is determined in which range the rotational speed of the drum at that time is, Determine acceleration or deceleration, and supply this acceleration or deceleration information to the drum drive circuit to change the rotational speed of the drum within a predetermined range, allowing the relative speed to pass a certain set value, and drive the drum servo using the regenerated clock. Therefore, the relative speed between the tape and the head can always be controlled at a constant level without being affected by dropouts or the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIGS. 2 to 7 are diagrams for explaining the operation of FIG. 1, and FIG.
The figure is a circuit diagram showing an example of a specific circuit configuration of the main part of the present invention, and FIG. 9 is a waveform diagram for explaining the operation of FIG. 8. (IIA) and (IIB) are rotating magnetic heads, (1
4) is a magnetic tape, (18) and (40) are comparators, (27) is a period detection circuit, (28) is drum acceleration or deceleration determining means, and (34) is a drum servo circuit. Figure 5

Claims (1)

[Claims] When the recording medium is fed at high speed compared to constant speed feeding, the rotational speed of the drum is detected by a pulse signal related to the rotation of the drum motor to determine acceleration or deceleration information of the drum motor. . A playback device characterized in that the information is supplied to a drum drive circuit so that when the relative speed reaches a certain set value, a servo is activated to keep the relative speed constant.