JPS6281182A - Nonlinear photoelectric converter - Google Patents

Abstract

PURPOSE:To convert an input optical signal of a wide dynamic range to a voltage signal with an excellent S/N by making the potential of the drain gate of a storage-type photoelectric conversion element a function of the time during an integrating period to compress said input signal of wide dynamic range. CONSTITUTION:The counting (n) of a counter 2 is inputted to the integrating residual time generating circuit 14 of a storing-control signal generating circuit 4 to generate the integrating residual time (t) of the charge-integration of the photoelectric conversion element 7. In a semiconductor memory 16 is the content y=f(t) of a data in an address (t) inputted beforehand. A function generating circuit 18 generates a binary signal f(t) to control the relative voltage of the drain gate of the storage-type photoelectric transducing element 7 by means of a function (f). A sample holding circuit 21 impresses a functional voltage Zs to an adding circuit 22, where it is added with a bias voltage Zo, and the resulting voltage Z is inputted to a buffer 6. A storing-control signal IG from the buffer 6 is impressed to the drain gate to drain excess charges to the drain. Consequently, the nonlinear storing of charges is executed.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention is directed to a storage type photoelectric conversion device such as a COD that converts an optical signal into an electrical signal, in which the gamma characteristic of an output electrical signal with respect to an input optical signal is reduced by γ. The present invention relates to a nonlinear photoelectric conversion device that can be set to.

[Prior art] Solid-state imaging devices such as COD use semiconductors, so they have advantages such as small size, light weight, low power consumption, and high reliability. Since the signals are read out sequentially, the graphical distortion is very small, so it has become widely used in recent years.

However, many devices have a gamma characteristic of γ = i, and while the gradation of the input image and output image are almost equal, and the nearness is good, the dynamic range is narrower than that of silver halide film, and it is difficult to use natural images or recorded images. It is difficult to obtain a video signal that can reproduce a high-definition image from high brightness to low brightness, and it has the disadvantage that dark areas tend to become black and bright areas become saturated. ing.

In addition, since the dynamic range that display devices can express is usually narrow, in order to reduce the burden of signal processing, it is necessary to convert the brightness level into a compressed signal for processing.
Even if processing such as γ conversion is performed at a later stage in OD, etc., no effective effect can be obtained due to the narrow dynamic range of the luminance information of the image signal obtained from a CCD, etc. Compression of image signals by γ conversion has the disadvantage that it cannot substantially handle optical images with a very wide dynamic range.

[Object of the Invention] An object of the present invention is to convert an optical image signal with a wide dynamic range into an electrical signal with a good S/N ratio by making the potential of the discharge gate of a storage type photoelectric conversion element a function of time during the integration period. , γ can be compressed by 1.

[Summary of the Invention] The gist of the present invention for achieving the above-mentioned object is to provide a photosensitive section that converts an optical signal into a charge signal, an accumulation section that accumulates charges generated in the photosensitive section, and a storage section that stores charges accumulated in the accumulation section. A discharge gate for discharging part or all of the charge to the drain; a shift gate for transferring the charge integrated in the storage section to the transfer section;
A storage type photoelectric conversion element consisting of a transfer section that transfers the charge transferred via the shift gate, a detection section that detects the charge transferred via the transfer section and converts it into a voltage signal, and a reference clock. A counting means for counting pulses to generate time information; a shift pulse given to the shift gate from the output of the counting means; a drive pulse given to the transfer section; a drive pulse for generating a reset pulse given to the detection section; By changing the potential of the discharge gate in relation to the generation circuit and the remaining integration time t until the end of the integration during the integration period of the charge in the storage section,
A nonlinear photoelectric conversion device characterized by comprising a charge accumulation control means for controlling a charge accumulation capacity of the accumulation section.

[Embodiments of the invention] The present invention will be explained in detail based on illustrated embodiments.

FIG. 1 is an overall configuration diagram, in which a counter 2 is connected to a clock generation circuit l that generates a reference clock pulse φ,
A driving pulse generating circuit 3 and an accumulation control signal generating circuit 4 are connected in parallel to the counter 2. The output of the drive pulse generation circuit 3 is connected in parallel to the storage type photoelectric conversion element 7 via the buffer 5, and the output of the storage control signal generation circuit 4 is connected to the storage type photoelectric conversion element 7 via the buffer 6.

The counter 2 divides the pulse φ to obtain time information from the reference clock pulse φ generated by the clock generation circuit 1, and outputs a signal n corresponding to the count to the drive pulse generation circuit 3 and the accumulation control signal generation circuit 4. ing. The drive pulse generation circuit 3 photoelectrically converts a drive pulse φ disk related to charge transfer to drive the photoelectric conversion element 7, a shift pulse SR related to charge transfer, and a reset pulse small R related to charge detection through a buffer 5. The signal is applied to the element 7 in correspondence with the signal n. The accumulation control signal generation circuit 4 receives the signal n and outputs an accumulation control voltage Z for controlling the discharge gate of the photoelectric conversion element 7 in response to the signal n.

The buffer 6 into which the accumulation control voltage Z is input buffers the accumulation control voltage Z and outputs it as an accumulation control signal IC to the photoelectric conversion element 7, thereby controlling the potential of the discharge gate of the photoelectric conversion element 7. It has become.

By controlling the potential of the discharge gate in this manner, the charge capacity that determines the maximum amount of charge that can be stored in the storage section of the photoelectric conversion element 7 is controlled.

FIG. 2 is a block diagram of the storage type photoelectric conversion element 7, in which four photosensitive sections 8 are arranged in parallel to convert an input optical signal into a charge signal.
Each of the photosensitive sections 8 is connected to an accumulation section 9 for temporarily storing charges generated in the photosensitive sections 8 . Although FIG. 2 shows an example of a 4-pixel photoelectric conversion element 7 consisting of four photosensitive sections 8 and four storage sections 9, the number of pixels may be selected as appropriate depending on the purpose. 9 is connected to a transfer section 11 via a shift gate 10, and the output of the transfer section 11 is connected to a detection section 12.

Further, each storage section 9 is connected to a drain 0FII via a drain gate 13.

Charges generated by the light irradiated onto the photosensitive section 8 are accumulated in a potential well of the accumulation section 9 . In the discharge gate 13 corresponding to the height of the wall of this potential well,
An accumulation control signal IG is inputted from the accumulation control signal generation circuit 4 via the buffer 6, and by controlling this control signal IC, the height of the potential of the discharge gate 13 is made variable, and the accumulation section 9 Controls the maximum amount of charge that can be stored in the The amount of charge that exceeds the height of the potential wall of the drain gate 13 is not accumulated in the storage section 9, but passes over the drain gate 13 and flows to the drain O having a voltage of Vdd.
It is designed to be discharged to FD. The shift gate 10 is then connected to the drive pulse generating circuit 3 via the buffer 5.
Due to the shift pulse SH input into the storage section 9, the charges accumulated in the storage section 9 are transferred to the transfer section l! via the shift gate 10. are transferred in parallel. Furthermore, the charge signal q is transferred to the charge detection section 12 in time series by the two-phase charge transfer pulses φ1 and φ2 inputted from the drive pulse generation circuit 3 to the transfer section 11 via the buffer 5, and is further transferred to the buffer 5. The charge signal q is converted into a voltage signal V by a reset pulse φR inputted from the drive pulse generation circuit 3 to the charge detection section 12 via.

FIG. 3 is a configuration diagram of the accumulation control signal generation circuit 4, and this circuit 4 has an integral remaining time generation circuit 14 and a sample clock generation circuit 15, each inputting the count n generated by the counter 2, as input terminals. There is. The output of the a-minute remaining time generation circuit 14 is sent to a function generation circuit 18 consisting of a semiconductor memory 16 and a D register 17 arranged in sequence, and a D/A
The output of this generation circuit 20 is connected to a sample hold circuit 21 and an addition circuit 22 in sequence, and the addition circuit 22 is connected to the output terminal of the accumulation control signal generation circuit 4. It has become. Further, the output of the sample clock generation circuit 15 is connected to the D register 17 and the sample hold circuit 21.

The integral remaining time generation circuit 14 inputs the count n generated by the counter 2 and generates the integral remaining time t of charge integration of the photoelectric conversion element 7. Data content Y=f(t) at address t is input to the semiconductor memory 16 consisting of RAM, ROM, EFROM, etc. here,
Both t and f(t) are numbers expressed in binary format. Then, the integration remaining time t is input to the 7-dress input terminal of the semiconductor memory 16, a binary signal is output from the data terminal, and the D register 17 is synchronized with the rise of the sample clock pulse φS input from the sample clock generation circuit 15. Then, a binary signal at the integration remaining time t is written.

In this way, the function generating circuit 18 generates a binary signal f(t) for controlling the relative voltage of the discharge gate 13 using the function f from the integration remaining time t.

Then, by converting the binary signal r(t) from a digital quantity y to an analog quantity functional voltage Zf by the D/A converter 19, the functional voltage generating circuit 20 generates a voltage of 1 when the integration remains.
A function voltage Zf, which is the relative magnitude of the voltage applied to the discharge gate 13, is generated corresponding to 17f t. This function voltage 21 is input to a sample and hold circuit 21, and the sample and hold circuit 21 inputs a sample clock pulse φS from the sample clock generation circuit 15. When this clock pulse φS is at a low level, it samples the function voltage Zf and outputs a clock signal. When the pulse φS is at a high level, the sampled signal voltage is held, and the sampled and held function voltage Zs is applied to the adder circuit 22. The adder circuit 22 adds the function voltage Zs and an appropriate bias voltage zO input from the outside, and outputs the voltage Z to the buffer 6.

In this way, the accumulation control signal generation circuit 4 generates the integration remaining time t from the count value n of the clock pulse φ generated by the counter 2, and performs the functional transformation of y = f(t) on this time t. . Then, applying the accumulation control signal IC from the buffer 6 to the discharge gate 13,
By discharging excess charge from the storage section 9 to the drain OFD, nonlinear charge storage is performed.

FIG. 4 shows a generating circuit 20' of another embodiment of the functional voltage generating circuit 20. In FIG. Similar to the function voltage generation circuit 20 described above, the function voltage Zf = f(t
), this function voltage generation circuit 20
° is for converting the function voltage Zf into seven voltage levels.

For simplicity, the case where the integral remaining time is 6 bits or less is shown, and t satisfies 0≦t and 63.

Here, tO to t5 is a signal of each bit of the integration remaining time t, and is either "1" or "0", and 2'' represents the power of 2.

Up to tl-t4, each is or game) 23b to 23e
The outputs of the OR game) 23b to 23e are connected to inverters 24b to 24e, AND gates 25b to 25e, analog gates 26b to 26e, and resistors T2 to t5, respectively. to is or game)23
a and an AND gate 25b, and the output of the OR gate 23a is sequentially connected to an inverter 24a, an analog gate 26a, and a resistor rl. t5 is the OR gate 23e, the inverter 24f, and the analog gate 26
The output of the inverter 24f is sequentially input to the analog gate 25f, the analog gate 26f, and the resistor r6.
The output of analog gate 28g is connected to resistor r7. Furthermore, tl is Antogame) 25c,
t2 goes to AND gate 25d, t3 goes to AND gate 2
5e and t4 are input to the ant game) 25f, and the output of the OR gate 23e is input to the OR gate 23d.
The output of the OR game) 23d is connected to the OR gate 23c, the output of the OR game) 23c is connected to the OR gate 23b, and the output of the OR gate 23b is connected to the OR gate 23a.

Further, the outputs of the analog gates 26a to 26g are connected to the input terminal of an operational amplifier 27, and the input terminal of the operational amplifier 27 to which these analog gates 26 are connected is connected to a constant voltage source of -Vl via a resistor Ro. is connected. The other input terminal of the operational amplifier 27 is grounded via the resistor Ra, and the output terminal of the operational amplifier 27 is connected to the resistors r1 to "
7 ends are connected. Here, as the resistors r1 to r6, resistors satisfying rk=rl/k (k=1 to 6) are arranged.

To explain the switch signals 5WI-SW7 input to the analog gates 26a to 26g, the analog gate 2
Switch signal SW input to 6g? Since only t5 is input, SW? =t5. Regarding the analog signal 26f, t4 and t5 via the inverter 24f are input via the AND gate 25f, so S6=t5-t4. However, t5" represents the negative value of t5. As the switch signal S%l15 input to the analog gate 26e, the negative input of t3, t5 and t4 via the OR gate 23e and the inverter 24e is the negative input of the AND gate 25e. sWs = (t5
+t4) ”φt3=t5 quintillion・t4 car-tO.

The switch signals S4 to SW2 are obtained in the same way, and for the switch signal SWI, to is or game) 23
a. Since it is input via the inverter 24a, SWI = t5" - t4' - tO"
−t2” −tl” −to” and 1=
When it is 0, grinning, tO~t5=Otonal(7)te, SWI
= t5 quintillion · t4" ・t3 quintillion ・t2 quintillion ・11 quintillion ・to" = 1, and the switch signals SW2 to SW
7 becomes O.

Also, when 1=1, t=Σtkken 2-k, so to=1, t1~tS=O, so SW2
= 1, and other switch signals S pull ±0.

When t=2, t1=1, to=o, t2-t5=0
Therefore, 5Il13 = 1, and the other switch signals SW become O. When t#3, t1=1, t
o=1.

Since t2 to t5 = 0, SW3 = 1, and other switch signals SW become 0, and in other cases, switch signals SWI to SW7 of 0 or more are obtained in the same way.
The logical formula and the value of t are as follows.

SW? =t5 (t≧32) SW8=t5 car ・t4 (t=ts~31)S
Ri 5= (t(5)◆ t(4)) car ・t3=t5
Military ・t4" tatami tO (k=8~15) S111
4 = (t(5)+t(a)+t(3))"
-t2=t5 car ・t4 quintillion ・t3 quintillion ・t2
(t=4~7) S 3 = (t5+ t4+ t3
φ t2) Wealth ・t1=t5 car ・t4yi ・t3
Car ・t2 quintillion ・tl (t=2.3) SW2 child (t5+ t4 age t3÷ t2◆ t
l) Kyo ・ tO=t5 family ・ t4" ・ t3 wealth ・ t2" @ tl book ・ 10 (t = 1) SWI = (t5+ ta+ t3◆ t2+
tl◆ to) car = t5 army - t4 car ・ t3 car
- t2 car - tl book - tol (1 = 0) In this way, tO to t5 take "1" or rOJ, so
Substituting this into the logical expression of switch signals 5Il11-SW7, SWI-SW? is "1" alternately depending on the value of t
Then, the switch signal Sν1~SW? One of them is always "1" and the others are "0". Now, if the switch signal SWk is "1", the resistor rk is selected, and the amplification factor of the operational amplifier 27 is -rk. /Ro. Therefore, Zr= (
rk/Ro) Vl is output.

FIG. 5 is a block diagram of the integration remaining time generation circuit 14 and the sample clock generation circuit 15 for generating the integration remaining time and the sample clock pulse φS from the count n which is the output of the counter 2. Here, when m is the number of bits of count n, count n can be expressed as follows, and t can be expressed as ra as described above.

The integral remaining time generation circuit 14 has counts n4 to n(m-1
) is input, but nlO~n(m-1) is input to the OR gate 28, and the OR gate 28 inputs nLO~n(m-1).
Compute the logical sum of each bit of n (layer-1), and calculate Xoma=n
Output lO+nll + * fistfight+n(m-1). Counts n4 to n9 are or game respectively) 29a to 29f
These or gates 29a to 29f
Since the Xo matrix is also input to each, the logical sum of each nk (k=4 to 9) and the Xo matrix is calculated and tO to t5 are output.

At this time, when the output Xo of the OR gate 28 becomes 1, the outputs of the OR gates 29a to 29f all become 1, and all tO to t5 also become 1. Therefore, nk2-10
When , any term greater than or equal to n10 is always 1, so tO~t5 becomes l, and t=1+2+22+...
+25, so t=26-1. When n<2''10, terms of n10 or more in the equation for n are O.

1(0) to n9 take either O or 1, to-t
5 is equal to the value from n4 to n8, and if n4-1, 10=1, if n5=1, tl=1, etc., so tk = n(k+4) (k = 0 to 5). Therefore, since t takes an integer value, t = [n/181
, where [ ] is a Gaussian symbol.

On the other hand, in the sample clock generation circuit 15, the count 13 is input to the trigger input terminal of the multi-by-break 30 to which the power supply voltage Vcc is input, and n3
When the trigger is activated at the rising edge of , a pulse of an appropriate width is output from the output terminal Q. At this time, since n3 rises repeatedly, the output sample clock pulse φ
S also becomes a continuous pulse.

FIG. 6 is a timing chart of each signal when the integration remaining time generation circuit 14 and the sample clock generation circuit 15 have the structure shown in FIG. FIG. 6(a) shows a timing chart when the circuit 20 shown in FIG. 3 is used as a function voltage generation circuit, and the circuit 2 shown in FIG.
A timing chart diagram when using 0' is shown in (b).

In FIG. 6(a), the sample clock generation circuit 15 inputting the count output n3 of the counter 2 outputs a clock pulse φS corresponding to n3, and the integration remaining time generation circuit 14 inputting the count output n4 of the counter 2 is to=n4
The integration remaining time t corresponding to the pulse signal is output. The function generating circuit 18, which receives the integration remaining time t, generates the function y from the D register 17 in synchronization with the sample clock pulse φS, so that y is output later than t. Then, this y is output as a function voltage Zt by the D/A converter 19, and is output as Zs in synchronization with the sample clock pulse φS in the sample hold circuit 21. When the function voltage generation circuit 20 is used in this way, Zs is output with a delay of one unit time with respect to t, so data is written in the semiconductor memory 16 of the function generation circuit 18 by shifting l addresses. good.

In the case of FIG. 6(b), the function voltage generation circuit 20' directly outputs the function voltage Zf from t, so the function voltage ZF is output corresponding to t, and Zs is synchronized with the sample clock pulse φS. The function voltage Zs is output with a slight deviation from the function voltage Zr.

FIGS. 7 to 9 show examples of the accumulation control signal IG applied to the discharge gate 13 obtained from Zg output at the above timing, and FIG. 7 shows a continuous logarithm FIGS. 8 and 9 show an accumulation control signal IG that provides an accumulation characteristic, and FIGS. 8 and 9 show an accumulation control signal IG that provides a logarithmic conversion characteristic approximated by a polygonal line. 1 during one cycle of accumulation cycle T
By using the function voltage generation circuit 20 shown in FIG. 3, the accumulation control signal IC within the period in which the pair of shift pulses SH is generated can generate various control intervals by setting the data in the semiconductor memory 16. can. The storage control signal IC shown in FIG. 7 is obtained by setting data as shown in the following equation for the address X of the semiconductor memory 16.

f(x)= a Hlog x+βl (l≦X≦xm
ax)=fO(x=O, xmax<x) Therefore, an optical signal with a brightness of
That is, when a charge whose amount of charge per unit time is a is generated and flows into the storage section 9, the integral remaining time t on the left side of the point P, which is the point of contact between the straight line with the slope a and the curve of the storage control signal IG, is When it is longer than ti, the rate of charge generation exceeds the increase in the potential of the discharge gate 13, so the excess amount flows into the drain OFD, and the storage section 9 is always filled with charges. After passing point P, the remaining integration time t is ti
When the charge generation rate a becomes smaller, the discharge gate 1
The rate of increase in the potential of No. 3 becomes faster, and the charges generated in the photosensitive section 8 do not overflow from the accumulation section 9, but are accumulated at a slope a. Then, the amount of charge read out by the shift pulse SH generated when 1=0 is g(
The amount corresponds to a), and g(a) is g(a) = az
lag a+β2.

Figure 8 shows the accumulation control signal shown in Figure 7! Accumulation control signal rather than G! This is a case where the voltage level at which G can be taken is small, and f
O-f32 is the voltage of the accumulation control signal IG corresponding to each integration remaining time t. In this case, since the accumulation control signal IG has a step shape, the read charge amount g(a) is a polygonal line approximation of logarithmic compression of a. It goes without saying that the accumulation control signal 1G shown in FIG. 8 can be generated by the function voltage generation circuit 20, but it can also be easily generated by the function voltage generation circuit 20'.

FIG. 9 is a modification of the M product control signal IG shown in FIG. 8, and only when t=1.2.4.8.16.32, the voltages of the accumulation control signal IG are , f8. He
, f32, and the voltage is 0 at other times.The conversion characteristics of the output voltage g(a) with respect to the amount of charge a generated per unit time in this case are also similar to those shown in Fig. 8, and the accumulation in this case is The control signal IO can also be easily generated by the function voltage generation circuit 20'.

Figure 1θ shows how charges are accumulated in the accumulation section 9 in response to the accumulation control signal IC, where (a) shows the accumulation control signal IG in the conventional device, and (b) shows the situation in which the charges are accumulated in the accumulation unit 9 in response to the accumulation control signal IC. This is for the accumulation control signal rG. In (a), one pulse is output during one integration cycle T, and the amount of charge a generated per unit time is
For i, the output V is V=vi, and a and V have a linear relationship unless saturated. When no light enters the photosensitive section 8, aO becomes al.When a certain amount of light enters the photosensitive section 8, a2 receives twice as much light as al, and a4 receives four times as much light as al.

a8 is an integral line that shows the integration when 8 times as much light as al and ale as 16 times as much light as al are input to the photosensitive section 8, and in the case of (a), the saturation level SL is reached at a4. It turns out that it reaches .

On the other hand, in the case of (b), six levels of pulses are output during one integration cycle T. The slope of ai is (a)
Since it has the same slope as , if 1 = 0 without the second and subsequent pulses, the saturation level SL will be reached when the light corresponding to the slope a4 is input to the transparent part, but the saturation level SL will be reached by the second pulse. There is a possibility that the slope of reaching SL will be a8, and each time a pulse is generated sequentially, the slope of reaching the saturation level SL will shift, and at the sixth pulse generation, 1 = 0.
When V =
It becomes g32.

The characteristics of ai and gi shown in FIG. 10(b), that is, the amount of charge generated per unit time a representing the input optical signal
FIG. 11 shows the conversion characteristics of the voltage output signal v=g(a), where v=g(a) is a polygonal line approximation of the logarithmic characteristic. The broken line ja shown in FIG. 11 shows the characteristics of ai and gi in the case of FIG. It turns out that it is possible.

Note that it is almost the same even if the accumulation control signal IG shown in FIG. 8 is implemented, and the accumulation control signal IG shown in FIG.
Although it is no longer a polygonal line approximation and becomes continuous, it is of course possible to logarithmically compress an input optical signal having a wide dynamic range.

FIG. 12 shows another embodiment of the accumulation control signal IC, and shows a case where the conversion characteristic is γ=0.5. FIG. 12(a) shows the accumulation control signal when the data is f(x)=α3/X+β3 for address X of the semiconductor memory 16! (b) shows the conversion characteristics of the amount of charge a generated per unit time and the output v = g (a) when the accumulation control signal IC is as shown in (a). This is what I did. In this case, g(a)
=α4·a+β4, and a wide dynamic range can be obtained as in the case of FIG.

[Effects of the Invention] As explained above, the nonlinear photoelectric conversion device according to the present invention limits the amount of charge that can be stored in the storage section of the storage type photoelectric conversion element, and discharges the charge exceeding the limit value to the drain. The storage-type photoelectric conversion element can be manufactured using an extremely simple circuit configuration that includes a discharge gate that has a discharge gate and a charge accumulation control means that controls the height of the potential of the discharge gate that limits the maximum accumulated charge amount as a function of the integral remaining time t. The input/output characteristics can be set as γ and l, making it possible to compress input optical signals with a wide dynamic range and converting them into voltage signals with a good S/N ratio.If this is used as an imaging device, , it becomes possible to input optical image signals with a wide dynamic range such as those from the natural world without saturation.

[Brief explanation of drawings]

The drawings show an embodiment of the nonlinear photoelectric conversion device according to the present invention, and FIG. 1 is an overall configuration diagram, FIG. 2 is a configuration diagram of a storage type photoelectric conversion element, and FIG. 3 is a voltage generation circuit. the first of
FIG. 4 is a configuration diagram of a second embodiment of the function voltage generation circuit, FIG. 5 is a configuration diagram of an integral remaining time generation circuit and a sample clock generation circuit, FIG. 6(a) is a timing chart diagram when the first embodiment of the function voltage generation circuit is used, and FIG. 6(b) is a timing chart diagram when the second embodiment of the function voltage generation circuit is used. Fig. 7 is an explanatory diagram of a charge accumulation control signal giving logarithmic conversion characteristics, Fig. 8 is an explanatory diagram of a step-like charge accumulation control signal giving logarithmic conversion characteristics approximating a polygonal line, and Fig. 9 is an explanatory diagram of a logarithmic conversion characteristic approximating a polygonal line. FIG. 10(a) is an explanatory diagram of charge integration when the charge accumulation control signal is generated only once in a conventional device. FIG. 10(b) is an explanatory diagram of the charge integration according to the present invention. An explanatory diagram of charge integration when a six-level charge accumulation control signal is generated, FIG. 11 is an explanatory diagram of the conversion characteristics between the amount of generated charge and the output voltage, and FIG. 12 (a) is an illustration of the charge accumulation control signal. (b) is an explanatory diagram of the conversion characteristic between the amount of generated charge and the output voltage when the charge accumulation control signal is used. 1 is a clock generation circuit, 2 is a counter, 3 is a drive pulse generation circuit, 4 is an accumulation control signal generation circuit, 7 is an accumulation type photoelectric conversion element, 8 is a photosensitive section, 9 is an accumulation section, 10 is a shift gate, 11 1 is a transfer section, 12 is a detection section, 13 is a discharge gate), 14 is an integration remaining time generation circuit, 15 is a sample clock generation circuit, 16 is a semiconductor memory, 17 is a register,
18 is a function generation circuit, 19 is a D/A converter, 20.20
' is a function voltage generation circuit, 21 is a sample and hold circuit,
22 is an adder circuit. Figure 4 Figure 5 Figure 6 (... Figure 6 (b) Figure 7 t=. Figure 8 ■ Figure 9 Figure 10 (C1) Q○ (b) Figure 11 ■

Claims (1)

[Claims] 1. A photosensitive section that converts a light signal into a charge signal; an accumulation section that accumulates charges generated in the photosensitive section; and a device for discharging part or all of the accumulated charges in the accumulation section to a drain. A discharge gate, a shift gate for transferring the charge integrated in the storage section to the transfer section, a transfer section for transferring the charge transferred via the shift gate, and a transfer section for transferring the charge transferred via the transfer section. A storage type photoelectric conversion element consisting of a detection section that detects and converts it into a voltage signal, a counting means that counts reference clock pulses to generate time information, and a shift pulse that is applied to the shift gate from the output of the counting means. A drive pulse generation circuit that generates a drive pulse to be applied to the transfer unit and a reset pulse to be applied to the detection unit; and a drive pulse generation circuit that generates a drive pulse to be applied to the transfer unit and a reset pulse to be applied to the detection unit; A nonlinear photoelectric conversion device comprising: charge storage control means for controlling charge storage capacity of the storage section by changing a potential. 2. The charge storage control means controls the potential of the discharge gate so that the ratio Qc/t of the charge storage capacitance Qc and the integration remaining time t increases monotonically. The nonlinear photoelectric conversion device according to item 1. 3. The charge accumulation control means is configured such that the relationship between the charge accumulation capacitance Qc and the integration remaining time t is such that Qc=α, with α_1 and β_1 being appropriate constants, in the range of α_1>0 and Qc>0.
3. The nonlinear photoelectric conversion device according to claim 2, wherein the potential of the discharge gate is controlled to be _1logt+β_1.