JPS6281107A - Voltage current converting circuit - Google Patents

Abstract

PURPOSE:To facilitate the constitution and to obtain a desired current ratio with high accuracy by connecting a base of a conversion transistor (TR) in crossing with a collector of a conversion TR of a corresponding stage in a different converting current path sequentially. CONSTITUTION:Output TRs Q11, Q12 and conversion TRs Q12 Q22 whose collector/emitter is inserted respectively in series with the emitter circuit of the output TRs are provided to conversion current paths L1, L2, and the base of each conversion R is connected in crossing with the collector of the conversion TR of a corresponding state of the different conversion current path sequentially. Even when the output current of each conversion current path differs, the difference from emitter-base voltages Vbe of each TR in each conversion current path is cancelled by the difference from the output current so that the output current ratio between the conversion current paths is made independent of the ratio of the emitter areas of the output TRs in each conversion current path.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a voltage-current conversion circuit capable of obtaining two or more converted current outputs, and is used, for example, in a light output control circuit of a laser diode.

[Technical Background of the Invention and Problems Therewith] A conventional voltage-current conversion circuit that can obtain two converted current outputs will be explained using FIG. 10 as an example.

The symbol A in the figure is an operational amplifier, and at the next stage there are first and second conversion current paths 1+ in which an emitter follower-connected output transistor and emitter resistors (conversion resistors) Q+ and R1, and Q2 and R2 are connected in series, respectively. 12 are arranged in parallel. The collectors of each output transistor Q+ and Q2 are
Each is connected to the current output terminal 2a12b.

The voltage input terminal 1 of the operational amplifier A is connected to its non-inverting input terminal ■, and the output terminal has each converted current name! , A2 are commonly connected to the bases of the output transistors Q+ and Q2. Further, the inverting input terminal θ is connected to the non-ground end of the emitter resistor R1 in the first converted current inscription 1.

Then, the input voltage Vi and the converted output current 11, I2
To describe the relationship, the following equation first holds true based on the principle of a virtual short circuit between both input terminals Φθ of the operational amplifier A and the condition that the base voltages of the output transistors Q+ and Q2 in the circuit configuration are equal.

, :e, t O''' 2 is the base-emitter voltage of each output transistor Q1, Q2.

Here, the relationship between the base-emitter voltage vbe of the transistor and the collector current 1c is generally as shown in the following equation.

Vbe=Vt-1n (Ic/Ae-1s)・(2)■
t: thermal voltage (26 mV, at 25°C) 〇: emitter area IS: reverse bias saturation current Substituting the above equation (2) into the above equation (1), 1+ R+
+Vt/url (I+ /Ae+ ・I5)=I
2R2+vt-in (12/ Ae2 ・Is) =・(3) Ae+
, Ae2 is the emitter area of each output transistor Q+, Q2. Equation (3) is transformed as follows.

12 R2=I+ R+ +vt & InAe2 ・
11/Ae1 ・I2...(4) The second term on the right side of the above equation <4) corresponds to the error term, and the emitter area ratio and the current ratio of the output current in this error term are expressed as Ae2 /Ae+ = 12/it
If .=5+ is set, equation (4) can be simply expressed as follows.

12 R2= I+ R+...
・(6) Therefore, from both equations (1) and (6), the relationship between the input voltage Vi and the converted output currents I+ and I2 is as follows:
1+ = V i/R+ 12 = V i/R2・
(7), and each output current 1+, 12 is proportional to the input voltage Vi.

Here, if both river power currents 1+ and 12 are set equal,
From the relationship in equation (5), it is sufficient to use the two power transistors Q1 and Q2 having the same emitter area Ae+ =Ae2 and the same characteristics, so that the voltage-current conversion circuit can be constructed relatively easily.

By the way, when a voltage-current conversion circuit is applied to, for example, an optical output control circuit of a laser light source in an optical disk device, the optical output needs to be controlled to two output levels: read power and write power. Ryogawa power current 1+
, 12 are required to be set to different current values.

In this case, if there is a small difference in the current values of the currents It and I2, it is possible to configure a voltage-current conversion circuit by selecting two output transistors Q1 and Q2 that have a corresponding difference in emitter area. It is possible, but Ryokawa current 1+, 1
When the difference between the current values of the two output transistors Q+ and Q2 becomes large, it becomes difficult to solve this problem using the difference in emitter area between the two output transistors Q+ and Q2. Therefore, Ryokawa power current 1+, 12
For example, if the ratio of current values is 1:n, the 11th
As shown in the figure, all output transistors have the same emitter area, and the first conversion current path (B has
One output transistor Q1 is used, and n output transistors Q1 to Qn are connected in parallel to the second conversion current path fL2. Emitter area ratio Ae2 /Ae
An attempt is made to realize 1=n.

However, if a large ratio of the current values of the Ryokawa power current I+, 12 is required and, for example, n = 10, then 10 output transistors are connected in parallel to the second conversion current path 2. Therefore, there was a problem in that the number of output transistors would be quite large.

Furthermore, since the current ratio of the currents 1+ and 12 depends on the ratio of the emitter areas of the output transistors Qt to Qn, which is difficult to finely adjust, the current ratio of the currents 1+ and 12 obtained by the circuit shown in FIG. There is a problem in that an error tends to occur between the current ratio and the desired current ratio.

[Purpose of the Invention] This invention was made based on the above circumstances, and even when a large current ratio between a plurality of conversion current paths is required, it is possible to configure a circuit without increasing the number of output transistors. It is an object of the present invention to provide a voltage-to-current conversion circuit that can easily realize a desired current ratio and accurately realize a desired current ratio.

[Summary of the Invention] In order to achieve the above object, the present invention has an output transistor and an emitter circuit of the output transistor each having a collector-emitter connected in series in each of the plurality of conversion current paths. By providing a required number of stages of conversion transistors, and by sequentially connecting the bases of these conversion transistors crosswise to the collectors of the conversion transistors of corresponding stages in different conversion current paths, the output current of each conversion current path can be adjusted. Even if the output currents are different, the difference in emitter-base voltage Vbe of each transistor in each conversion current path due to the difference in output current is canceled out, and the current ratio of the output current between each conversion current path is This is done so that it is not dependent on the ratio of the emitter areas of the output transistors.

"First Embodiment" A first embodiment of the present invention will be described below based on FIG. 1. This embodiment has two conversion current paths.

In FIG. 1 and the figures to be described later, the same or equivalent parts as the equipment or circuit elements shown in FIGS. 10 and 11 are designated by the same reference numerals, and redundant explanation will be omitted.

First, to explain the configuration, in this embodiment, there are two conversion current paths, the first conversion current path L+ and the second conversion current path L2, each of which has two output transistors QI.
A total of four transistors, including I N QZI and conversion transistors Q12 and Qu, are arranged in two rows and two columns.

That is, the first conversion current path L2 and the second conversion current path L2
In the first conversion current path L1, the collector and emitter of the conversion transistor Q12 are inserted and connected in series to the emitter circuit of the output transistor Q++, and the emitter of the conversion transistor QI2 is connected to the emitter circuit of the output transistor Q++. A conversion resistor R1 is connected. Similarly to the second conversion current path L2, the output transistor Qλ1, the conversion transistor Q)L, and the conversion resistor R2 are connected in sequence.

In this embodiment in which there are two conversion current paths L+ and L2, each conversion current path L+ and L2 is provided with only one stage of conversion transistors Q12 and Q-, respectively.

In this invention, the final stage conversion transistor refers to the lowest stage conversion transistor in the figure, so in this embodiment, each conversion transistor QI2, Qu
becomes the final stage conversion transistor in each conversion current path L1, L2, and the conversion resistor R+,
R2 are connected to each other.

The base of the conversion transistor Q12 in the first conversion current path L1 is connected to the collector of the conversion transistor Q- in the corresponding stage in the second conversion current path L2, and conversely, the base of the conversion transistor Q12 in the first conversion current path L1 is connected to the collector of the conversion transistor Q- in the corresponding stage in the second conversion current path L2. The base of the conversion transistor Q,- of L2 is connected to the collector of the first conversion current path L1. Therefore, both conversion transistors Q1
2, the base and collector of Q- are cross-coupled.

A feedback line is connected from the non-grounded end of the conversion resistor R1 in the first conversion current path L+ to the inverting input terminal θ of the operational amplifier A.

Next, the action will be explained.

In this embodiment, first, the equation corresponding to the above equation (1) is Vb
eB , V b ex+ are each output transistor Q+
+, Q□ base-emitter voltage, Vb e 1
2. Vbe is each conversion transistor QI2, Q, .
is the base-emitter voltage of Further, II R+ and 12 R2 are equal to the voltages V+ and V2 appearing at the non-ground terminals of the respective conversion resistors R+ and R2, respectively.

Substituting the above equation (2) into equation (8) and transforming it, we get 12
R2=I+ R+ +Vt-fLn(A
e If°I+12/Ae12・Ae哩−I2・I1
)=B R+ +vt-1rl (Aem 6 Aeu /Ae+2IIAew)...
・(9) A e ++ , A ell are each output transistor Q
These are the emitter areas of ++ and Q-, and Ae12 and Ae are the emitter areas of each conversion transistor QI2 and Q-.

The second term on the right side of the above equation (9) corresponds to the error term, and the emitter area ratio of the four transistors in this error term is expressed as A ew - A eu / A e 12 '' A
By setting ex+ = 1 - (TO), this error term can be eliminated.

The above error term elimination condition is set to (5) in the conventional example.
Comparing with the formula, in this example, the emitter area ratio for error term cancellation is the current ratio of the set output current 12/
It can be set independently of II.

For example, if the emitter areas of the two transistors Qo and 012 in each conversion current path L+ and L2 and Qtan and Qμ are set equal as shown below, Aell=Ae1
2 Aea−+=AElz ・(If) The condition of the above formula (1o) is satisfied, and (
6) Similarly to formula 12 R2= I+ R+ ・
...(W holds true, input voltage Vi and each output current 1+,
The relationship with I2 is determined by the following equation.

Therefore, from each current output terminal 2a, 2b, the conversion coefficient 1/
A precisely defined output current 1+, 12 is obtained by the value of R1 or 1/R2, respectively.

Next, FIG. 2 shows a specific example of the first embodiment.

In this specific example, the conversion resistors R+ and R2 in the first and second conversion current paths L1 and L2 are respectively selected to be 10Ω and 1Ω, and the ratio of the dual-purpose currents 11 and I2 is 1:
It is specified to be 10. Further, each current output terminal 2a, 2b is connected to the ten power source line 3a through an output resistance Ra=10 and Ω and an output resistance R9=1 and Ω, respectively. A capacitor C-10 pF connected to the output terminal of operational amplifier A is for preventing oscillation.

In the above specific example, when input voltages Vi=0.2Vpp and V i =3vpp are applied, each conversion resistor R
+ , the voltage appearing at R2 V+ = 1+ ・R1 and V2 = 12 ・An example of measurement of R2 is shown in Figure 3, (b).
, (C) and FIG. 4 (a), (b), and (C), respectively. From these measurement examples, Vi=0.2vpp1
and V + =3vpp, in both cases v
The values of l and V2 are exactly the same, and both conversion resistors R1
and R2 are selected to be 10Ω and 1Ω, so
It has been confirmed that the ratio of the dual-purpose electric power FE I 1 and 12 is precisely defined as 1:10.

Next, FIG. 5 shows an application example of the first embodiment.

This application example is an application of the first embodiment to an optical output control circuit for a Raded diode having a function of compensating temperature characteristics of optical output.

When a laser diode LD is used as a light source of an optical disk device, for example, its optical output PO needs to be controlled to two different output values for read power and write power. In this application example, the voltage-current conversion circuit J is used as a reference current source circuit in an optical output control circuit, and its two different output currents I+, 12 are used as the first and second reference currents in the optical output control circuit. 1refl, 1r
ef2, and the optical output of the laser diode LD is controlled to two levels of output levels corresponding to the first and second reference current values.

In FIG. 5, the symbol PD is a photodiode for monitoring the optical output PO of the laser diode LD, and the common connection terminal 4a of the 7 nodes of the laser diode LD and the cathode of the photodiode PD is
From a, the driving transistor Q8 and the forward current I
A forward current circuit 5 including a resistor RI4 for regulating f to a maximum rated value is connected. R15 is a resistor for setting the bias current of the driving transistor QB, and also serves as an output resistor of the control transistor Q9, which will be described next.

Q9 is a control transistor, and a J FET is used. The control transistor Q9 inverts and amplifies the difference current between the photovoltaic current (monitor current) Is of the photodiode PD and the reference current (ref or) ref2 set in the reference current source circuit J, and controls the laser diode LD. This is for feeding back to the forward current circuit 5 and controlling the optical output po to an output level corresponding to its reference current .rerl or (ref2).

Symbol R+s is a detection resistor, Q+o is a limiting transistor, and these detection resistors R+e and limiting transistors Q+o provide the maximum rated current (
A forward current limiting circuit is configured to limit the flow of a forward current 1f exceeding the current limit (current limit).

Further, a changeover switch circuit configured as follows is connected between the anode terminal 4C of the photodiode PD and the reference current source circuit J.

That is, the first and second differential circuits 6a each include a pair of transistors Q3, Q4, and Qs, Qe.

6b is configured, and the first and second differential circuits 5a.

6b constitutes a changeover switch circuit for switching the reference current (ref to two values Iref1 or 1ref2).The base of the transistor Q3 in the first differential circuit 6a and the base of the transistor Q3 in the second differential circuit 6b A switching control voltage Vc is applied to the base of the transistor Q8 from the control voltage input terminal 7. On the other hand, the first differential circuit 6
A reference voltage (ground potential in the illustrated example) vref is applied to the base of the transistor Q4 in a and the base of the transistor Q5 in the second differential circuit 6b.

The relationship between the switching control voltage VC and the reference current Vref is
When Vc>Vref, the transistor Q3 in the first differential circuit 6a turns on, and the reference current 1ref becomes
First reference current 1ref in first conversion current path L1
l is set.

On the other hand, when VC<Vref, the transistor Q5 in the second differential circuit 6b turns on and the reference current Iref
is the second reference current 1r in the second conversion current path L2
et'2.

Furthermore, in this application example, the first and second reference currents [ref
l, Iref2 has a temperature coefficient with the opposite sign to the optical output temperature coefficient of the laser diode LD and a value corresponding to the optical output temperature coefficient, so that the optical output 1]0 can be made stable against temperature changes. For control purposes, the following circuit is provided on the input terminal side of operational amplifier A.

That is, first, a series circuit of a transistor Q7 and two resistors R11 and R12 is connected between the ground and the - power supply line 3b. Resistors R11 and R12 have the same resistance temperature coefficient.

R13 is a resistor for setting the base bias current of the transistor Q7, and the base of the transistor Q7 is further connected to one power supply line 3b via a forward-connected diode D and a reverse-connected Zener diode ZD.

The connection point between resistor Rn and R12 is the operational amplifier A.
is connected to the Φλ force terminal.

Diode D has a forward voltage of transistor Q7.
A voltage having the same value as the base-emitter voltage Vbe of , and also having the same temperature characteristics as that voltage is used.

The Zener diode ZD has a Zener voltage Vz having a temperature coefficient with an opposite sign to the temperature coefficient of the optical output PO of the laser diode LD, and the coefficient value has a value corresponding to the temperature coefficient of the optical output po. Those that have are selected.

As mentioned above, since the forward voltage of the diode D and the base-emitter voltage Vbe of the transistor Q7 have the same value, a voltage equal to the Zener voltage VZ is applied to the emitter of the transistor Q7. appears. Therefore, the input voltage Vi input to the non-inverting input terminal Φ of operational amplifier A is V i =vz 6 R12/ (R11+RI2)
becomes.

Therefore, from the above equation, the input WaVi to the operational amplifier includes the temperature coefficient of the Zener voltage Vz, so from the relationship of the Q'3 equation, the first and second reference currents 1ref+
(=I+) and U l r e f' 2 (=I
2) has the required temperature coefficient.

In this way, in this application, the laser diode L
The optical output po of D is equal to the first and second reference currents 1ref1
, Iref2 is precisely controlled to two levels of output level corresponding to Iref2, and the temperature characteristics of the Zener voltage VZ of the Zener diode ZD are used to
D's light output p.

temperature characteristics are compensated.

"Second Embodiment" Next, FIG. 6 shows a second embodiment of the present invention. This is a conversion circuit.

In this example, three output transistors Q++, Q,
I, Qb+ and six conversion transistors QI2, Q
A total of nine transistors, λ\1Q1, Q10.01%, and Q3i, are arranged in 3 rows and 3 columns.

The first to third conversion current paths 11 to L3 include two stages of conversion transistors QI2 and Q10, QΩ and Q10, respectively.
and QJ Yu and R31 are connected. The base of each conversion transistor is cross-coupled to the collector of the conversion transistor of the corresponding stage in successively different conversion current paths, etc., which is the same as in the first embodiment shown in FIG. .

To explain the operation, in this embodiment, the equation corresponding to the above equation (8) is expressed as follows.

Vt-I+R+ 1+ R1+Vbe13+Vbe3h+'Jbey=
[2R2+ 'J bez3 +Vbe12 +Vt)
eql= 13 R3+Vbe13+Vbe-+Vbe
u...(2) Hereinafter, using this formula as the starting formula, each formula can be modified and operated in almost the same way as in the first embodiment, and the input corresponding to formula 03 can be Voltage v1 and each output current 1
The relationship between + and 12.13 is determined by the following equation.

1+ =V l /R+ =V+ /R+12 =V
i/R2=V2/R2l3=V i/R3=V3
/R3...■And each current output terminal 2a, 2b, 2
c is the conversion coefficient 1/R+, 1/R2 or 1/R
3. Output current precisely defined by 1. +, I2.1
3 are obtained respectively.

“Third Example” Next, FIG. 7 shows a third embodiment of the present invention.

In this example, the conversion current path LI% 12 , I3 N
This is a 4-output type voltage-current conversion circuit by arranging four I4s in parallel.

In this example, four output transistors Qu, Q
A total of 16 transistors, including N QS+ 1Q++ and 12 conversion transistors Qt2 to 044, are arranged in 4 rows and 4
arranged in columns.

The first to fourth conversion current paths L1 to L4 include three stages of conversion transistors Q12, Q10 and Q10, Q〉 and α, Q3B and R21, and Q1 and 0, respectively.
43 and Q+ are connected. The base of each conversion transistor is cross-coupled to the collector of the conversion transistor of the corresponding stage in successively different conversion current paths, etc., which is the same as in the second embodiment shown in FIG. 7. .

To explain the operation, in this embodiment, the equation corresponding to the above equation (8) is expressed as follows.

■1=lIR* 1+ R+ +Vben+Vbe43+Vbe5z+V
beL1 = 12 ・2RI+Vbe4+Vbe130V b
e4L+ V be31 = 13 ・3R+ +Vt)e14+Vt)e
hx+ V b e 12 + V b e4゜-14
・4R+ +Vbe44+VI) eis 10V be
LL + V b e u...0e Hereinafter, using this equation (g) as the starting equation, each equation can be modified and operated in almost the same way as in the first embodiment, and the equation θ) above can be used as the starting equation. Input voltage ■i and each output current I corresponding to
The relationship between +, 12, and I3.14 is determined by the following equation.

I+ =V i /Rt =Vt /R+12 =V
i/2R+ =V2 /2R+I3 =V i/3R+
=V3/3R+14=Vi/4R+ =V4/4Rt...0 However, from each current output terminal 2a, 2b, 2C12d, the conversion coefficient 1/R+, 1/2R+, 1/3R1 or 1
/4 Output current I+ precisely defined by R+,
I2, Ill, and 14 are obtained, respectively.

This embodiment can be applied to a 4-bit D/A converter, etc.

"Fourth Embodiment" FIG. 8 shows a fourth embodiment of the present invention. In this embodiment, a pair of two-output type circuits corresponding to the first embodiment shown in FIG. 1 are arranged symmetrically to form a differential input type voltage-current conversion circuit.

Each first conversion current path L1 in the pair of left and right circuits,
A resistor R4 is connected between the emitters of the conversion transistors QI2 and Q12 in LI', and similarly, each second
Another resistor R4 is also connected between the emitters of the conversion transistors Q1 and QU in the conversion current paths L2 and L2'.

Next, the action will be explained.

The input voltages input to the left and right voltage input terminals ia and ib are respectively ■il, Vi2, and each current output terminal 2a, 2b,
The output currents from 2a' and 2b' are I+ and
12, I+', I2' The current flowing between the emitters of the N conversion transistors Q+2 and Q12 is
+, another conversion transistor Q4, the current flowing between the emitters of the Q pot IC2, each conversion current path L+,
12% The bias currents flowing in L+' and L2' are respectively Ib+, Ib2, It)+'', and Ib
2'.

Here, the bias currents 1b+ and Ib+' are as described above (
This corresponds to the current Vi/R+ in Equation 111, and the other bias currents Ib2 and Ib2' similarly correspond to the current Vi/R2 in Equation 03).

Each first conversion current path L1, L+' in the left and right circuits
To explain the output currents 1+ and I+' that flow between the connection points 9a and 9b, the current IC+ that flows between the connection points 9a and 9b is: IC+ = (Vi+ - Vi2)/R4 = ΔVi/R4 Therefore, each output current! +,! + ' is I+ = I
C+ +Ib+ =ΔVi/R4+ltg1+' =
IC+lb1' = -ΔVi/R4+lb,', and each output current has a bias current 1b+, Ib
In addition to +', a current depending on the voltage difference Δv1 between both input voltages is added or subtracted.

The output current 12.12' flowing through each of the second conversion current paths L2 and L2' can also be expressed in the same way as above.12=ΔVi/R4+Ib2 12'=-ΔVi/R4+Ib2
' becomes.

"Fifth Embodiment" FIG. 9 shows a fifth embodiment of the present invention. In this embodiment, three 3-output type circuits corresponding to the second embodiment shown in FIG. 6 are arranged in a Δ type, and the differential input type voltage This is a current conversion circuit.

First conversion current path L1, L+' in each of the three circuits
, Lt", the output currents I+, I+', and 11" flowing through the connection points 11a and 11bfi! 1
, 11b and 11C, and between 11C and 11a, are expressed as IC+, lc2 and Ices, respectively.
Then, ICt-(Vi+-Vi2)/Rs=ΔVia
/R5 IC2= (V i 2 - V i 3 )/Rs
=ΔVt2/R5 IC3= (VI3-Vit)/Rs=ΔV
t3 /Rs Therefore, each output current I+, It', It'' is 1+
=ICI IC3+Ib+ =(ΔVt1-ΔVi3)/Rs +It)+I+
'=IC2-IC+ +lb,'-(ΔV iz-
8V it >/Rs+lbl' B ``-IC3-IC2+lbl'' = (ΔV i3-ΔV iz )/Rs+Ib'', and each output current 11, ■1', 11'' has a bias current 1b+, Ibt', Ib'' In addition, the difference voltage ΔV between the three input voltages Vi+, Vi2, and Vi3 is the same.
Currents depending on t1, ΔVi2, ΔVi3 are added or subtracted.

Second conversion current path L2.12', L in each circuit
2″, and the third conversion current path 13 N L3 ′,
Although the expressions for the output currents 12, 12', I2", and 13, I3', 13" flowing through the output currents 13" and 13" are omitted, they are also obtained in substantially the same manner as above.

This embodiment can be applied to cases where three-phase voltages are converted into three-phase required current values.

"Effects of the Invention" As explained above, according to the present invention, in each of the plurality of conversion current paths, an output transistor and an emitter circuit of this output transistor are each inserted in series between the collector and emitter. The required number of stages of conversion transistors are provided, and the bases of the conversion transistors are cross-connected to the collectors of the conversion transistors of corresponding stages in different conversion current paths in sequence, so that the output current of each conversion current path is Even if the output currents are different, the difference in emitter-base voltage of each transistor in each conversion current path due to the difference in output current is canceled out, and the current ratio of the output currents between each conversion current path is equal to the output in each conversion current path. It is no longer dependent on the ratio of emitter areas of transistors. Therefore, even when a large current ratio between multiple conversion current paths is required, there is no need to increase the number of output transistors, which simplifies the configuration, and has the advantage that the desired current ratio can be obtained with high precision. be.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a voltage-current conversion circuit according to the present invention, FIG. 2 is a circuit diagram showing a specific example of the present invention, and FIGS. 3 and 4 show voltages of the same specific example. A waveform diagram showing current conversion characteristics, FIG. 5 is a circuit diagram showing an application example of this invention, FIG. 6 is a circuit diagram showing a second embodiment of this invention, and FIG. 7 is a circuit diagram showing a third embodiment of this invention. 8 is a circuit diagram showing a fourth embodiment of the invention, FIG. 9 is a circuit diagram showing a fifth embodiment of the invention, and FIG. 10 is a circuit diagram showing a conventional voltage-current conversion circuit. , FIG. 11 is a circuit diagram showing another conventional example. 1.1a11C... Voltage input terminal, 2a-2d... M outflow terminal, A... Operational amplifier, L+, L2, L3, L4... Conversion current path, Q
II, Ql, N Q1, Q4 pin...output transistor, Q12-Q44...conversion transistor, R+
, R2, Rs...conversion resistor. Agent Patent Attorney Noriyuki Ken Chika Patent Attorney Nori Ogo Figure 3 Figure 4 3b Figure 6 Figure 7

Claims (1)

[Scope of Claims] A voltage-current conversion circuit in which a plurality of conversion current paths are set, wherein each of the conversion current paths includes an output transistor whose collector is an output terminal, and a collector connected to an emitter circuit of the output transistor. - Consisting of a required number of conversion transistors inserted in series between emitters and a conversion resistor connected to the emitter of the conversion transistor at the final stage, and the bases of the conversion transistors are connected to the conversion current that is different in sequence. The input voltage is input to the non-inverting input terminal, the output terminal is commonly connected to the base of the output transistor in each of the conversion current paths, and the inverting input terminal is connected to the collector of the conversion transistor in the corresponding stage in the conversion current path. A voltage-current conversion circuit characterized in that an operational amplifier is disposed at a connection point between the emitter of the conversion transistor and the conversion resistor in the conversion current path.