JPS6278642A - Control system for memory control unit - Google Patents

Abstract

PURPOSE:To improve the performance of a virtual computer system by securing the direct use of an address conversion table through a memory control unit for execution of the conversion of addresses and the check of protection. CONSTITUTION:A memory control unit MMU22 uses directly an address conversion table 19 of an operating system OS16. Then the execution of address conversion is inhibited by a non-conversion indicating signal line 29 when the operation is sent back to a control program VMCP18 from a program (OS, AP) on a virtual computer. In addition, such a case is avoided by a SUB signal line 28 that a logic address space receives an access from a program which is executed in a user mode with a report given to the MMU22 from a CPU21.

Description

[Detailed description of the invention]

[Field of Application of the Invention 1] The present invention relates to a control method for a memory management unit in a virtual computer system, and particularly to improving the performance of a virtual computer system in which multiple virtual computers operate in parallel on one real computer. The present invention relates to a preferred memory management unit control method. [Background of the Invention] Usually, a real computer system has a central processing unit as shown in Figure 2. (c p U)], memory management unit M
MU)2. Main memory (MEM) 3. Human output control device i (I 0C) 4, input/output equipment storage system (IO) 5 a
, 513..., Appli Cage Men Progera 4 (A
P) 7 a. 7b...7, and an operating system 11 (hereinafter referred to as O8) 6 that controls both the hardware and the rough 1 to software. On the other hand, a virtual computer system (hereinafter referred to as VMS) is used to cause multiple virtual machines (hereinafter referred to as VMs) to execute Me line number processing on the above-mentioned real computer system. As shown in FIG. 3, each part 1 to 1 in FIG.
5b, a central processing unit similar to each software 6-7 (
CPU) II, memory management unit (MMU) 12.・
......Application program (AP)
) 17b, 0816 and central processing unit (CP
U) Virtual machine control program (hereinafter referred to as VMC)
(referred to as P) 18. This VMCPlg
is the central processing unit (CPU) 11 instead of O86 in Figure 2.
Corresponding to this, the real computer system shown in FIG. 2 is operated as a plurality of virtual computers. In the VM 9, an area is provided for each VM in the main memory (MwM) 13, and a central processing unit (CPTJ) is installed in that area.
) 11, etc., and have each VM use a real computer in a time-sharing manner to operate each VM under the control of each O8 (not shown) that corresponds to multiple VMs. Application program (AP)
Execute the process. In other words, each O8 has their own time.
``Arithmetic registers'' are virtual hardware within the slot. 1 control register', 'instruction address register'. By setting up a 'memory management unit', a memory device, etc. on real hardware, one real computer can operate as if it were a separate side computer. In other words, multiple operating systems are running simultaneously on one actual computer. In a conventional VMS, a memory area is fixedly allocated to a running VM, and the address translation table 19 managed by the 0816 on that VM is stored in a memory management unit (
A method is known in which the MMU 12 directly performs address translation (logical address to physical address) to improve the performance of the VMS. Note that Japanese Patent Laid-Open No. 53-142137, Japanese Patent Laid-Open No. 54-052929@publication, etc. are cited as methods for fixedly allocating the memory used by the VM to lower the performance of the VMS by 11%. However, a 'protection code' corresponding to the execution mode of the central processing unit (Cp [1) +1] is provided in the address translation table 19 of the 0816, and it is sent to the memory management unit (MMTJ) 12 during address translation. The application program (A
P) In order to prevent it from being broken by bugs in 17a and I7b, a ``protection check'' is performed, but when setting the execution mode, 0816 of 7M''2 Since the memory management unit (MMU) 12 sets a ``protection code'' that is accessible only in ``supervisor mode I'' to the address translation table 19 even though it is executed in ``mode'', the memory management unit (MMU) 12 has a ``protection check'' error. Since it is determined that the address is not converted and the VMCP 18 is bypassed each time, a lot of processing time is lost. In addition, since the memory area of VMCPlg is not defined in the address translation table 19 managed by O81, 6 on the VM, when the program on the VM returns to the operation of VMCPlg, the memory management unit (MMU) 12 Main memory bag f directly to VMCPI8 without address conversion
It is necessary to use il(MEM)23. [Object of the invention] The object of the present invention is to solve such conventional problems and to
In a virtual machine system in which the address translation table is set to supervisor mode, there is a simple and inexpensive method that allows the memory management unit (MMtJ) to directly use the address translation table to perform address translation and protection checks. Computer Sisteno, (VM
An object of the present invention is to provide a memory management unit control method that can improve the performance of S). [Summary of the Invention] In order to achieve the above object, the memory management unit control method of the present invention provides a memory management unit control method for controlling a memory management unit in a virtual computer system having a plurality of operating systems. A first storage means (VM bit 32) for storing the 'execution mode' of the program on the virtual machine, a second storage means (PC bit 32) for storing the 'execution mode' of the program on the virtual machine, and a protection check by the memory management unit. Signals for control (ST, J signal 2
8); and means (hrp signal 29) for instructing the memory management unit to perform address conversion to non-conversion (hrp signal 29); (] Directly use O9 to program (1) virtual computer-L (O
8 or AP) to return to the operation of the control program (VMCP18) that controls the virtual nI computer, 1-
The present invention is characterized in that the rear address conversion is not executed in accordance with the valve allocation conversion instruction, and the protection check is performed based on the 1 and 2 control signals output based on the contents of the first and second storage means. [Embodiments of the Invention] Examples of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a virtual SL computer system (VMS) showing an embodiment of the present invention. In the figure, 21 is a central processing unit (CPU) that performs various processes, and 22 is a memory management unit (MM) that performs logical/physical address conversion.
TJ), 23: 8vM processing progera! 1, etc., 24 is C) 16 data lines used for data transfer between iJ21 and MEM 23, and 32-bit address signal output by 25 CPU2+. These are the lower 12 offset address lines, which directly connect the CPU2+ and MEM23, and 26 is the lower 12 offset address lines.
These are the upper 20 logical address lines in 2 bits 1-, and M
A ``logical address signal'' is sent to the M TJ 22. 27 are 20 physical address lines that send out the ``physical address signal'' converted by MM 1122 to MEM 23;
8 changes the VMS execution mode from CI”TJ21 to MMIJ
S U signal line reporting to 22, 29 is cpn2] to M
M tJ22 head address non-conversion operation (logic)
'Contents of dress line 26 &+ remains physical atto L nos line 2V
13 [3 signal lines to instruct each signal to be sent out. Note that this system operates according to the VMS software configuration shown in FIG. 3. Further, only the ``supervisor mode'' can execute the ``privileged instruction'', and only the VM(:) 18 can execute the ``special camellia instruction''. In other words, 0 running at 'user-board'
316. It is not possible to execute a privileged instruction in AP27. V M , the poor algorithm (0816 or AP17a, 17b) of 1x is v
Operating in ``user mode'' under the control of MCP 18 9 Furthermore, by reporting the execution mode using the S tJ signal line 28, the logical address space of the program executed in ``supervisor mode'' is set to 1 user mode. This prevents it from being accessed by programs running in . The following FIG. 4 is a configuration diagram of the VM control register 30 and status register 35. In the same figure, 30 is V M
, PC pin 1 indicating the ``execution mode'' of the t-program.
A VM control register 31 stores a VM bit 32 indicating that the VMS is in operation, and a status 1 register 35 stores an S bit indicating an ``execution mode'' of the CPU 1l. In addition, both registers 30 and 35 are CF) U
Implemented within 21. Also, S p1- is cp'tTi
When i is in 'supervisor mode'

[SLVJ, set to 0 when in user mode.CPNll is set to 0 when pc bit 31 is 111' (VM is in supervisor mode) and VM bit 32 is LLll (in operation). is CPUII itself-8
= STI signal 28 is i+ 1, regardless of the execution mode of
, , i.e. the VMS is in 'supervisor mode'
Reports to MMN 22 that it is in operation 4.Meanwhile,
VM bit 32 is '1' (VMS is in operation),
PU], if the execution mode of 1 is 'supervisor mode', the BP signal 29 is set to 1''', i.e. VM
CP18 (7) operation (1) instructs the MMU 22 not to perform 7-dress conversion. Each of the above bits 31, 32, 36 and J, and both control signals 28
．． The relationship between 29 and the execution program during operation of the VMS is not shown in FIG. In other words, when VMCP18 is operating, S-pill-36,
VM Pi 1-32. STJ signal 28 operation 1. :IRP
All signals 29 are set to II 111, and ``Supervisor mode'' and ``Address conversion offer'' are set to MM (J
22. Then 0816 at V M , 1-:
When operating, the PC picks 1-31. VM Bee) l-32, S
t■iii□'+ 28 are all If I II,'
The supervisor instructs the MMIJ 22 to 'execute address translation'. Next, when operating APs 17a and 1.7b at
Instructs the MMU 22 to 'execute address translation'. Similarly, the relationship between the bits 31, 32, 36 and the surface control signals 28, 29 and the execution program during operation of the actual computer system is as shown in FIG. In other words, when O86 operates, the S bit is 36°STJ.
Set all signals 28 to '1' and set pc bit 31 to '111'
/ II Regardless of OII, 'Supervisor
Instruct the MMU2 to set the mode'. Next, AP7a, 7b
, . . , instructs the MMU 2 to operate in 'user mode'. In this way, in the operation of a real computer system, the original operation is guaranteed by always setting the VM bit 32 to '0'. The VMS in this embodiment is a KVM as shown in FIG.
0816 is operated under the control of CP18, and its 081
APs 17a, 17b, . . . are operated under the control of AP 6. Inside the CPU, 0816 under VM
run in ``user mode''. On VM (7) O8
When 16 (or AP1, 7) issues a 'privileged instruction' to control CI) Ul, 1 or l0C14 while operating in 'user mode', VMCP18 detects it as a 'privileged instruction interrupt'. After that, based on that instruction, VMCPI3 goes into ``supervisor mode'', for example, 7M (7) virtual CPU II or virtual l
Controls 0C14. In other words, when a "privileged instruction arrival interrupt" occurs, the execution mode is automatically switched to "supervisor mode" and control is transferred to VMCP18, so that the actual l0C1 corresponding to the virtual input/output device
Enables execution of ``privileged instructions'' that control 4. ○ A 'privileged instruction' in which S16 sets the address of the address conversion table 19 in the control register located in the width of the MMU22.
As mentioned above, a "privileged instruction arrival interrupt" is generated and control is transferred to the VMCP18.When the VMCP18 receives the "privileged instruction arrival interrupt", it writes the 0816 to the control register in the MMU22. Then, the table address of the address conversion table 19 is set. Based on that at L/X, the MMU 22 sets the VM lower +71O8.
Address translation, protection checking, etc. are performed by directly using the address translation table I9 set by 16. For this reason, the programs used by each VM are fixedly allocated on memory. Next, two problems arise when the MMU 22 is made to directly use the address translation table 19 set by the 0816 on the VM, which will be described below. The first issue is that since there is no VMCP18 area in the logical address space managed by 0816 on the VM, the address conversion function of MMTJ22 can be bypassed when control is transferred from 0816 on VM to VMCP18. , the address needs to be untranslated. In order to achieve this, ■ VMCP13 has the ■ ゛M bit 1 of the VM control register 30 at the same time as starting the VMS.
2 to "1" (VM in operation). ■CPU
VM running in 'user mode' in 21
When transferring control from the above program (0816 or APl7) to VMCP18 operating in 1 supervisor mode', the MMTJ22 from CPU21
BP signal 29 to 0171, M M t-722
command not to perform address conversion (VM in Figure 5).
(See CP operation). Regarding this procedure, if the S bit 36 of the status register 35 in the CPU 21 is 100u
BP signal 29 only if the VM bit 32 of the VM control register 3° is II 177.
This is done so that sr is 1″″. As the second eight, 0816 on the VM assumes that it is running in 'supervisor mode', and
The O8 area of the address translation table 19 indicated by U2 is set to be accessible only in ``supervisor mode,'' whereas it operates in ``user mode'' within CPU II. In this case, a 'protection check' error occurs due to MMU22, and 0
816 cannot access the O8 area of MEM23. In order to eliminate this, ■VMCP18 is 0816 under VM.
PC bit 3 of VM control register 3° when starting
Set N 1 +7 to 1, A on VM, P17a
, 17b, the VM control register 30 PC
Set bit 31 to '0''. @CPTJ2L to MMU22 (7) STJ signal 28 is output according to the following logical formula. 5U=S or (VM and PC)..."
(1) However, or is logical sum, and is logical product, S,
VM and PC are the contents of the bits. In other words, the mode of the real computer (VM bit 32 is
OII), S bit 3 of status register 35
6 is output as is as 50m No. 28, and on the other hand, when in VM mode (VM pitch h32 is 1 degree), -■-S bit 36 and PC bit 3 are the same as fiB.
The logical sum of both contents with 1 is output as the STJ signal 28. As a result, even though VM-HI's 0816 is operating in 'user mode', the MMU 22 recognizes it as operating in 'supervisor mode'.
Since the 0816 performs a 'protection check', it can operate without causing a 'protection check' error. In this way, when 0816 is executed on the VM, even though the internal execution mode of the cPU is 'user mode', it is reported to the MMU 22 that it is '1 supervisor mode', and the address translation table is protection code and C
By preventing 1 protection check' errors when comparing PTTil's executable code. To reduce the processing of the VMCP 18 by performing address translation, and to have the MMU 22 directly use the address translation table set by O8+6 on the VM, and also control the address translation without going through the VMCP 18. As a result, a high-performance virtual computer system can be realized. In addition, 7MC from Progera 11 on VM-
1118, that is, the execution mode of cpuii changes from "user/host" to "supervisor/host".
When the CPU changes to the VM mode, the CPU II detects that the VMS is in operation, sends HPrn number 29, and sets the MMTI 22 to address non-conversion -15. It became possible to move to
VMCP18 manages each VM in 'supervisor mode'.
can be controlled. In this embodiment, the VM control register 30 and the status register 35 are built into the CPU 21, so that the same system configuration can be used when operating on a real computer system and when operating on a VMS. Also, CPU21
By providing the inner U signal line 28 and the BP signal line 29 as hardware, the CPTJ 21 and MMU 22 can be configured as separate chips. [Effects of the Invention] As explained above, according to the present invention, O8 on the VM
In a virtual machine system where the address translation table corresponding to the O8 area can be referenced only in supervisor mode, VM pin 1- is set to ``Operating'', and I''C pin 1- is set to ``Operating'' of VMS, and I''C pin 1- is set to When the ``supervisor mode'' of the program is stored, M
Since 'supervisor mode' and 'address non-conversion instructions' are sent to M U in a hardware manner, M M U can perform the address conversion set by O8 of VM-1- without using any special circuit components. Tables can be used directly to perform address translation and protection checks, and VMS performance is greatly improved.

[Brief explanation of drawings]

FIG. 1 shows a virtual computer system (
Figure 2 is the software configuration diagram of the real computer, Figure 3 is the software configuration diagram of the virtual machine system (VMS), Figure 4 is the configuration diagram of the VM control register and status register, and Figure 5 is the configuration diagram of the VM control register and status register. Virtual computer system (
FIG. 6 is a diagram showing the states of registers and control signals during operation of the actual computer system. 1.11: Central processing unit (cpU), 2, 12: Memory management unit (MMTJ), 3.13: Main memory (MEM), 4.14: Input/output control unit-OC), 5
a, 5b, 15a, 15b: Input/output device system (10), 6
．． 16: Operating System (O8), 7a,
7b...7, 17a, 17bi application program (AP), I8: Virtual computer control program (
VMCP), 19 Near address conversion table, 21: Central processing bag [1 (CPU), 22: Memory management unit (M
MU), 23: Main memory (MEM), 24: Data line, 25: Offset address line, 26: Logical address L27: Physical address line, 28: SU signal line, 29
: BP signal line, 30: VM*J control register, 31
: PC bit, 32: VM bit, 35: Status register, 36: S bit.

Claims (1)

[Claims] (1) Memory management unit, multiple operating systems
In a virtual computer system having a system, a first storage means for storing 'in operation' of the virtual computer system, and an 'execution mode' of a program on the virtual computer.
a second storage means for storing a protection check by the memory management unit, a means for outputting a signal for controlling a protection check by the memory management unit, and a means for instructing the memory management unit to perform address conversion to non-conversion; The unit directly uses the address translation table of the operating system and does not execute rear address translation according to the non-conversion instruction when returning from the program on the virtual machine to the operation of the control program that controls the virtual machine. A memory management unit control method characterized in that a protection check is performed based on the control signal output based on the contents of the first and second storage means.