JPS6275977A - Digital audio disk reproducing device - Google Patents

Abstract

PURPOSE:To facilitate a change over control and apply a general frequency characteristic to a digital sound signal by reading an input digital signal bit every sampling cycle and by performing a change over of a deemphasis and a non-deemphasis by an instantaneous change over of a program. CONSTITUTION:A digital sound signal and a deemphasis change over signal reproduced and obtained from a player part 1 in a signal processing part 11 of a reproducing device are outputted at a prescribed sampling frequency. The amplitude data designating an optional equalizer characteristic or a filter coefficient are outputted from an operating part 17 and applied to digital signal processors DSP12L, 12R. Digital filters of both side channels are constituted of the DSP12L and 12R, an oscillator 14 of interruption circuits 13L, 13R, input interface circuits 15L, 15R and output circuits 16L, 16R. A sound signal and a change over signal from the processing part 11 and added to both the filters to facilitate a change over and a control and a general frequency characteristic is applied to the sound signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital audio disc playback device, and more particularly, a programmable digital filter is used to impart necessary de-emphasis characteristics, non-de-emphasis characteristics, or arbitrary characteristics to a reproduced digital audio signal. This applies to digital audio disc playback devices that switch and apply equalizer characteristics.

Prior Art Conventional Digital Audio Disc Playback 111 (
D-mk-z&゛T1flJt6°y'#')9
/L/°t-1 A compact disc (CD) is known as a digital disc. FIG. 15 shows a block system diagram of an example of a conventional compact disc playback IIF. This compact disc playback device has a left channel (hereinafter referred to as UL-channel).
, for example, one sampling point obtained by separately pulse code modulating (PCM modulating) the two channels of audio signals of the right channel (hereinafter referred to as "R channel") at a sampling frequency (sampling frequency) of 44.1 kHz. Digital data with a quantization bit count of 16 bits per unit, a control signal,
One block consisting of error correction code, synchronization signal, etc.
After the signals of 1 frame) are synthesized in time series for each frame, EFM modulation (Eight t.

Fourteen Modulation) and recorded.

Further, the digital data is interleaved and scrambled to rearrange the data arrangement order.

Here, in order to improve the S/N of the audio signal reproduced from a compact disc (CD), pre-emphasis is performed on the audio signal to emphasize high frequencies during recording.
During reproduction, a de-emphasis characteristic complementary to the pre-emphasis characteristic is given to the reproduced audio signal. However, the analog filter used in the de-emphasis circuit affects the phase characteristics of the reproduced audio signal, causing problems such as fluctuations in sound localization and deterioration of sound quality. For this reason, pre-emphasis has traditionally been performed on audio signals with a particularly wide dynamic range (such as classical music) during recording and de-emphasis during playback, but audio signals that do not require a large dynamic range (such as classical music) For example, popular music)
The above-mentioned pre-emphasis is not performed for , and therefore no de-emphasis is performed either. Therefore, depending on the presence or absence of pre-emphasis of the recorded audio signal of the compact disc to be played back, one of the control signals in each frame of the recorded signal is
A de-emphasis switching presence/absence code is provided in each bit, and the playback device switches whether or not to apply a de-emphasis characteristic based on this one bit.

Now, in FIG. 15, a digital audio signal taken out from a player section 1 that performs disk tracing is supplied to a signal processing section 2. As shown in FIG. After demodulating this digital audio signal, the signal processing unit 2 performs dinterleaving and descrambling to rearrange the digital audio signal in a predetermined order, and also detects and corrects error data to obtain digital signals for each of the L and R channels. The data is alternately output to the D/A converter 3.4 at a predetermined sampling period.

The D/A converters 3.4 separate the input digital data into L channel data and R channel data according to the signals supplied from the signal processing section 2, convert them into analog signals, and output the analog signals to the de-emphasis circuits 5 and 6. do.

A de-emphasis switching signal based on a predetermined bit in each frame is supplied from the signal processing unit 2 to the de-en7192 circuits 5 and 6, and when this switching signal is at a high level, for example, the input analog audio signal is De-emphasis is performed which gives the opposite characteristics to the pre-emphasis described above, while no de-emphasis is performed when the signal is at a low level.

are output from the de-emphasis circuits 5 and 6 respectively, and R
A total of two channels of analog audio signals are processed by a low-pass filter (LPF) for converting the audible frequency band component signal into a P-wave.7.
8 to output terminals 9 and 10, respectively.

Problems to be Solved by the Invention The above-mentioned conventional playback device directly converts the two channels of digital data output from the signal processing section 2 into the D/A converter 3.
, 4, converts it into an analog signal, and sends the output to a de-emphasis circuit 5.6. However, since this Dien 7192 circuit 5.6 is a so-called analog filter, it causes deterioration of sound quality due to phase distortion peculiar to analog filters for reproduced audio signals that impart de-emphasis characteristics, and also Due to the incoming spurious noise, the S/N
is degraded by, for example, 10 dB, and furthermore, it is impossible to avoid inaccuracies in de-emphasis characteristics due to numerical deviations (variations) of analog elements such as capacitors and resistors, and when de-emphasis characteristics are applied or not applied,
Or, in the opposite case, there is a problem in that the followability of de-emphasis switching is poor, and therefore de-emphasis cannot be switched during a song.

In addition, in order to add arbitrary equalizer characteristics according to the listener's preference for the purpose of reducing listening noise, etc. to the reproduction signal from the conventional reproduction device, it is necessary to Another problem was that an equalizer (equalizer 1 not shown) had to be provided separately.

Therefore, the present invention provides a digital signal processor that is a high-speed performance processor that can share the de-emphasis circuit and equalizer between the signal processing section and the D/A converter.
It is an object of the present invention to provide a digital audio disc playback device that solves the above problems by inserting and connecting a digital filter device using a processor (DSP).

Means for Solving the Problems The digital audio disk playback device according to the present invention includes a signal processing section that outputs a digital audio signal and a de-emphasis switching signal obtained by playing back a rotating recording disk at a predetermined sampling frequency. , an operation unit that generates and outputs amplitude data or filter coefficients specifying arbitrary equalizer characteristics, and at least a digital audio signal and a de-emphasis switching signal from the signal processing unit are supplied to provide a predetermined de-emphasis characteristic for the digital audio signal. and non-de-emphasis characteristics, and
When amplitude data or filter coefficients are input from the operation unit, a digital filter device that simultaneously imparts a synthesized characteristic of the equalizer characteristics; and D that converts the calculation result data output from the digital filter device into an analog audio signal.
/A converter.

Function: The digital filter device takes in the digital audio signal supplied from the signal processing section every sampling period, and first performs arithmetic processing based on the amplitude data or filter coefficients supplied from the operating means,
An arbitrary equalizer characteristic is given to this f-digital audio signal. Thereafter, the digital filter device performs predetermined arithmetic processing according to the de-emphasis switching signal supplied from the signal processing section, and converts the digital audio signal to which the above-described equalizer characteristics are given predetermined de-emphasis characteristics or non-de-emphasis characteristics. Give characteristics. The calculation result f output from the digital filter device is converted into an analog audio signal by the D/A converter and output.

Embodiment FIG. 1 shows a block system diagram of a first embodiment of a digital audio disc playback apparatus according to the present invention. In the figure, the same components as those in FIG. 15 are given the same reference numerals, and the explanation thereof will be omitted as appropriate. Here, the device of this embodiment has a digital signal processor (DSP) 12L, 12R1 and an interrupt circuit 13L, which constitute the digital filter device, between the signal processing section 11 and the D/A converter 18.

13R1 oscillator 14, input interface circuit 15L,
15R, output memories 16L, 16R, and operation section 17 are inserted and connected. In this embodiment, a dedicated DS is used separately for the output from the signal processing unit 11 and for the parallel digital audio signals of two R channels.
P12L.

1°R! ([1tyr*@ii.'rj ik @W
'r v ``C'v, 6a Because the dispersion is measured for each channel, the same program is applied to each DSP12L,
It can be used for 12R, so it can be used for mask type leads in DSP.
The same chip can be used as the only memory (mask ROM), which has the advantage of being cost effective.

General sea lion 91″717″), characteristics″1, well-known 0 like 4,
: As shown in Fig. 2, in the high frequency band (10.6 kHz to 20 kl-1z) in the audio band, it is about 10. f3 is selected to be attenuated.

Here, in order to realize the above de-emphasis characteristics and desired equalizer characteristics, DSPL 2L.

12R has a configuration as shown in FIG. 3, for example. That is, the input signal from the input interface circuit 151 (15R) is supplied to bandpass filters (BPF) 19+ to 19Tll (where m is an integer of 2 or more), respectively, and is divided into m bands and P waves. Here, the BPFs 19I to 19m each have frequency characteristics as shown in FIG. 4(A), and their signal passbands (frequency fc+ to fc2) are
F19+ is OHz ~ 220Hz, BPF 19
2 is 220H7~600t-1z, BPF 193
is 6001-1z to 1.5 kHz.

BPF194 is 1.5 kHz to 5 kHz, B
The PF195 is selected from 5 kHz to 20 kl-12, etc.

In this way, the input signals divided into m bands by the BPFs 19+ to 19yn are transmitted to the amplitude control units 20+ to 2, respectively.
0TI+.

On the other hand, data specifying a desired equalizer characteristic is input to the operation section 17, and this equalizer characteristic specifying data is supplied to the amplitude data setting section 22 via a terminal 21. The amplitude data setting section 22 generates amplitude data corresponding to desired equalizer characteristics according to the above-mentioned incoming data, and outputs it to the amplitude control sections 20+ to 20Tl+.

The amplitude control units 20+ to 20Tl+ respectively amplify or attenuate the levels of the signals supplied from the BPFs 19+ to 19Tn by a predetermined amount according to the incoming amplitude data, and output the amplified or attenuated signals to the adder 23.

The adder 23 adds the incoming signals, for example in FIG.
B)) A signal having an equalizer characteristic indicated by e is generated and outputted to the de-emphasis filter 21!I and the terminal 25a of the switch circuit 25, respectively.

The de-emphasis filter 24 is a known acyclic digital filter (FIR digital filter) as shown in FIG. 5, and includes delay elements D1 to Dη and multipliers Mo to M.
It is composed of T and an adder A, and its transfer function H(z) is expressed by the following equation.

However, ai does not indicate the multiplication coefficients of the multipliers Mo to Mη.

Further, n is selected to be about 123, for example. Therefore, the de-emphasis filter 24 applies the second equalizer characteristic Ke to the signal supplied from the adder 23.
A de-emphasis characteristic as shown in the figure is further added to generate a signal having a frequency characteristic as shown by Kt in FIG. 4(B), for example, and supplied to the terminal 25b of the switch circuit 25.

The switch circuit 25 is a switch circuit for switching between de-emphasis and non-de-emphasis, and the switching is performed by r of the de-emphasis switching signal bit (or de-emphasis code) from the J: sea urchin terminal 26 described above.
This is done by reading HJ or "L" and checking the flag set. Therefore, during non-de-emphasis, the switch circuit 25 is connected to the terminal 25a side, and the adder 23
A signal to which the equalizer characteristic Ke is applied is outputted via the terminal 25a of the switch circuit 25. On the other hand, when performing de-emphasis, the switch circuit 2
5 is connected to the terminal 25b side, and a signal to which the equalizer characteristic Ke outputted from the de-emphasis filter 24 and the total frequency characteristic Kt of the de-emphasis characteristic is given is outputted via the terminal 25b of the switch circuit 25.

The device of the present invention performs the filtering operation shown in FIG. 3 using a DSP. Here, the configuration of the DSP will be explained with reference to the block system diagram shown in FIG. The illustrated block system in FIG. 6 is a general configuration diagram of the DSP 12L or 12R, and also includes a multiplexer (MUX) and a program counter (PC) in the same figure.

Stack, data memory page pointer (DP)
, an auxiliary register, an auxiliary register pointer (ARP), and a shift circuit are not directly related to the present invention, so their explanation will be omitted, and the configuration of the DSP will be briefly explained below.

DSPs are characterized by lower cost and more extensive multiplication functions than conventional central processing units (CPLJs). In other words, while conventional CPUs perform multiplication using software, DSP has a multiplier 27 internally as hardware, and its calculation speed is approximately 10 to 100 times faster than that of CPJJ. . In addition, the calculation by the FIR digital filter shown in equation (1) above usually requires 20 to 100 steps or more (i.e., n-
20 to 100 or more), and must be performed at a sampling period (1/44.1 kHz = 2311 s), which is impossible with conventional CPUs. On the other hand, the DSP described above, which has a calculation speed approximately 10 to 100 times faster than the CPLJ, can be effectively used as an FIR digital filter.

In FIG. 6, a program read only memory (program ROM) 28 stores in advance a program to be executed by the DSP and data such as the multiplication coefficients aO to aTl and amplitude data. The controller 30 etc. are connected via the program bus 29, and the multiplier 27 is connected via the program bus 29 and data bus 31.
etc. Further, the controller 30 is supplied with a clock signal (CLKIN signal) from the oscillator 14 .

Returning to FIG. 1 again, in this first embodiment, the same signal processing is performed on the L and R channel digital audio signals. This will be explained with reference to the time chart shown in FIG.

In FIG. 1, as shown in FIG. 7 (Δ), the signal processing unit 11 generates a digital audio signal a in which digital audio data of the R channel is distributed alternately at a sampling period.
is supplied to input interface circuits 15L and 15R. At the same time, signals d and e as shown in FIGS. 7(D) and 7(E) are supplied from the signal processing section 11 to the input interface circuits 15L and 15R, respectively. As a result, the input interface circuit 151 handles and outputs only the L channel digital audio signal from the digital audio signal a, while the input interface circuit 15R extracts and outputs only the R channel digital audio signal.

On the other hand, the interrupt circuits 13L and 13R are connected to the DSP 12L and 1
This is a circuit for setting the data transfer timing to 2R. t, that is, DSP12L.

The sampling frequency of the digital audio signal taken into 12R is 44.1 kl-12, and -10,000 SP1
Since the machine cycle of 2m and 12R is approximately 20MH2, the interrupt circuits 13L and 13R interrupt the DSP 121.
DSP12L at a convenient timing for 1'2R
, 12R is importing the data.

The interrupt circuits 13L and 13R are as shown in FIG.
It is composed of a NOR circuit 32 and a D flip 70 tube 33 and 34. Here, a reset signal (R3 signal) generated when a reset switch (not shown) (usually shared with a power switch) is turned on is supplied to one input terminal of the NOR circuit 32 via a terminal 61. be done.

This reset signal is a signal for returning the D flip 70 knob 33 to its initial state. Further, the other input terminal of the NOR circuit 32 is connected to the output signal shown in FIG. 7 (F) or (G) which is output from the controller 30 shown in FIG.
) Data enable signal (DEN signal) 1 as shown in
31g is supplied.

The D flip 70 tube 33 has its data input terminal (D terminal) grounded, and its clear (CL) terminal is supplied with the output signal of the NOR circuit 32. Further, the signal d or e is supplied to the clock (GK) terminal. Therefore, a signal synchronized with the signal d or e is outputted from the Q terminal of the knob 33 of the flip 70 and supplied to the data input terminal (D terminal) of the flip 70 knob 34.

The D flip-flop 34 receives a clock signal (CLK) with a frequency of 5 MHz from the controller 30 to its GK terminal.
OUT signal) is supplied. Therefore, the I10 branch control signal (BIO signal) output from the Q terminal of the D flip-flop 34 to the controller 30 in the DSPs 12m and 12R is synchronized with the above CLK and OUT signals, and an interrupt occurs at the falling time of the I10 branch control signal (BIO signal). On the other hand, DEN
The BIO signal is reset at the falling time of the signal (
t) t5 A L/ < JLI t':l/ri
)・ :Human interface circuit 1
As shown in FIG. 9, 5L and 15R are composed of D flip-flops FI+ to FTu, inverters T+ and I2, and gate circuits G i + to G T 16. here,
Each bit of the 16-bit digital audio signal a supplied from the signal processing section 11 is input to the D flip-flop F.
It is separately supplied to the D terminals of I+ to Fry6.

On the other hand, the signal d or e is inputted to the G terminal of each of the D flip-flops FT+ to FT+6 via the inverter 1. As a result, only the digital audio signal of either the L or R channel is extracted as described above from the Q output terminal of the D flip 70 tube FI+ and the σ output terminal of each of FT2 to FI16, and the digital audio signal of either the L or R channel is extracted as described above.
6 input terminals.

The DEN signal f or q is supplied as a gate signal to the other input terminal of the gate circuits GI+ to GI+6 via an inverter 2. Therefore, the falling time t1. of the DEN signal f. Input interface circuit 15L with 'js etc.
A 1-channel digital audio signal is output from DSP 12L to DSP 12L, and on the other hand, at fall time j3. of DEN signal q. t
7 etc. from input interface circuit 15R to DSPL 2
The digital audio signal of the R channel is output to R.

Note that only the most significant bit (MSB) of the 16-bit digital audio signal is inverted, converted into a two's complement format, and output.

The digital audio signal of the above-mentioned channel is taken into the data random access memory (data RAM) 35 shown in FIG. 6 at time t1, and is stored together with a predetermined address. Thereafter, the multiplier 27 multiplies the digital audio data and the multiplication coefficients ao to aη read from the program ROM 28 as shown in equation (1) above, and the result is subjected to the logical operation shown in FIG. Circuit (AIL
J) 36 and accumulator (800) 37. In this way, after the DSPL 2L takes in the input digital audio data at the falling time t1 of the DEN signal f, it performs the filtering process at each sampling period, and the calculation results are stored in the output data memory 161-
and is written at the falling edge time t6 of the W child signal.

As shown in FIG. 10, the output memory 161- has D flip 70 tubes FL+ to FLI6. FOLI to FOI+6 and inverter T L, + to I L3 and gate circuit GL
+ to GL 16. Here, the above 16
Each bit of the bit operation result data is supplied to the CK terminal, while the controller 3 in the DSPL 2L
A write enable signal (WE multiplied signal h) as shown in FIG. Flip 70 Tsubu FL+~FLI6
from the Q terminal to the D flip 70 knob F.
It is supplied to each D terminal of Cj L + to F OL 16.

On the other hand, an output timing adjustment pulse b as shown in FIG. 7(B) is supplied from the signal processing section 11 to the CK terminal of each of the D flip 70 knobs FOI-+ to FOL 16 via the inverter IL2, and , inverter 11-3
It is supplied to one input terminal of gate circuits G1-1 to G[16 via G1-1 to G[16. After the fall time of the signal S (time ts shown in FIG. 7), the above calculation result data is sent to the D/A from the Q terminal of the D flip-flop GL+ and the extension terminals of GL2 to GLI6 via the gate circuits GL+ to GLI6, respectively. converter 18
Output to. Here, among the above calculation result data, MS
Only B is inverted and converted into two's complement format Glass/A converter 1
8 mode (also called straight binary or offset binary).

In this way, the DSPI 2L takes in data at time t1, outputs the calculation result of the previous data at time t2 immediately after that, takes in the next data at the next time t5, and raises the WE multiplication signal. At downstream time t6, the calculation result of the data taken in at time t1 is written into the output memory 16L, and the calculation result data is outputted to the D/A converter 18 at timing t9, which is synchronized with the subsequent signal a.

On the other hand, the R channel digital audio signal is also processed in the same way as above in the DSPI 2R and output memory 16R. Here, the output 16R is sent to the D flip-flop FR+ to FR16°FOR+ as shown in FIG.
R+6 and inverter IR+~rR3 and gate circuit G
Consists of R+ to G R16.

Further, the WE signal 1 which falls at times t4 and +8 as shown in FIG. A signal with a characteristic opposite to that of D flip-flop FOR via inverter IR2 is
It is supplied to the CK terminals of + to FOR+6, and is also supplied to one input terminal of gate circuits GR+ to GR16 via an inverter IR3. Furthermore, the calculation result data of the R channel from the DSP12R is supplied to the D terminals of the D flip-flops FR+ to FR16, respectively.

Since the processing of the calculation result data of the R channel is similar to the processing of the calculation result data of the 1-channel, a detailed explanation thereof will be omitted and a brief description of the seventh drawing will be given. That is, the DSPL 2R takes in data at time t3, outputs the calculation result of the previous data at time t4 immediately after that, takes in the next data at the next time t7, and then outputs the calculation result of the previous data at time t4.
At step 8, the calculation result of the data taken in at the time t3 is output. At the subsequent time tLD, the above calculation result data is output to the memory 16. The gate circuit GR+ in R
+6 is output to the D/A converter 18. In this case as well, of course, only the MSB of the R channel calculation result data is inverted and output and converted into the direct format.

On the other hand, the DSPs 12L and 12R receive a de-emphasis switching signal C as shown in FIG. 8(C) from the signal processing section 11.
is supplied, and this signal C is taken in immediately after the data is taken in. Here, when signal C is high level, D
As described above, the SPs 12L and 12R perform calculation processing for equalizer characteristics and de-emphasis, and when the -power signal C is at a low level, calculation processing for only the equalizer characteristics is performed and de-emphasis calculation processing is not performed.

In this way, the characteristic Ke or 1<t is given,
Further, as shown in FIG. 8LJ), a signal j in which the calculation result data of the L and R channels are arranged alternately is outputted from the output memories 16L and 16R to the D/A converter 18. Note that this signal j is delayed by two sampling periods from the original digital audio signal a output from the signal processing section 11, as shown in FIGS. 7(A) and 7(J).

Next, the D/A converter 18 is supplied with the signal, and converts the incoming and R2 channel calculation result data into analog signals, and separately outputs the L2 data for each channel.
It is output to output terminals 38 and 39 via PF7 and PF8. The above LPFs 7 and 8 are respectively antialias filters,
This is provided to eliminate aliasing noise.

FIG. 11 shows a block system diagram of a second embodiment of the reproducing apparatus of the present invention. In the figure, the same components as in FIGS. 1 and 15 are denoted by the same reference numerals, and their explanations will be omitted. This second
In the embodiment, a negative DSP 40 is used for a 2-channel digital audio signal, and in order to perform so-called time division processing, the interrupt signal (corresponding to the BIO signal) generated and output from the interrupt circuit 41 is as follows. This is performed twice for each R channel during one sampling period. Furthermore, since the digital audio signal output from the signal processing section 42 is not in parallel as described above but in serial format, a serial-to-parallel converter (S/P) is used to convert the digital audio signal into a parallel signal. converter)
43 and a parallel/serial converter (P/S
strange*! ri44. ! ''Fr * L/ 'C(1' 8
Z′! ″1Special 104・.

Here, the DSP 40 is composed of a digital filter 45.4.6 and a filter coefficient supply section 47 as shown in FIG. The digital filter 451 is a smooth filter that realizes free transfer characteristics by changing filter coefficients as disclosed in Japanese Patent Application Laid-Open No. 59-52912 (Japanese Patent Application No. 57-163727). calculation means for calculating a time-series impulse response based on predetermined phase and amplitude information;
This time-series impulse response is used as a filter coefficient,
It is composed of a real-time processing digital filter that convolves the filter coefficients and the input digital signal.

On the other hand, the digital filter 46 is a digital filter that can switch between de-emphasis characteristics and non-de-emphasis characteristics by changing filter coefficients, and during de-emphasis, it imparts de-emphasis characteristics as shown in FIG. 2 above to the input signal. However, during non-de-emphasis, a non-de-emphasis characteristic as shown by Kf in FIG. 13 is given to the input signal. In this case, the cutoff frequency is, for example, approximately 20kHz.

Here, a filter coefficient corresponding to a desired equalizer characteristic is outputted from an operation section 48 configured with, for example, a CPLJ and a ROM with built-in filter coefficients, and is supplied to a filter coefficient supply section 47 via a terminal 49. The filter coefficient supply unit 47 corresponds to a part of the data RAM 35 in the DSP, and supplies the incoming filter coefficients to digital filters 45 and 46, respectively.

In this way, the input signal is first passed through the digital filter 45 to have an equalizer characteristic K as shown in FIG.
After e/ is given, the digital filter 46 gives the de-emphasis characteristic or non-de-emphasis characteristic Kf shown in FIG.
A signal is generated and output.

On the other hand, the high-speed ROM 50 external to the DSP 40 contains the de-emphasis program (referred to as program A) and the non-de-emphasis program (referred to as program B).

) and an equalizer program (referred to as program C) are stored. Therefore, switching between de-emphasis and non-de-emphasis is achieved by instantaneously switching between the programs A and B in accordance with the de-emphasis switching code included in the input data supplied to the DSP 40. For this reason,
Compared to conventional de-emphasis and non-de-emphasis switching performed on analog signals, which involves a time delay in the time constant due to OR, this second embodiment has no time delay, so it can be used, for example, in the middle of a song. can also perform the above switching. Note that since the program is created so that the data in the data RAM 35 in the DSP 40 can be shared, there is no loss of output data during the above switching.

Next, the operation of the second embodiment will be explained with reference to the signal waveform diagram shown in FIG. In FIG. 11, the signal processing unit 4
2 outputs a data transfer start pulse k that rises at time 1 ++ as shown in FIG. 14(A) to the interrupt circuit 41, and at the same time outputs 16-bit digital audio data m as shown in FIG. 14(C). It is sent serially to the S/'P converter 43.

Note that the data m shown in FIG. 14(C') is only the data of one of the R2 channels, and in fact, the digital audio data of the other channel is the blank part (i.e., the time t12~t1
5), and there is also a data transfer start pulse for the other channel.

The interrupt circuit 41 is the interrupt circuit 13L.

Similar to 13R, this is a circuit for setting the data transfer timing to the DSP 40, and uses the data transfer start pulse k and the clock signal (
This corresponds to the CLKOLIT signal. ) and outputs an interrupt signal (corresponding to the BIO signal).

On the other hand, the S/P converter 43 is supplied with the serial digital audio data m and the pit clock signal e as shown in FIG.
The DEN signal 0 as shown in FIG. 14(E) is supplied from SP40. Therefore, the S/P converter 43 at time t
Each bit of the serial digital audio data m transmitted between ll and t12 is latched and captured when the clock signal is insufficient, and the subsequent falling time t of the DEN signal 0 is detected.
, +a are sent to the DSP 40 in parallel for each channel.

The DSP 40 performs de-emphasis or non-de-emphasis on the input data by performing the above-described predetermined arithmetic processing, and sends the resultant data to the P/S converter 44 .

The clock signal 2 is supplied to the P/S converter 44,
On the other hand, at the falling time t14 of the WE multiplication signal, which is supplied from the DSP 40 and falls at time t14 as shown in FIG. The data is converted into data and sent to the timing adjustment shift register 51. The timing adjustment shift register 51 is supplied with the clock signal P, and in response to this, the calculation result data is transferred to D.
/A converter 52.

The 0/A converter 52 uses a two's complement format as its calculation method, and the signal processing section 42 calculates the data as shown in FIG.
The output timing adjustment pulse n as shown in D) is supplied, and the input calculation result data is integrated and converted into an analog signal. Output terminal 53.54 through
Output to.

In this way, de-emphasized and analog audio signals of each R channel can be obtained from the output terminals 53 and 514.

Note that the digital audio disc is not limited to a compact disc (CD), so the player unit 1 may be a player unit for other digital audio discs, and the recorded digital audio signal is always pre-emphasized. Of course, this can also be applied to a playback device that always performs de-emphasis.

In addition, configuration methods or calculation formulas for realizing de-emphasis and non-de-emphasis may be other than those described above, and are not limited to the embodiments.

Effects of the Invention As described above, the present invention has the following features.

■ A total frequency characteristic consisting of the desired equalizer characteristic and a predetermined de-emphasis characteristic based on the amplitude data or filter coefficients supplied from the operation unit, or a total frequency characteristic consisting of the above-mentioned desired equalizer characteristic and a predetermined non-de-emphasis characteristic. Frequency characteristics can be imparted to digital audio signals.

■ Switching between de-emphasis and non-de-emphasis is carried out by reading the de-emphasis switching signal bit of the input digital signal every sampling period and instantaneously switching the program, making the switching control described above easy and easy to use when switching. There is no deviation.

■ The above switching can be performed even in the middle of a song. For example, depending on the spectral distribution of the song, pre-emphasis can be effectively selectively performed when cutting a disc, increasing the transmission efficiency by expanding the dynamic range of the transmission path. Out.

(2) Since an FIR filter with perfect linear phase characteristics is used as the digital filter, phase distortion can be removed not only during de-emphasis but also during non-de-emphasis.

(2) Deterioration of the S/N ratio due to spurious noise caused by a digital signal flying into the conventional de-emphasis circuit serving as the analog filter is eliminated.

(2) Since a digital signal processor (DSP) is used to provide de-emphasis characteristics and equalizer characteristics, system reliability can be improved and costs can be reduced.

■ From the above, it is possible to realize a digital audio disc playback device with good reproducibility and no deterioration in sound quality.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the first embodiment of the reproducing device of the present invention, FIG. 2 is a de-emphasis characteristic diagram, and FIG.
FIG. 4(A) is a block system diagram showing the configuration of an embodiment of the DSP in the illustrated program system. (B) is a diagram showing the frequency characteristics of the bandpass filter of the block system shown in FIG. 3 and the overall frequency characteristics of the entire block system shown in FIG. 3, FIG. 5 is a block system diagram showing the configuration of the FIR digital filter, and FIG. The figure is a 10-block system diagram showing the general configuration of a DSP, FIG. 7 is a signal waveform diagram for explaining the operation of the block system shown in FIG. 1, and FIGS.
FIG. 10 is a detailed circuit diagram showing an example of the interrupt circuit and input interface circuit in the illustrated block system; FIG. 10 is a detailed circuit diagram showing an example of the output memory in the block system illustrated in FIG. 1; FIG. A block system diagram showing a second embodiment of the playback device; FIG. 12 is a block system diagram showing the configuration of an embodiment of the DSP in the block system shown in FIG. 11;
FIG. 13 shows de-emphasis characteristics in the second embodiment,
FIG. 14 is a signal waveform diagram for explaining the operation of the block system shown in FIG. 1, and FIG. 15 is a block system diagram showing an example of a conventional compact disc playback device. 1... Player section, 7, 8... Low pass filter (LP
F), 11.42... signal processing section, 12L, 12R. 40...Digital signal processor (DSP)
), 13L, 13R, 41... interrupt circuit, 14.
...Oscillator, 15L, 15R...Input interface circuit, 16L, 16R...Output memory, 17°48.
...Operation unit, 18.52...D/A converter, 191-
19Tn...bandpass filter (BPF), 20+ ~2
0m... Amplitude control unit, 21... Equalizer characteristic specification data input terminal, 22... Amplitude data setting unit, 23°A... Adder, 24... De-emphasis filter, 25... Switch Circuit, 26... De-emphasis switching signal input terminal, 27, Mo = MTl...
- Multiplier, 28... Program ROM, 29... Program bus, 30... Controller, 31... Data bus, 32... NOR circuit, 33.34. FT+
~FIf6, FL1~F+16. FOLI〜FO
L+6. FR+~FRI6゜FOR+-FOR+6...
・D flip 70 knob, 35...Data RAM, 36
...Logic operation circuit (ALU), 37...Accumulator (A(,C), 38.53...Left channel analog audio signal output terminal, 39°54...Right channel analog audio signal output terminal, 43...-serial/parallel (S/P) converter, 44... parallel/serial (P/S) converter, 45.46... digital filter, 47... filter coefficient supply unit, 49... ...Filter coefficient input terminal, 50...ROM, 51...Shift register for timing adjustment, 61...Reset signal input terminal, D+~Dη...R extension element, GI+~GI+s
, GI+~GLI61GR+~GR16... gate circuit, I+, 12, If-+~ILa, TR
+~IR3...Inverter.

Claims (1)

[Claims] A digital audio disc that reproduces a previously recorded signal on a rotating recording disk in which a digital audio signal obtained by digitally modulating an analog audio signal is recorded together with a de-emphasis switching signal indicating whether or not a pre-emphasis characteristic has been added. The reproducing device includes a signal processing unit that outputs the digital audio signal obtained by reproducing the rotating recording disk and the de-emphasis switching signal at a predetermined sampling frequency, and amplitude data or filter coefficients that specify arbitrary equalizer characteristics. An operating section that generates and outputs, and is supplied with at least the digital audio signal and the de-emphasis switching signal from the signal processing section, and applies either a predetermined de-emphasis characteristic or a non-de-emphasis characteristic to the digital audio signal. and a digital filter device that simultaneously imparts a synthesized characteristic of the equalizer characteristic when the amplitude data or filter coefficient is inputted from the operation unit, and converts the operation result data output from the digital filter device into an analog audio signal. Do D/
A digital audio disc playback device comprising: an A converter.