JPS6275850A - Control system for execution of microinstruction - Google Patents

Abstract

PURPOSE:To minimize the generation of queuing cycles for the information of page faults by producing a queuing state for the execution of a microinstruction according to whether a program under the execution or a segment to be written undergoes a dynamic paging action or not. CONSTITUTION:A paging system instruction bit 25 in a program status word 24 supplies a signal 29 to an AND gate 28 to show whether a page fault may possibly produced or not. The gate 28 delivers the signal 30 of level '1' in case the signal 29 and a gate writing request signal 27 given from a memory access control circuit 26 are equal to '1'. A microinstruction execution queuing generating circuit 31 produces the queuing for the execution of a microinstruction following the data writing request when the signal 30 is equal to '1'. While the generation of the microinstruction queuing is inhibited even with a data writing request in case the signal 30 is equal to '0' since there is no possibility for generation of a page fault.

Description

[Detailed Description of the Invention] Techniques of Akira (Field H) This invention relates to a virtual storage system that applies both dynamic paging and static page paging methods, and in particular ( J-'11] Concerning command execution υ control system during data writing.

[Technical background of the invention and its problems] Using a physical structure consisting of a relatively small main storage device and a large-capacity external storage device, programs can use a large-capacity device that they can use as they wish. There is a virtual memory 5 stem that extends the logical structure consisting of an address space. In this type of virtual storage system, as shown in FIG.
1 is generally provided in a main memory device (fvt role 1Li) 12 and a memory control unit (MCU) 13 for formation.

When the address translation device M11 determines that the target page does not exist in the main memory in the above address translation 1, it notifies the CPU 14 that a page fault 1 has occurred.

Now, since the CF) U14 does not need to have data when making an N write request, unlike when making a read request, it is possible to proceed to the execution of the next microinstruction. However, with this method, if a page fault occurs in response to a write request, the state of c p v 14 changes from the state at the time of the seat request, making it difficult to re-execute the instruction after page-in processing. becomes.

Conventionally, when a page fault occurs, the microinstruction following the write request is not executed in order to save the internal state of the CPU 14 at that time and enable re-execution of the instruction after page-in processing. , the micro-instruction real 11 Samurai generation circuit 15 waits for a response (normal completion or page fault notification indicating the occurrence of a page fault) from the memory control unit 13 and resumes instruction execution.
was provided within the CPU 14. However, in the method using the microinstruction execution master generation circuit 15, a cycle is always generated for each refining request, so that CP tJ 1
There was a problem that the chirality performance of No. 4 deteriorated.

On the other hand, a method is also known in which the internal state of the CP port at the time of the access request is saved and the page fault is generated. However, this method requires complicated processing, and
There was a vacancy to accommodate the increase in hardware science within the PU.

[Purpose of the Invention] This invention was made in view of the above circumstances, and its purpose is to minimize the number of cycles required for page fault notifications, which were required at the time of a data transfer request, while having an intermediate configuration. The object of the present invention is to provide a microinstruction execution control system that can limit the number of microinstructions.

[Summary of the Invention J In this invention, a holding unit is provided that holds first information indicating whether or not dynamic paging is performed for each job or task whose execution is managed by the operating system, or for each segment. . When the program status word or segment changes, the first status word held in the holding means corresponding to the relevant job, task, or segment
The information is set as second information in the program status word or another holding means different from the above holding means.

The second information indicates whether the program being executed or the corresponding segment is subject to dynamic paging,
It is guided to a 0 signal generation means which controls the store request signal outputted from the memory control circuit. The control 2D signal generating means generates a control signal indicating that the write request is a write request that may cause a page fault, based on the second information and the internal request signal. This control signal is directed to executive control means. The execution controller control means controls 11 the execution wait of the microinstruction in response to the control signal.

That is, this invention was made by paying attention to the fact that there is a possibility of page faults occurring only in the dynamic paging method. A wait for execution of a microinstruction (that is, a page fault notification wait cycle) is generated depending on whether or not pair 9 is satisfied.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

Note that this embodiment is applied to a virtual storage system that applies both paging methods, dynamic paging and static paging. The above dynamic paging method and static paging method involve rollout of pages between the main storage device and external storage bag in a virtual storage system.
This is known as the roll-in method. In the dynamic paging method, when a job is executed, whether information required by the job exists in the main memory is determined at the time of actually accessing the information. If the required information does not exist in main memory, a page fall occurs, and at that point, unnecessary pages are rolled out (page-out), necessary pages are rolled in (page-in), and the job is executed. This is a continuation of the 11th episode. on the other hand,
In the static paging method, when running a job consisting of
The information required for the job (task) is placed in the main memory, and the job is executed after creating an environment free of page faults.

FIG. 1(a) is a block diagram showing an embodiment of the present invention, and 2) is an operating system (hereinafter referred to as
This is a segment management table (hereinafter simply referred to as a management table) that is prepared for each job (or task) under the management of the O8. The management table 2) has entries for the number of segments allocated to the relevant job. Each entry in the management table 2) includes base information (base address) indicating the corresponding segment area, well-known segment management information for memory access such as the execution ring number, and information about jobs that use the corresponding segment being executed by dynamic paging. A first paging method instruction bit 22 is provided to indicate whether paging is performed using static paging or static paging.

That is, in this embodiment, the job (
The applicable paging method is assigned to each (or task). 23 is a management table directory indicating the correspondence between jobs and management table 2). Each entry in the management table directory 23 includes information such as a management table pointer that specifies the management table 2) corresponding to the job in question and the number of entries in the table 2) (i.e., Seramen 1 - Loss assigned to the job in question). It has been described. The management table 2) and the management table directory 23 are placed on a main memory (not shown).

24 is a program status word (hereinafter referred to as PSW) indicating the status of the program currently being executed. The PSW 24 has a second paging method indicator 25 that indicates whether the program being executed is subject to dynamic paging. 2G is a memory access control circuit that outputs a data write request signal 2) when a data write request is made to the main memory, and 28 is, for example, an AND gate operated by two people. One input of the AND gate 28 has PSW2.
The paging method instruction 25 in 4 is supplied as a signal 29, and the data write request signal 27 from the memory access control circuit 26 is supplied to the other input of the antagonist 28.
is supplied. Signal 3 output from AND gate 28
0 is supplied to a microinstruction execution wait generation circuit 31 that controls the execution of microinstructions. The PSW 24, the memory access control circuit 26, the AND gate 28, and the execution controller generation circuit 31 are provided in a CPU (not shown).

Next, the operation of the configuration shown in FIG. 1(a) will be explained.

First, a software management method related to this embodiment will be explained. In this embodiment, the O8 generates, for each job (or task) whose execution is managed, a management table 2) for managing segments to be allocated to the job. At this time, the O8 determines whether each job is to be executed by dynamic paging or static paging, and the assignment is made using the paging method instruction pin 1 at each end of the management table 2). -22 will be reflected.

Here, the paging method instruction bit 22 is 1'.
, indicates that the job to which the corresponding segment is assigned will be the target of dynamic paging, and indicates that the job to which the corresponding segment is assigned will be the target of static paging.
When the PSW 24 is switched, the paging method instruction bit 22 of the entry in the management table 2) corresponding to the segment allocated to the program to be newly executed is used as the paging method instruction bit 25 in the new PSW 24.

In this embodiment, for example, a user job consisting of static paging is performed, and a 1.10 (input/output) job under O8 called by this user job performs dynamic paging. Manages the running program [PSW2 showing the status of 1 gram] +
Specify the paging method in this case.
~25) actually reflects the job paging method including the program RL (in the program). The paging method instruction bit 25 becomes II 1 N when the program in ff? is a dynamic paging counterpart. , 11011 if the target is static paging.

The paging method instruction pin (-25) in the PSW 24 is supplied to the AND gate 28 as a signal 29 indicating whether or not the possibility of a page fault occurring is 4 (when "]"). , a data write request signal 27 output from the memory access control circuit 2G is also supplied.The data write request signal 27 becomes '1' (valid) when the executed microinstruction is a data write request. , and the signals 27 and 29, and if both signals are '1'', that is, if the data write request signal 27 indicates a data write request and the signal 29 indicates the possibility of a page fault occurring. , logic "1" indicating that a page fault occurs during a data write request.

Outputs the message @30. This signal 30 is supplied to a microinstruction generation circuit 31.

The microinstruction execution wait generation circuit 31
If the signal 30 output from 28 is logic 1'', there is a possibility that a page fault will occur at the time of a data write request.
In order to save the internal state of the CPU at that point in A and re-execute the instruction after the page-in processing, S: In order to make it possible, the execution wait for the microinstruction following the data 1 request is set to F, and the execution wait for the microinstruction is also executed. The generation circuit 31 resumes instruction execution upon receiving a response from the unillustrated menu (not shown) to the roll unit 13 (page fall 1 notification indicating normal completion or page fault occurrence).

On the other hand, the signal 30 from the AND gate 28 is logical.
In the case of "0", there is no possibility of page fall 1- occurring, so the microinstruction execution wait generating circuit 31 refrains from generating a microinstruction execution wait even when a data write request is made.

That is, in this embodiment, even if a data write request is made while a program is being executed, if the job to which the program belongs is not executed by dynamic paging, no microinstruction is queued for execution.

Next, an embodiment of this Bummei no Haku will be described with reference to FIG. 1(b). Note that the same parts as in FIG. 1<a) are given the same reference numerals.

In FIG. 1(b), 41 is a management table (segment management table) similar to the management table 2) shown in FIG. 1(a). However, the management team 11 has a first paging method instruction bit 42 in each entry indicating whether the corresponding segment becomes a dynamic paging pair or a static paging target. Tube 1! ! Table 2) is different. That is, in this embodiment, the paging method applied to each segment pipe, which is the management result of O8, is υj
This differs from the described embodiment in which the paging method υj is applied to each job whose execution is managed by the O8. Note that 43 is a management table directory similar to the management table library 1-23 in FIG. 1(a).

Reference numeral 44 denotes a segment display register that holds segment management information of the segment that is the target of the currently executed memory access. The contents of the segment display register 44 are as follows:
The information of the corresponding entry in the management table 41 is updated every time the segment is switched. Ceramen 1 to management information have a second paging method instruction bit 45 indicating whether the corresponding segment is a target of dynamic paging. 48 is a two-man powered AND gate. The paging method instruction bit 45 of the segment display register 44 is supplied as a signal 49 to one input of the AND gate 48, and the memory access sub-circuit 2 is supplied to the other input of the AND gate 48.
A data embedding request signal 27 from 6 is supplied.

A signal 50 output from the AND gate 48 is supplied to a microinstruction execution wait generation circuit 31. The segment display register 44 and the computer game 1/48 are provided in the CPU (not shown) together with the memory access control circuit 26 and the microinstruction processor generation circuit 31.

Next, the operation of the configuration shown in FIG. 1(b>) will be explained.

First, a software management method related to this embodiment will be explained. In this embodiment, when the O8 generates the management table 41, it assigns to each segment to be managed whether it is a segment that is subject to the dynamic paging method or a segment that is subject to the static paging method. The allocation reflects the status in the paging method instruction bit 42 of each entry in the management table 41.

Here, the paging method indicator 1-42 is 1'',
Indicates that the corresponding segment is subject to dynamic paging, and "0'' indicates that it is subject to static paging. When switching segments, the information in the entry in management table 2) corresponding to the new segment is held in the segment display register 44 as segment management information, so that the paging method instruction bit 45 of the same register 44 is updated to the paging method instruction bit 112 in the entry information.Therefore, the paging method instruction bit 45 is 1 if the target segment of the currently executing memory access is subject to dynamic paging
'', and o'° if the same segment is subject to static paging.

The paging method instruction bit 45 in the segment display register 44 is supplied to the AND gate 48 as a signal 49 indicating whether or not there is a possibility that a page fault will occur (when it is "1"). And Gate 48 has
A data write request signal 27 output from the memory access control circuit 26 is also supplied. Andgoo 1-48 are
When the signals 27 and 49 are both "1", a signal @50 of logic "1" indicating that a page fault occurs at the time of a data embedding request is output. This signal 50 is supplied to the R main circuit 31 for microinstruction execution. If the signal 50 output from the AND gate 48 is logic "1", the microinstruction execution wait generation circuit 31 detects that there is a possibility that a page fault will occur during a data write request.
Execution of subsequent microinstructions is made to wait until a response from a memory control unit (not shown) arrives.

On the other hand, the signal 50 from the AND gate 48 is logic "
In the case of O11, since there is no possibility of a page fault occurring, the microinstruction execution wait generating circuit 31 refrains from generating a microinstruction execution wait.

That is, in this embodiment, even if a data write request is made during program execution, no microinstruction execution wait occurs unless the segment in which the data to be written falls is subject to dynamic paging.

Although the cache method is not described in the above embodiment, the present invention can also be applied to a virtual storage system having a store-through type cache memory inside the CPIJ, for example. In this case, let the AND gate 28.48 be, for example, three people, and
) In addition to the input signal I], a signal indicating that there is no cache hit is added.

Alternatively, execution of the microinstruction may be held according to the conditions in the above embodiment only when the cache is not hit. By doing this, when the cache is flushed, there is no need to wait for the execution of microinstructions even though there is no possibility of a page fault occurring (4).
Become, book.

[Effects of the Invention] (More details) According to this invention, it is possible to reduce the dynamic paging target or static paging target by reducing the operation ratio 6j under the management of O8. , set static basing to row 1 to subtract dynamic paging
;ni) Tei・2. Deaf', 1'l' is also the page number 4-l which was necessary when inputting f-ta.
1 can be reduced to a minimum by attaching the bar 17 in the cylinder to +rjlλ, and the system performance can be improved.

[Brief explanation of drawings]

Figure 1 (a) is a block diagram showing an embodiment of the second invention, Figure 1 (b) is a block diagram showing an embodiment of the invention, and Figure 2 is a general virtual diagram. It is a block diagram showing a storage system. 2), 41... Management table (segment management table), 22. 42... 1st page]/G method instruction bit, 24... psw <Program status word ), 25°45... To second paging method instruction pin 1, 26... Memory P access control circuit, 28.4
8...And gate, 31...Nicro instruction execution wait generation circuit, 44...Segment '''/[・Display register. Applicant's agent Patent attorney Takeshi Suzue 1 Figure 2

Claims (4)

[Claims] (1) In a virtual storage system that applies both dynamic paging and static paging, the operating system provides first information indicating whether each job or task whose execution is managed is subject to dynamic paging. A program status word having a holding means for holding and second information indicating whether or not the program being executed is subject to dynamic paging, and each time the word is switched, the second information is changed to the corresponding job or A write request that may cause a page fault due to the program status word updated to the first information corresponding to the task, at least the second information in the program status word, and a write request signal output from the memory control circuit. A control signal generation means for generating a control signal indicating that the microinstruction is executed, and an execution wait control means for controlling the execution wait of the microinstruction in response to the control signal generated by the control signal generation means. A microinstruction execution control method. (2) The control signal generating means generates the control signal based on the second information in the program status word, a write request signal output from the memory control circuit, and a signal indicating the presence or absence of a cache hit. A microinstruction execution control system according to claim 1. (3) In a virtual memory system that applies both dynamic paging and static paging, first information indicating whether each segment managed by the operating system is subject to dynamic paging is retained. a first holding unit; and second information indicating whether or not the segment to be processed is a target of dynamic paging, the first holding unit corresponding to the segment each time the segment is switched.
a second holding means for holding second information to be updated;
the second holding means held by at least the second holding means;
control signal generation means for generating a control signal indicating that the write request is a write request that may cause a page fault based on the write request signal output from the information and memory control circuit; and the control signal generated by the control signal generation means. 1. A microinstruction execution control method, comprising: execution wait control means for controlling execution wait of a microinstruction according to a signal. (4) The control signal generating means generates the control signal based on the second information held in the second holding means, a write request signal output from the memory control circuit, and a signal indicating the presence or absence of a cache hit. A microinstruction execution control system according to claim 3, characterized in that: