JPS627264A - Picture processor - Google Patents

Abstract

PURPOSE:To decrease the amount of processing on the unit of one picture element, to speed the processing and to simplify the hardwares by generating a bit selecting pattern to correlate an input picture and an output picture after enlarging/contracting processing based on the magnification of the enlarging and the contraction. CONSTITUTION:A picture to be converted which is inputted through a picture inputting part 1 is inputted to a bit selecting pattern generating part 6 via an image memory 2 and an enlarging/contracting processing part 3. The part 6 generates, based on the enlarging/contracting ratio, the bit pattern to correlate the input picture and the output picture after the enlarging/contraction, and outputs it to a bit selecting pattern register 7. The part 3 rotates the register 7 for each of the input picture elements, and if a carry results from it, outputs it as one output picture element, but does nothing if the carry does not result. That means that the enlarging/contracting processing is executed only by a shifting operation, so the amount of the processing for one picture element is reduced, and the processing is speedified and further, the circuit is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image processing apparatus that freely edits an input image and enlarges or reduces the image for display.

BACKGROUND OF THE INVENTION Conventional image enlargement/reduction processing devices use a digital differential analyzer to perform enlargement/reduction processing on images input from an image input unit (Shukami, Shimazaki, Hirokami,
Suzuki, ``Binary image processor LS aimed at the office processing field''
I”, “Nikkei Electronics J, December 1983
9th issue, pp.

195-216. ).

This converts the coordinate 1 of the input screen A to the corresponding coordinate 1 of the output screen B by sequentially adding the enlargement/reduction magnification to the starting point coordinates of the output screen B. Figure 4 (a), (b
), in order to obtain the output screen B corresponding to the input screen A during reduction, the residual R is given the enlargement/reduction magnification m/n (4th In Figure 3), S/a) is added, and if a carry occurs as a result of the addition, output the contents of coordinate i on input screen A to coordinate j on output screen B, move j by 1 pixel, and check if there is no carry. do nothing. The relationship between the coordinate i of the input screen A and the output screen B is as shown in the following equation.

j=c-.(i-1)+RO]+1 However, [X] is the maximum integer not exceeding X, and RO represents the initial value of the residual.

At the time of enlargement, screen A is the output screen and screen B is the input screen, so it is the same as in the case of reduction, except that the correspondence between coordinates l and j is reversed.

Problems to be Solved by the Invention In the above-mentioned enlargement/reduction processing method, addresses and residuals are calculated for each pixel of the input image, so processing speed is a problem for large amounts of image data. becomes. Furthermore, when considering hardware, since the basic processing unit is one pixel, the circuit becomes complicated if processing is performed in units of multiple pixels.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention generates a bit selection pattern that associates an input image with an output image after enlargement/reduction processing based on a prespecified enlargement/reduction ratio. Then, by rotating and referring to the bit select pattern register for the input image that is the output of the image input unit to obtain the output image, the amount of processing per pixel is reduced and the processing content is simplified. It is something that becomes.

Function The present invention aims to speed up the enlargement/reduction process and flexibly respond to the need for hardware by reducing the amount of processing per pixel and simplifying the processing content using the above-mentioned technical means. be.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of an embodiment of an image processing apparatus according to the present invention. Reference numeral 1 denotes an image input unit which inputs an image to be converted. An input image, which is the output of the image input section 1, is stored in the image memory 2. A bit select pattern generation unit 6 generates a bit select pattern that associates the input image with the output image after the enlargement/reduction conversion, and stores it in the bit select pattern register 7. The enlargement/reduction processing section 3 obtains the output image while referring to the bit select pattern register 7, stores it in the video memo I74, and displays it on the display section 6.

In the image processing device configured as described above, magnification and
A case where the reduction conversion magnification is 13/1e will be explained.

The second diagram is a diagram explaining the bit selection pattern in detail.
It is a diagram. The bit select pattern is generated by using a digital differential analyzer in the bit select pattern generation unit 6 to find the coordinates of pixels in the input image that correspond to the coordinates of each pixel in the output image, and by taking the difference between adjacent pixels in the output image. It is generated. The bit selection pattern is 16 bits long, and when reduced, each pixel of the input image and
When enlarging, there is a one-to-one correspondence with each pixel of the output image. In the case of reduction, each pixel of the input image corresponding to "1" in the bit select pattern is selected, and the pixels corresponding to '0' are thinned out.In the case of enlargement, each pixel of the input image corresponding to "1" in the bit selection pattern is selected It is the same as in the case of reduction, except that the correspondence between pixels and each pixel of the output image is reversed.The hit select pattern generated by the bit select pattern generation unit 6 is stored in the 16-bit bit select pattern register 7. Using the bit select pattern described above, the enlargement/reduction processing unit 3 rotates the bit select pattern register 7 for each pixel of the input image that is the output of the image input unit 1, as shown in FIG. If a carry occurs as a result, it is output as one pixel of the output image.If no carry occurs, nothing is done.In other words, since the enlargement/reduction process is performed only by shift operations, It becomes easy to reduce the amount of processing per pixel and simplify the circuit.

Effects of the Invention According to the present invention, a bit selection pattern is generated that associates an input image with an output image after enlargement/reduction processing based on the enlargement/reduction magnification, and the bit selection pattern is rotated with respect to the input image that is the output of the image input section. A stone that reduces the geographical amount of each pixel by performing enlargement/reduction processing only by operation, increasing speed and making it easy to make hardware.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an image processing device according to an embodiment of the present invention, Fig. 2 is an explanatory diagram of a bit select pattern, and Fig. 3 is a diagram showing the flow of enlargement/reduction processing when using the bit select pattern. , FIG. 4 is a diagram illustrating a conventional enlargement/reduction processing method. 1... Image input section, 2... Image memory, 3... Enlargement/reduction processing section, 4...
・Video memory, 5...Display section, 6...
-Bit select pattern generation unit, 7...Bit select pattern register. Name of agent: Patent attorney Toshio Nakao and 1 other person - ← Shi-no-ha” Ward Figure 3

Claims (1)

[Claims] an image input unit that inputs an image to be processed; a bit select pattern generation unit that generates a bit select pattern that associates an input image that is an output of the image input unit with an output image after enlargement/reduction processing; a bit select pattern register that stores the pattern;
An image processing apparatus comprising: an enlargement/reduction processing section that receives the input image and obtains the output image while referring to the bit select pattern register.