JPS6271689U

JPS6271689U -

Info

Publication number: JPS6271689U
Application number: JP16377885U
Authority: JP
Priority date: 1985-10-25
Filing date: 1985-10-25
Publication date: 1987-05-07

Description

[Brief explanation of the drawing]

第１図は本考案の第一実施例を示すブロツク構
成図。第２図は第一実施例の具体的回路の一例を
示す回路図。第３図は本考案の第二実施例を示す
ブロツク構成図。第４図は第二実施例の具体的回
路の一例を示す回路図。１―１，１―２，１―３，１―４……，１―ｎ
，１１―１，１１―２，１１―３，１１―４，…
…，１１―ｎ−１，１１―ｎ……状態表示信号、
２，１２―１，１２―２，……，１２―ｋ……選
択回路、３，１３―１，１３―２，……，１３―
ｋ……選択表示信号、４，１４……選択信号発生
回路、５―１，５―２，……，５―ｍ，１５……
選択信号、６，１６……表示盤、７―１，７―２
，７―３，７―４，……，７―ｎ，１７―１，１
７―２，１７―３，１７―４，……，１７―ｎ…
…駆動解路、８―１，８―２，８―３，８―４，
……，８―ｎ，１８―１，１８―２，１８―３，
１８―４，……，１８―ｎ……表示部、９―１，
９―２，９―３，９―４，……，９―ｎ，１９―
１，１９―２，１９―３，１９―４……，１９―
ｎ……駆動信号、１０，２０―１，２０―２，…
…２０―ｋ……解読回路、Ｇ_２１〜Ｇ_２４，Ｇ_７
１〜Ｇ_７４，Ｇ_１０１〜Ｇ_１０３，Ｇ_１２１〜Ｇ
_１２４，Ｇ_２０１〜Ｇ_２０４……アンド回路、Ｇ
_１０４，Ｇ_１２２，Ｇ_１２４，Ｇ_２０２，Ｇ_２０
４……オア回路、Ｉ_１〜Ｉ_１０……インバータ。 FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of a specific circuit of the first embodiment. FIG. 3 is a block diagram showing a second embodiment of the present invention. FIG. 4 is a circuit diagram showing an example of a specific circuit of the second embodiment. 1-1, 1-2, 1-3, 1-4..., 1-n
,11-1,11-2,11-3,11-4,...
..., 11-n-1, 11-n...status display signal,
2, 12-1, 12-2, ..., 12-k... selection circuit, 3, 13-1, 13-2, ..., 13-
k...Selection display signal, 4, 14...Selection signal generation circuit, 5-1, 5-2,..., 5-m, 15...
Selection signal, 6, 16...Display panel, 7-1, 7-2
,7-3,7-4,...,7-n,17-1,1
7-2, 17-3, 17-4,..., 17-n...
...Drive route, 8-1, 8-2, 8-3, 8-4,
..., 8-n, 18-1, 18-2, 18-3,
18-4, ..., 18-n...display section, 9-1,
9-2, 9-3, 9-4, ..., 9-n, 19-
1, 19-2, 19-3, 19-4..., 19-
n... Drive signal, 10, 20-1, 20-2,...
...20-k...Decoding circuit, G ₂₁ to G ₂₄ , G _{7
1} ~ G ₇₄ , G ₁₀₁ ~ G ₁₀₃ , G ₁₂₁ ~ G
₁₂₄ , G ₂₀₁ ~ G ₂₀₄ ...AND circuit, G
₁₀₄ , G ₁₂₂ , G ₁₂₄ , G ₂₀₂ , G _{20
4} ...OR circuit, _I1 to _I10 ...inverter.

Claims

[Claims for Utility Model Registration] n (n is a natural number of 2 or more) state display signals indicating the desired state to be displayed, and n drive circuits each driving n display units using the state display signals. In the display drive control circuit including the n state display signals, m (m is a natural number,
a selection means for selecting by logical combination with m<n) selection signals and sending out k (k is a natural number, k<n) selection display signals; A display unit drive control characterized in that it includes a decoder for decoding which of the n status display signals the selection display signal is from the selection signal and sending it to the corresponding drive circuit. circuit.