JPS6271099A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To extremely shorten a time required for erasing and writing the whole chips in an EEPROM by connecting a capacitor 12 between two terminals of an EEPROM cell to which a high voltage is applied at erasing/writing through a resistor. CONSTITUTION:A high voltage is applied between nodes 6, 7, a word line 5 is selected to charge the capacitor 12 electrically and to keep the potential difference between both the terminals of the capacitor 12, and then the word line 15 is closed. Since the resistor 11 exists, the potential difference between the drain 3 and the control gate 1 of a MOSFET is reduced less than the potential difference of the capacitor 12 by CR delay, so that a thin oxide passing a tunnel current can be prevented from the application of stress. The opening time of the word line 5 may be sufficiently satisfied with the charging time of the capacitor 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an EEPKOM (Electrically Erasable EPRO)
M) Concerning semiconductor memory devices using cells, especially l
Peng's is used when writing the entire chip at high speed.

[Technical background of the invention and its problems]

Generally using 70-chiing f-) gli? In a ROM cell, erasing and writing of the cell are performed by applying a high voltage to a thin oxide film to cause a tunnel current to flow. However, this erasing and writing takes ams of time.
Furthermore, since it is necessary to avoid applying stress to the thin oxide film, when applying a high voltage, the rise time of the arm cannot be made too rapid. For these reasons, it takes a long time to erase and write the entire chip.

Figure 2 shows a conventional 1iiKFR to explain the above matters.
In the OM cell, 1 is the control gate and 2 is the 70-
Teinggut, 3 is Drain, 4 is Select Dart,
5 is a word line, 6 is a pin, ) line, and 7 is a node. Erasing and writing operations of this EEPROM cell are performed by the word line 5.
, leave select gate 4 open, and select node 6.
Apply high voltage between and 7. A few ml for erasing and writing
, the word line 5 must be selected during this time. Furthermore, since the potential difference between nodes 6 and 7 directly becomes the potential difference between drain 3 and control gate 1, stress is applied to the oxide film. :To prevent this, it is necessary to smooth out the rise of high voltage.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and the EEFRO
The present invention aims to provide a semiconductor memory device that can extremely shorten the time required for erasing and writing the entirety of h and f in M.

[Summary of the invention]

In an EEPROM cell having a floating gate and a control gate, the present invention provides a capacitance between two terminals to which high voltage is applied during erasing and writing, that is, the drain and the control gate via a resistor. It is considered a sign that it has been inserted.

[Embodiment 2] An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is an EEFROM cell circuit diagram of the same embodiment, but since this is an example in which it corresponds to the conventional one, corresponding parts are given the same reference numerals and explanations are omitted. Explain the parts. The feature of this embodiment is that a resistor 111 is inserted in the power supply system name of the control gate 1, and a capacitor 2'i is provided between one end of the resistor 11, the drain, and the select gate.

Erasing and writing operations in the configuration shown in FIG. After increasing the potential difference between the two terminals, the word line 15 is closed. However, due to the presence of the resistor 11, the potential difference between the drain 3- and the control gate 1 becomes more blunted by the CR delay than the potential difference of the capacitor 12 (t), which causes stress to the thin oxide film through which the tunnel current flows. You can avoid adding Also, the time it takes to keep Word@5 open is limited to the time it takes to charge the battery to capacity 12.

〔Effect of the invention〕

As described above, according to the present invention, when erasing or writing to an EEPROM cell, the word line can be selected while the capacitor is being charged, so it takes a very short time to write the entire chip. Furthermore, since the resistance is generally high, it is possible to avoid applying strong stress to the thin oxide film.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional EEFROM cell. 1... Control gate, 2... Floating gate, 3... Drain, 4... Select gate,
5...War #9 line, 6...Pit line, 11...Resistance, 12...I:e Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (3)

[Claims] (1) EEPROM that applies high voltage during erasing and writing
A semiconductor memory device characterized in that a capacitor is provided between two terminals of a cell through a resistor. (2) The semiconductor memory device according to claim 1, wherein the two terminals are a drain and a control gate of a cell. (3) The semiconductor memory device according to claim 1, wherein the resistor is connected to a control gate of an EEPROM cell.