JPS6266683A - Pin diode - Google Patents
Pin diodeInfo
- Publication number
- JPS6266683A JPS6266683A JP20697085A JP20697085A JPS6266683A JP S6266683 A JPS6266683 A JP S6266683A JP 20697085 A JP20697085 A JP 20697085A JP 20697085 A JP20697085 A JP 20697085A JP S6266683 A JPS6266683 A JP S6266683A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor layer
- pin diode
- type
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000009792 diffusion process Methods 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 2
- 229910018885 Pt—Au Inorganic materials 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明はＰＩＮダイオードに関し、特に高周波可変抵抗
素子に関するものである。DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a PIN diode, and particularly to a high frequency variable resistance element.
（ロ）従来の技術
一般にＰＮ接合の間に真性半導体である１層を形成しＰ
ＩＮ接合としたのがＰＩＮダイオードといわれる。この
ＰＩＮダイオードはＰＩＮの順方向電流を制御すること
で高周波直列抵抗を変化させることができ、マイクロ波
の回線切替、テレビ・ラジオのバンド切替、ＡＧＣ等多
種に使用されている。(b) Conventional technology In general, one layer of intrinsic semiconductor is formed between the PN junction.
A diode with an IN junction is called a PIN diode. This PIN diode can change the high frequency series resistance by controlling the forward current of the PIN, and is used in a variety of applications such as microwave line switching, television/radio band switching, AGC, etc.
上述の如く使用されているＰＩＮダイオードＱｌ）は一
般に特開昭５９−２２２９７０号公報（第５図）に詳述
されているように１．Ｎ 型の半導体基板υと、ｍＮ
型の半導体基板翰上に形成されるＮ−型の半導体層＠
と、該Ｎ−型の半導体層−の略中夫にその主面より約１
．０μｍの深さまで形成されたＰｉの拡散層−と、該Ｐ
型の拡散層−を囲むシリコン酸化膜（ハ）と、前記Ｐ
型の拡散層（ハ）と電気的に接続された電極（ホ）と
により構成されていた。The PIN diode Ql) used as described above is generally 1. N type semiconductor substrate υ and mN
An N-type semiconductor layer formed on a type semiconductor substrate ＠
and about 1 inch from the main surface of the N-type semiconductor layer.
．． A Pi diffusion layer formed to a depth of 0 μm and the P
a silicon oxide film (c) surrounding the diffusion layer of the mold;
It consisted of a molded diffusion layer (c) and an electrically connected electrode (e).
（ハ）発明が解決しようとする問題点
斯上の如きＰＩＮダイオードＱ１）に順方向電圧を印加
すると１層である前記Ｎ−型の半導体層−に電子、正孔
が注入されろ。この注入された電子、正孔は再結合し、
順方向電流となるものと、１層（財）内に蓄積されるも
のとになる。モして工１６（イ）内に蓄積された電子、
正孔は工層翰の導電率を上昇させ、高周波における直列
抵抗を低下させ高周波可変抵抗素子勾として動作するが
、＠６図（イ）に示す如＜ＰＩＮダイオードの立上がり
電圧以下では動作できない問題点を有し【いた。(c) Problems to be Solved by the Invention When a forward voltage is applied to the PIN diode Q1) as described above, electrons and holes are injected into the N-type semiconductor layer, which is one layer. These injected electrons and holes recombine,
One becomes a forward current, and the other accumulates within one layer (goods). Electrons accumulated in the motor 16 (a),
Holes increase the electrical conductivity of the wire, lowering the series resistance at high frequencies, and operating as a high frequency variable resistance element. However, as shown in Figure 6 (a), there is a problem that it cannot operate below the rising voltage of the PIN diode. [had] points.
に）問題点を解決するための手段
本発明は上述の問題点く鑑みてなされ、少なくとも高不
純物濃度の一導電型の第１の半導体層（３）と該第１の
半導体層（３）上に形成された一導電型の第２の半導体
層（２）と該第２の半導体層（２）の表面に形成された
逆導電型の拡散層（５）と該逆導電型の拡散層（５）と
オーミック接触したアノード電極（９）とを具備するＰ
ＩＮダイオード（１）に於いて、前記第２の半導体層（
２）と接触するアノード電極（８）がショットキー接合
することで解決するものである。B) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and includes at least a first semiconductor layer (3) of one conductivity type with a high impurity concentration and a top layer on the first semiconductor layer (3). A second semiconductor layer (2) of one conductivity type formed on the surface of the second semiconductor layer (2), a diffusion layer (5) of the opposite conductivity type formed on the surface of the second semiconductor layer (2), and a diffusion layer (5) of the opposite conductivity type formed on the surface of the second semiconductor layer (2). 5) and an anode electrode (9) in ohmic contact.
In the IN diode (1), the second semiconductor layer (
This problem can be solved by forming a Schottky junction between the anode electrode (8) and the contact point 2).
（ホ）作用
前述の如く前記−導電型の第２の半導体層（２）とアノ
ード電極（８）をショットキー接合することでＰＩＮダ
イオード（１）内にショットキーバリアダイオードが形
成される。一般にショットキーバリアダイオードはＰＮ
接合のダイオードと異なり、片側が金属（８）であるた
め同一半導体基板濃度に対して立上がり電圧は低くなる
。(E) Function As described above, a Schottky barrier diode is formed within the PIN diode (1) by forming a Schottky junction between the - conductivity type second semiconductor layer (2) and the anode electrode (8). In general, Schottky barrier diodes are PN
Unlike a junction diode, since one side is made of metal (8), the rising voltage is lower for the same semiconductor substrate concentration.
（へ）実施例
以下に本発明の一実施例を第１図乃至第４図を参照しな
がら説明する。(F) Example An example of the present invention will be described below with reference to FIGS. 1 to 4.
本発明のＰＩＮダイオード（１）は第１図に示す如く、
予め用意されたＮ−型の半導体基板（ここでは第２の半
導体層と該当する）（２）の両面にリンを用いて熱拡散
処理を施し、前記Ｎ−型の半導体基板（２）内にＮ 型
の半導体層（３）を形成し、その後前記半導体基板（２
）の一方をミラーボリッシェして−上述の如く作成した
後本発明であるＰＩＮダイオード（１）は次のような構
成となる。Ｎ 型の第１の半導体層（３）上に載置され
ｆ、、Ｎ−Ｗの第２の半導体層（２）と、該第２の半導
体層（２）上にシリコン酸化膜（４）をマスクとして熱
拡散法により形成されたリング状のＰ 型の拡散層（５
）と、前記第２の半導体層（２）の周囲にシリコン酸化
膜（４）をマスクとして熱拡散法により形成されたチャ
ンネルストッパーとして作用するＮ 型の拡散層（６）
と、前記Ｐ 型の拡散層（５）の少なくとも一部と前記
Ｐ 型の拡散層（５）で囲まれた第２の半導体層（２）
が露出するように開口されたシリコン酸化膜（４）と、
少なくとも前記開口部（７）を覆うように蒸着されたＴ
ｉ −Ｐｔ −Ａｕ電極（８）と、ここで電極（８）は
第２の半導体層（２）とショットキー接合される、更に
アルミニウム蒸着より形成されるアノード電極（９）と
、前記第１の半導体層（３）に形成されるカンード電極
（ト）とにより構成される。The PIN diode (1) of the present invention is as shown in FIG.
A thermal diffusion treatment is performed using phosphorus on both sides of a pre-prepared N-type semiconductor substrate (corresponding to the second semiconductor layer) (2), and the inside of the N-type semiconductor substrate (2) is An N-type semiconductor layer (3) is formed, and then the semiconductor substrate (2) is formed.
) is fabricated as described above by mirror-borishing one side of the PIN diode (1) of the present invention, which has the following configuration. A second semiconductor layer (2) of N-W type is placed on the first semiconductor layer (3) of N type, and a silicon oxide film (4) is placed on the second semiconductor layer (2). A ring-shaped P-type diffusion layer (5
), and an N type diffusion layer (6) which acts as a channel stopper and is formed around the second semiconductor layer (2) by thermal diffusion using the silicon oxide film (4) as a mask.
and a second semiconductor layer (2) surrounded by at least a portion of the P type diffusion layer (5) and the P type diffusion layer (5).
a silicon oxide film (4) opened to expose the silicon oxide film (4);
T deposited to cover at least the opening (7)
an i-Pt-Au electrode (8), where the electrode (8) is Schottky-junctioned with the second semiconductor layer (2), and an anode electrode (9) formed by aluminum evaporation; and a canned electrode (g) formed on the semiconductor layer (3).
本発明の特徴とするところは前記開口部（７）を覆うよ
うに蒸着された電極（８）と前記第２の半導体層（２）
との接合部がショットキー接合することにある。The present invention is characterized by an electrode (8) deposited to cover the opening (7) and the second semiconductor layer (2).
The junction with the two is a Schottky junction.
これによりＰＩＮダイオードとショットキーバリアダイ
オードが同時に形成されたことになり第２図（イ）・第
２図（ロ）のような特性が可能となった。従って約０．
２Ｖで立上がり約０．６ｖまではショットキーバリアダ
イオードの７２％性となり、それ以上の電圧となるとＰ
ＩＮダイオードの■、特性となった。また第２図（ロ）
に示す如く順方向電流■。As a result, a PIN diode and a Schottky barrier diode were formed at the same time, making it possible to achieve the characteristics shown in FIGS. 2(a) and 2(b). Therefore, about 0.
When the voltage rises at 2V and reaches approximately 0.6V, it becomes a 72% Schottky barrier diode, and when the voltage exceeds that level, it becomes P.
■Characteristics of IN diode. Also, Figure 2 (b)
As shown in , the forward current ■.
が約１００μＡになると直列抵抗は急激に変化した。こ
れはこの不連続部で急激に層方向電流Ｉ。The series resistance changed rapidly when the current became approximately 100 μA. This causes the layer direction current I to suddenly increase at this discontinuity.
が増加するためである。This is because the amount increases.
一方第３図に示す如くＰ 型の拡散層（５）をＡ→Ｂ４
Ｃと１１次広げてゆ（と、第４図の如く直列抵抗Ｒｓ−
Ｎ−向電流１．特性の変化領域が順次変化してゆく。こ
れはＰ 型の拡散層（５）の接合面積とショットキー接
合面積が変化してゆくためである。On the other hand, as shown in Fig. 3, the P type diffusion layer (5) is changed from A to B4.
C and the 11th order (and the series resistance Rs- as shown in Figure 4)
N-direction current 1. The region of change in characteristics changes sequentially. This is because the junction area of the P type diffusion layer (5) and the Schottky junction area change.
（ト） 発明の効果
以上の゛説明からも明らかな如く、前記開口部（７）を
覆うように蒸着された電極（８）と前記第２の半導体層
（２）との接合部がショットキー接合されることで従来
のＰＩＮダイオードの立上がり電圧より低い電圧で動作
できることが可能となった。(g) Effects of the invention As is clear from the above description, the junction between the electrode (8) deposited to cover the opening (7) and the second semiconductor layer (2) is a Schottky layer. This junction makes it possible to operate at a voltage lower than the rise voltage of conventional PIN diodes.
またショットキーバリアダイオードの特性とＰＩＮダイ
オードの特性が順次光われ、第２図（ロ）Ｋ示す如く急
激な変化を示す特性が実現できた。Further, the characteristics of the Schottky barrier diode and the characteristics of the PIN diode were sequentially illuminated, and a characteristic showing a rapid change as shown in FIG. 2(b)K was realized.
更にＰＷの拡散層（５）を第３図の如＜Ａ−＋Ｂ→Ｃと
順次広げてゆくことで第４図のように直列抵抗−順方向
電流特性の変化領域な顆次変化させてゆくことが可能と
なった。Furthermore, by expanding the PW diffusion layer (5) sequentially from <A-+B to C as shown in Fig. 3, the range of change in series resistance-forward current characteristics is changed condyle as shown in Fig. 4. It became possible.
従ってマイクロ波の回線切替、テレビ・ラジオのバンド
切替、ＡＧＣ等の用途に有効に活用できる。Therefore, it can be effectively used for microwave line switching, television/radio band switching, AGC, etc.
第１図は本発明の一実施例であるＰＩＮダイオードの断
面図、第２図（イ）・第２図（ロ）は本発明のＰＩＮダ
イオードの特性図、第３図は本発明のＰＩＮダイオード
のＰ 型の拡散領域を変化させた時の断面図、第４図は
第３図におけるＰＩＮダイオードの特性図、第５図は従
来のＰＩＮダイオードの断面図、第６図（イ）・第６図
（ロ）は第５図におけるＰＩＮダイオードの特性図であ
る。
主な図番の説明
（１）はＰＩＮダイオード、 （２）は第２の半導体層
、（３）は第１の半導体層、 （４）はシリコン酸化膜
、（５）はＰ 型の拡散層、 （６）はＮｕの拡散層、
（７）は開口部、 （８）は電極、 （９）はアノード
電極、αＯはカソード電極である。
第１ ｒ’４ 甲 ８−．７．９５
１２・イ
〔ｐ＾〕
７、［） 工Ｆ第３１１；］
〔几〕
１１１１＊…Ｉｔミ免エロ
第５図
・２４
ミ・６〜イFigure 1 is a cross-sectional view of a PIN diode that is an embodiment of the present invention, Figures 2 (a) and 2 (b) are characteristic diagrams of the PIN diode of the present invention, and Figure 3 is a PIN diode of the present invention. Fig. 4 is a characteristic diagram of the PIN diode in Fig. 3, Fig. 5 is a sectional view of a conventional PIN diode, and Figs. Figure (b) is a characteristic diagram of the PIN diode in Figure 5. Explanation of main drawing numbers: (1) is a PIN diode, (2) is a second semiconductor layer, (3) is a first semiconductor layer, (4) is a silicon oxide film, and (5) is a P-type diffusion layer. , (6) is the Nu diffusion layer,
(7) is an opening, (8) is an electrode, (9) is an anode electrode, and αO is a cathode electrode. 1st r'4 A 8-. 7.95 12.I [p^] 7.
Claims (1)
体層と該第１の半導体層上に形成された一導電型の第２
の半導体層と前記第２の半導体層の表面に形成された逆
導電型の拡散層と該逆導電型の拡散層とオーミック接触
したアノード電極とを具備するＰＩＮダイオードに於い
て、前記第２の半導体基板と接触するアノード電極がシ
ョットキー接合することを特徴とするＰＩＮダイオード
。(1) A first semiconductor layer of at least one conductivity type with high impurity concentration and a second semiconductor layer of one conductivity type formed on the first semiconductor layer.
In the PIN diode, the PIN diode includes a semiconductor layer of the second semiconductor layer, a diffusion layer of opposite conductivity type formed on the surface of the second semiconductor layer, and an anode electrode in ohmic contact with the diffusion layer of the opposite conductivity type. A PIN diode characterized in that an anode electrode in contact with a semiconductor substrate forms a Schottky junction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20697085A JPS6266683A (en) | 1985-09-19 | 1985-09-19 | Pin diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20697085A JPS6266683A (en) | 1985-09-19 | 1985-09-19 | Pin diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6266683A true JPS6266683A (en) | 1987-03-26 |
Family
ID=16532017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20697085A Pending JPS6266683A (en) | 1985-09-19 | 1985-09-19 | Pin diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6266683A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446979A (en) * | 2010-10-12 | 2012-05-09 | 上海华虹Nec电子有限公司 | PIN (Positive Intrinsic Negative) diode and manufacturing method thereof |
-
1985
- 1985-09-19 JP JP20697085A patent/JPS6266683A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446979A (en) * | 2010-10-12 | 2012-05-09 | 上海华虹Nec电子有限公司 | PIN (Positive Intrinsic Negative) diode and manufacturing method thereof |
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