JPS626497A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To attain redundancy constitution simply even if plural spair memory arrays exist by forming current switches and low active driver stages. CONSTITUTION:One of NPN transistors (TRs) 65-1-65-n, 66-1-66-3 is turned on and one of the corresponding lines Lx1-Lxn, L1-L3 is selected by a driver stage 53 of each corresponding line. Each driver stage 53 is constituted of a Darlington transistor (TR) setting a PNP TR 67 as an input TR; namely, a TR 24 can be driven by drawing the base current of the TR 67. When a current switch 52 is driven almost simultaneously on the address input ADx side and address ad1-ad3 side, the high level turning on the redundant NPN TRs 66-1-66-3 is set higher than the high level turning on the main NPN TRs 65-1-65-n.

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] The present invention is suitable for a semiconductor memory device with a redundant configuration and furthermore, having a plurality of spare memory arrays. The lines that connect to these spare memory arrays and the lines that connect to the original main memory array are connected to the corresponding rows (
low) active do. Furthermore, these driver stages are selectively driven via current switches. The current switch consists of a group of NPN transistors which are emitter-coupled to each other and are turned on and off in response to the respective outputs of each normal driver gate and each conveyor gate for redundancy selection.

[Industrial application field]

The present invention relates to a semiconductor memory device, particularly a redundant IC (Int
egrated C1cutt) memory.

As the microfabrication of IC memories progresses, redundant configurations become essential. For redundant configuration of IC memory, on-chip E C
C (Error Checking and Corr)
There are two known methods: the redundancy method and the redundancy method. In the present invention, an IC memory using the latter method, that is, a circuit including a hard error location due to a defect on an IC chip, is provided redundantly. We will refer to a type of IC memory that can be replaced with a spare circuit. Although a spare row or a spare column is provided as a spare circuit for relief, the present invention can be applied to either type.

[Conventional technology]

FIG. 3 is a block diagram showing the general overall configuration of an IC memory having a redundant configuration. In the figure, 11 is a main memory array, from which a large number of memory cells are read out through each word line (described above each intersecting plane of each bit line) to become read data RD0-t.

Memory cell selection is performed using the X address input A D x and Y
This is done by address input A D v. To do this, first, these address inputs A D x and A D v
are input to X address buffer 12 and X address buffer 13, respectively, and these address buffers send out main selection signals Sx and S7.

These main selection signals S and Sv are further applied to an X driver gate 14 and an X driver gate 15, respectively, which drive lines LX and LV, respectively, connecting to the memory cell to be selected. Thus, one desired memory cell is accessed.

On the other hand, there are defective memory cells in the main memory array 11, and in order to relieve them, the spare memory array 17
is provided. This spare memory array 17 is accessed when the X address input AD specifies the defective memory cell. Therefore, the address ad of the defective memory cell is stored in advance in a recording unit, for example, ROM (Re
ad 0nly Mem-ory) Write it in 19. This address ad is further applied to one input of the conveyor gate 1B. The normal X address input AD
The redundancy selection signal SR is sent out. Spare driver gate 1 receives redundancy selection signal Sll.
6 becomes active and drives the normal spare memory array 17 corresponding to the array containing the defective memory cell.

Here, the defective memory cells in the main memory array 11 are repaired. The above explanation has been made using the so-called word line relief (X address input side relief) as an example, but the so-called bit line side relief (Y address input side relief) is of course also possible, and furthermore, these It is also possible to rescue both the word line and the focus line.

By the way, the block in FIG. 3 that is particularly relevant to the present invention is the driver gate, for example, the X driver gate 14. FIG. 4 is a circuit diagram showing a detailed example of a part of a conventional driver gate.

In this figure, the driver gate 14 has the illustrated transistor configuration, and receives the inhibition signal I sent from the conveyor gate 18 through one emitter-coupled transistor 21 having a differential input. X address input
is sent out, that is, when a defective memory cell is selected, the transistor 21 is turned off regardless of the signal applied from the X address buffer 12 to the bases of the transistors 22 and 23. Then, transistor 2zx:x%
At least one of 3 is always turned on. Therefore, the base potential of the transistor 24 in the driver stage remains at the non-selection level, and as a result, the main selection signal SX
will be invalidated. In other words, all word lines (lines LX) are unselected.

Under such a state, the spare driver gate 16 is driven by the redundancy selection signal Sll from the conveyor gate 18 (which can also be used in combination with the inhibition signal ■), and the spare memory array 17 is accessed.

FIG. 5 is a circuit diagram showing a specific example of the conveyor gate 18. However, the address of the defective memory cell (for example, 8
Only one bit of the bit configuration is shown. As shown in this figure, the conveyor gate 18 has an X address input AD
It consists of an exclusive OR gate (EXOR gate) that compares one bit of X with the corresponding one bit of the address ad of a defective memory cell from the ROM. Only when each bit matches with logic "1" or logic "0", logic "0" is output, and a level "L" (low level) prohibition signal ■ (as well as redundancy selection signal SR) is sent out. do. Thus, if a defective memory cell is selected, the redundant spare memory array 17 is immediately activated by the "L" level inhibition signal I (as well as the redundant selection signal SR).
will be accessed.

[Problem that the invention seeks to solve]

According to the above example, the redundant configuration was only one layer (the spare memory array 17 was one layer). However, as the capacity of memory mounted on a single chip increases, the number of defective memory cells that occur also increases. At times, there arises a demand for relieving these problems and improving yield.

However, there is a problem in that the above-mentioned spare driver gates and spare memory arrays cannot simply be formed into multiple layers. FIG. 6 is a diagram illustrating the problem to be solved by the present invention, and corresponds to a further development of FIG. 4. For example, if the spare driver gate and the spare memory array are made up of three layers, and in order to rescue three defective memory cells, three pairs of conveyor gates (CM, P) and a storage unit (ROM) corresponding to each layer are required. Become.

These are CMPI, ROM+ and CM Pz, RO
Mz and CMP x , denoted by ROMs. What is sent out from each of these pairs are respective inhibition signals (and redundancy selection signals 511) I+, [1 and ■.

If even one of these prohibition signals occurs, the main selection signal Sx must be immediately invalidated. For this purpose, an AND game 1-41 is provided. This AND gate 41 immediately outputs the "L" level when any one of the inhibition signals (which is at the "L" level) is input. As a result, even a plurality of defective memory cells can be repaired.

However, the introduction of the AND gate 41 has a problem.

The first is that there is an unavoidable delay time when passing through the AND gate 41. If such a delay time exists, a meaningless situation will arise in which the main selection signal S is invalidated after a defective memory cell is selected by the main selection signal SX. The second is to connect the AND gate 41 to E CL (Emitter Coupled
Logic) It is not easy to assemble with gates.

While ECL gates are very effective for high-speed memory operation, ECL gates essentially have a structure suitable for creating logical sum gates, OR or NOR.
To form a D gate, these OR and NOR gates must be combined and realized, which also causes the above-mentioned delay time.

[Means for solving problems]

FIG. 1 is a principle block diagram of an IC memory according to the present invention. 1. Similar components are designated with the same reference numbers or symbols throughout the drawings. In this figure, the blocks that should be noticed first are the current switch 52 and the low (l)
ow) active driver stage 53; The driver stage 53 is a driver stage DRV corresponding to the main memory array.
, DRV2゜...DRV,l and driver stages DRV□, DRV-t and DRV corresponding to the spare memory array
.

[For production]

Since the low-active driver stage 53 is functionally equivalent to the conventional driver stage (24 in FIG. 4), the presence of the current switch 52 characterizes the present invention from an operational standpoint. This current switch 52 is connected to each line (L
x+, Lx□,...LXIIIL, -t, s)
It consists of a group of corresponding transistors that are emitter-coupled, so that only one line is always selected. Therefore, when the spare memory array side is selected, the main memory array side is never selected. The reverse is also true. With such a configuration, it is not necessary to employ the AND gate 41 shown in FIG. 6.

Therefore, there is no problem with delay time, and it is also suitable for ECL gate memories.

〔Example〕

FIG. 2 is a circuit diagram showing an embodiment of the <Ic memory according to the present invention. First, the current switch 52 is formed by emitter-coupling a group of NPN transistors as shown in the figure.
A current switch is formed together with constant current 1164. To express it more precisely, the main NPN transistor 5-
1, 65-2=65-n and redundant NPN transistor 6
6-1, 66-2, and 66-3 are emitter-coupled.

Main NPN Transistoro 5-1, 65-2-65-
n is the corresponding driver gate D G +, D G
z, . . . turn on and off according to the output of DC. Also redundant NPN transistors 66-1, 66-2 and 66
-3 is the corresponding conveyor gate 18-1, 18-2
, and turn on and off according to the outputs of 18-3. In the figure, inverters 61 and 62 are connected between these redundant NPN transistors and the conveyor gate, respectively.
and 63 are inserted.

Because the address of the defective memory cell and the address input A
When the DX matches, each conveyor gate (1B-1,
18-2 or 18-3); Prohibition signal 1+
, It, and Iz are L'' level signals, and unless their levels are inverted, the corresponding redundant NPN transistor 66-1, 66-2, or 66-3 cannot be turned on.

Thus, NPN l-ranjistaro 5-1, 65-
2... Only one of 65-n, 66-1 to 66-3 is turned on, and the corresponding line (Lx+,
Lxz, =Lx-, L+ to Lz). This selection is performed by a driver stage corresponding to each line. In this case, the selection cannot be made using only the normal driver stage transistor (24 in FIG. 4). because,
This is because the current switch 52 acts to draw current, and in order to drive the driver stage with such current drawing, it must be a low active driver stage. As a preferred example, each driver M (53) can drive the transistor 24 by drawing a PNP l-transistor current.

In the end, without using the AND gate 41 in FIG.
This means that a redundant configuration with multiple layers can be realized. This AND
The problem was that the insertion of the gate 41 caused a delay time, but according to the configuration shown in FIG.
The address adl to ad3 side is faster than the side. Also, the second
According to the configuration in the figure, inverters 61 to 61 on the address input side
63 is inserted, and considering the consequences, the address manual ADX side and the addresses adl to ad3 side drive the current switch 52 almost simultaneously. However, AND
This does not result in a fatal delay as in the case of using the gate 41.

When the address input ADX side and the addresses adl to ad3 side drive the current switch 52 almost simultaneously, it is preferable to give priority to the addresses adl to ad3 side.
...65-n, redundant NPN transistors 66-1, 66-2 compared to the high ()I) level that turns on
and the high level that turns on 66-3 is higher<(H
H). For example, a difference may be provided between each resistance R in driver gate 51 and each resistance r in inverters 61 to 63. That is, it is sufficient to set R>r in advance. In addition, the second part of the present application
It goes without saying that the use of an inverter such as the PNP l-transistor 7 shown in the figure is not limited, and that an ECL gate may also be used, for example.

〔Effect of the invention〕

As explained above, according to the present invention, even if there are multiple spare memory arrays, a redundant configuration can be easily implemented.Moreover, no matter how many layers the spare memory arrays have, it is possible to simply plug the outlet into the current switch (52). Redundant expansion becomes possible with such ease. Although the IC memory of the present invention is particularly advantageous over ECL IC memories, the basic idea can also be applied to MOS or TTL IC memories.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of an IC memory according to the present invention, Fig. 2 is a circuit diagram showing an embodiment of an IC memory based on the present invention, and Fig. 3 is a general diagram of an IC memory having a redundant configuration. 2 is a block diagram showing the overall configuration; FIG. 4 is a circuit diagram showing a detailed example of a part of a conventional driver gate; FIG. 5 is a circuit diagram showing a specific example of the conveyor gate 18; FIG. FIG. 2 is a diagram schematically representing the problem to be solved. DESCRIPTION OF SYMBOLS 11... Main memory array, 12... X address buffer, 13... Y address buffer, 18-1, 18-2, 18-3... Conveyor gate, 51... Driver gate, 52. ...Current switch\53...Low active driver stage, 61, 62
, 63...inverter, 65-1, 65-2 to 6
5-n-main NPN I-transistor, 66-1, 66
-2, 66-3...Redundant N P N I-transistor, 67... PNP I-transistor, Sx... Main selection signal, SRI+3112, 5II3... Redundant selection signal, II, It, Ill...inhibition signal, AD,,ADV...address input, adl, ad2, ad3...address of defective memory cell. ADy ADx, ADy--7 dress manual Sx, 5y--Main selection signal, Lx, Ly--Line S--Redundant selection signal 1...-Prohibition signal General IC memory with redundant configuration Fig. 3 is a block diagram showing the overall configuration; Fig. 3 is a circuit diagram showing a detailed example of a part of a conventional driver cart; Fig. 4 is a circuit diagram showing a specific example of a conveyor f-)+8; Figure 6 diagrammatically represents

Claims (1)

[Claims] 1. An address buffer that receives a designated address input and sends out a main selection signal for selecting the relevant memory cell from the main memory array; A driver gate that drives a line connected to a memory cell detects that a defective memory cell in the main memory array has been selected by comparing it with a pre-held address of the defective memory cell and generates a redundancy selection signal. at least one conveyor gate for transmitting and disabling the main selection signal and respectively selecting at least one spare memory array via the line, the semiconductor memory device comprising: a conveyor gate for each output of the driver gate; A main NPN transistor that is turned on and off according to the output of the conveyor gate and a redundant NPN transistor that is turned on and off according to each output of the conveyor gate are provided, and these are emitter-coupled to form a current switch. A semiconductor memory device characterized in that a low active driver stage is provided for each line to drive the corresponding line depending on whether the line is turned on or off.