JPS6263172A - Ignition timing control for internal combustion engine - Google Patents

Abstract

PURPOSE:To permit the correct ignition in all the cylinders by arranging two position detecting means, separated by the angle corresponding to the crank angle between the top dead centers of two cylinders in a prescribed ignition order and carrying out ignition control by processing the output signals of the means. CONSTITUTION:In the application for 4-cylinder engine 1, a rotary disc 15 having reactors 16a-16g projectingly installed at the equally divided positions excluding one position on the circumference is installed onto a crankshaft 14, and two electromagnetic pick-ups 17 and 18 are arranged outside the disc 15. The pick- ups 17 and 18 are arranged, separated by the angle corresponding to the crank angle between the top dead centers of two cylinders in a prescribed ignition order. When the pick-up 17 detects a prescribed angular position in the ignition control by an ECU 2, ignition of one of the above-described cylinders is carried out, and when the pick-up 18 detects the angular position after the pick-up17 detects the angular position immediately before the reactor cut part on the rotary disc 15, ignition for the other cylinder is carried out.

Description

[Detailed Description of the Invention] 3. Technical Field of the Invention This invention relates to ignition timing control for an internal combustion engine, and in particular to control of ignition timing for each cylinder of an internal combustion engine having a plurality of cylinders. The energization and de-energization of the motor is controlled only by the crank angle position signal. This invention relates to an ignition timing control method using a so-called angle lock method.

(Background of the invention and its problems) The angular positions of a plurality of protrusions 2 that have one missing part and are arranged at equal intervals (for example, equally spaced at 45 degrees) on the circumference of the output shaft of an internal combustion engine are different. Detected by first and second position detection means located at circumferential positions.

When the second position detecting means does not detect an angular position while the first position detecting means detects an adjacent previous angular position and a subsequent angular position, the subsequent angular position is set as a reference crank angular position. There is a known method for detecting a reference crank angle position, and after detecting a reference crank angle position by this method for detecting a reference crank angle position, a predetermined angle position is detected by a first position detection means, and then, A method (hereinafter referred to as "arithmetic ignition control method") is known in which ignition is performed after a required period of time has elapsed from the detection of the predetermined angular position to optimize the ignition timing at the rank angular position. It is being Furthermore, in an operating range where engine speed fluctuations are large, such as an extremely low engine speed range, the ignition timing is fixed at a predetermined crank angle position (for example, the top dead center position of each cylinder) instead of the above-mentioned computational ignition control. A so-called angle lock control method or fixed ignition control method is employed. If the protrusions of the rotating body used in the above-mentioned calculation ignition control are provided in a protruding manner corresponding to the top dead center position of each cylinder, the first position detecting means can detect the top dead center position of each cylinder even in fixed ignition control. It is sufficient to ignite each cylinder at the time of each detection of the protruding angular position corresponding to the point position. However, for example, not only in-line 4-cylinder engines but also engines with cylinder angles of 4
5°, 60'.

In the case of V-type four-cylinder engines such as 90", 128", 135', etc., the top dead center interval of each cylinder is different, so depending on the type, an ignition control device that applies such an ignition control method is applied. I can't do it.

(Object of the Invention) The present invention was made to solve the above-mentioned problems, and is capable of accurately igniting each cylinder at a set ignition angle position, and moreover, is applicable to various types of engines. It is an object of the present invention to provide an applicable ignition timing control method for an internal combustion engine.

(Structure of the Invention) According to the present invention, a plurality of angular positions arranged at equal intervals with one missing portion on the circumference of the output shaft of an internal combustion engine are connected to the first and second angular positions at different circumferential positions. when the second position detecting means does not detect the angular position while the first position detecting means detects an adjacent previous angular position and a subsequent angular position; In the ignition timing control method, the subsequent angular position is set as a reference crank angular position, and ignition is executed when a predetermined number of angular positions are detected by the reference crank angular position detector. are arranged at an angle corresponding to the crank angle between the respective top dead centers of two successive cylinders, and when the first position detection means detects a predetermined angular position, ignition of one of the cylinders is performed. executing the ignition of the other cylinder when the second position detecting means detects the angular position after the first position detecting means detects the angular position immediately before the cutout portion; A method of controlling ignition timing for an internal combustion engine is provided.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

Fig. 1 is an overall configuration diagram of an electronic ignition timing control device to which the present invention is applied. In the figure, reference numeral 1 is an in-line four-cylinder engine, and reference numeral 2 is an electronic control unit (hereinafter referred to as rEcUJ), and engine 1 is other than an in-line four-cylinder engine. Also, the cylinder included angle (hereinafter referred to as "bank angle") is 45" and 60'.
, 90', 1211@, 135'', etc. Fig. 1 is a partial cross-sectional view of the main part of one of the plurality of cylinders. Reference numerals 10a and 10b indicate spark plugs. Although only two spark plugs are shown in the figure, these spark plugs are installed in each cylinder separately.As will be described later, each spark plug 1-Oa, 10b is connected to an ignition coil installed separately. For a four-cylinder engine, one other spark plug (not shown) is electrically connected in series with the spark plugs marked IQ, and a. It is.

Similarly, another spark plug (not shown) is electrically connected in series with the spark plug 10b.

Each of the two spark plugs connected in series is ignited by the same large signal, and one of the two spark plugs that are lit at the same time is ignited during the exhaust stroke, so this is the so-called stubby ignition method. is taken. Reference numeral 3 designates a combustion chamber of the engine 1, and an intake pipe 4 and an exhaust pipe 5 are communicated with the combustion chamber 3.

An intake valve 6 and an exhaust valve 7 are provided at each communication port, respectively. A throttle valve 8 is provided in the middle of the intake pipe 4, and an absolute pressure sensor (hereinafter simply referred to as "intake pressure sensor") 9 is provided downstream of the throttle valve 8. The intake pipe internal pressure signal converted into an electric signal by 9 is sent to the ECU 2. Further, the peripheral wall of the cylinder of the engine 1 is filled with cooling water, and an engine water temperature sensor 11 made of a thermistor or the like is attached to this portion. A detection signal from this engine water temperature sensor 11 is supplied to the ECU 2. A piston 12 is connected to a crankshaft 14 via a connecting rod 13. A pulse generating mechanism is disposed on this crankshaft 14 to generate first and second pulse signals PCI and PC2 as shown in FIGS. There is. That is, first, the rotating disk 15 is attached to the crankshaft 14, and the reactors 16a to 1, which are formed of convex bodies made of ferromagnetic material, are attached to the circumference of the rotating disk 15.
6g are protruded at equal positions on the circumference except for one position, for example, at angular intervals of 45°. In the illustrated example, only one reactor is missing between reactors 16d and 16e, and the angular interval of this missing part is 90''.Rotating disk 1
5, magnet bodies 17a, 1 are arranged along its circumference.
Electromagnetic pickups (hereinafter referred to as "pulsar") 17 and 18, which are first and second position detection means formed by winding coils 17b and 18b around 8a, are disposed. The angular spacing between the first and second pulsers 17 and 18 is defined in accordance with the top dead center spacing of the applied engine, and in the illustrated example, it is applied to an in-line four-cylinder engine with a top dead center spacing of 180°. The angular spacing between the two pulsers 17 and 18 is defined as approximately 180''.For example, when the present invention is applied to an engine with a bank angle of 128°, , the arrangement spacing of the pulsers 17 and 18 is defined by the top dead center spacing (128@) of the engine.

On the other hand, the ECU 2 includes an input circuit 19, an input/output LSI (hereinafter [engineering 10/LSI
(referred to as rCPUJ) 21, central processing unit C (referred to as rCPUJ) 22. A/D converter 23 and first . Second output circuit 24a.

24b is provided. Furthermore, the input circuit 19 has a first
and the first and second pulse signals Pct and PC2 generated by the second pulsers 17 and 18, respectively (see FIG. 2(a), which will be described later).
(b) Waveform shaping circuits 25 and 26 that shape the waveform of
First and second flip-flop circuits 27 and 28 are provided to latch the outputs from the waveform shaping circuits 25 and 26, respectively.

The first flip-flop circuit 27 has its Q output line connected to the INT terminal of the CPU 22 via the l1O-LSI21, and the second flip-flop circuit 28 has its Q output line connected to the INT terminal of the CPU 22 via the l1O-LSI21. CPU
It is connected to the 5TATUS terminal of 22. Reference numeral 29 is a clear signal line for the first and second flip-flop circuits 27 and 28.

The CPU 22 executes various programs for calculating the energization timing and the ignition timing, and internally contains the above calculation program, a No-Pe-θig map described later, and a T
Read-only memory (hereinafter referred to as rROMJ) that stores w-Δθig table, bank angle table, etc. 31. and a random access memory (hereinafter referred to as rRAMJ) 32. for storing the above calculation results, etc. An I10 buffer 33 for input/output is provided, and an internal counter 34 functioning as a power supply counter is further provided within the CPU. Reference numerals 34a and 34b indicate registers in the RAM 32 that store the energization timing data, and reference numerals 35a and 35b indicated by broken lines indicate comparators, and these comparators 35a and 35b store the count value of the internal counter 34 and each register 34a.

Compare the stored contents of the energization timing data of each of 34b,
When the counted value and the stored value match, the CPU 22 (7) turns on.
- PORT terminals 22 a, 22 b A program-like process for outputting a predetermined high level (hereinafter referred to as rll level or rHJ level) is shown below.
The "1" level output as the energization signal on the 0a side and the "1" level output as the energization signal on the spark plug 10b side to the 0N-PORT terminal 22b are I10 and LS, respectively.
The first and second output circuits 24a, 24b via I21
It is guided to each energized signal line 40a, 40b.

On the other hand, the Ilo LSI 21 includes a first ignition counter 36 for the ignition plug 10a, the details of which will be described later, and a second ignition counter circuit 37 for the other ignition plug 10b.
is installed. Figure 3 shows the ignition counter circuit 36,
37, each counter circuit has first and second registers 38a and 38b, which store the lower 8 bits and upper 8 bits of binary ignition timing data (for example, 16-bit data), and First and second counters 39a and 39b that count the number of pulses of a clock signal generated in a period, and a first comparator 41 that compares the data of the first register 38a and the count value of the first counter 39a.
a, the data of the second register 39a, and the second counter 39
It is composed of a second comparator 41b that compares the counted value of b, and a pre-stage register 42 that is connected to the second register 38a by a pass line and stores the upper 8 bits of the ignition timing data. The pre-stage register 42 is connected to the CPU 22 via a data bus 43. First and second counters 39a.

39b is an 8-bit up counter, and the output side of the AND circuit 49 is connected to the clock terminal GK of the first counter 39a, and one input terminal of the AND circuit 49 is connected to the clock terminal GK of the first counter 39a.
The Q output terminals of five -S flip-flops are connected, and the clock signal is applied to the other input terminal. 1st
The most significant bit output terminal of the counter 39a is connected to the clock terminal 39b of the second counter 39b. The output side of the second comparator 41b is connected to the corresponding first and second
It is connected to the output circuits 24a and 24b of , and is also connected to each reset terminal R of the first and second counters 39a and 39b and the R-S flip-flop 50. R-S
A start signal pulse supplied from the CPU 22 is applied to the set terminal S of the flip-flop 50 .

Returning to FIG. 1, numerals 30 and 47 in the l1O-LSI 21 are a fail-safe circuit and a Me timer, respectively, which detect the output timing signal, which will be described later. The first and second ignition counters 36 and 37 are connected to output lines 44a and 44a, respectively.
44b to the first and second output circuits 24a, 24b.
It is connected to the.

Reference numerals 45 and 45 denote first and second ignition coils, and these ignition coils 45 and 46 are provided with a primary coil and a secondary coil, respectively, which are not shown.

The output line from the first output circuit 24a is connected to the primary coil of the first ignition coil 45, and the secondary coil is connected to the spark plug 10a. Further, the primary coil in the second ignition coil 46 is connected to the second output circuit 24.
The output line from spark plug 10b is connected, and the secondary coil is connected to another spark plug 10b.

Next, the operation of the electronic ignition timing control device will be explained with reference to FIGS. 2, 4 to 13. 4 to 10 and 12 are flowcharts showing the ignition timing control procedure executed by the CPU 22. First, the flowchart of the main routine in FIG. Initialization processing of the CPU 22, etc. is performed, and then, in step 100, the reference position of the crank angle is detected. After detecting the reference position.

Calculating the time Me required for one rotation of the crankshaft 14,
and determining the value of the engine rotational speed Ne based on this Me value (step 200), calculating the advance angle data θig, and storing the calculated value in the RAM 32 (step 300).
, calculation of the energization time TOH and storage of this calculated value in the RAM 32 (step 400).

Energization stop timing based on advance angle data θig and energization time TOH, that is, ignition timing data Tig and energization timing data Tc
The calculation of g and the storage process of these calculated values in the RAM 32 (step 500) are performed sequentially, and each such calculation process is repeated when the interrupt processing program INT, which will be described later, is not executed.

Next, the processing in each of the above steps will be explained in detail.

FIG. 5 shows in detail the initialization process and the reference position detection procedure in step 100 in FIG. Step 101 is executed and the CPU 22 is initialized.

In the initialization process, the RAM32 area is cleared to zero, I10
Port initialization settings, etc. are performed. After the initialization process, the stage variable STG is set to a temporary value of 1 (step 102
).

At the same time, the first variable CTI used to determine whether the detected reference position is the correct reference position, which will be described later, is set to the same value as the number of reactors 16a to 16g, and the second variable CT
2 to zero (steps 103 and 104), and the first flip-flop circuit 27 is set with a clear signal (see FIG.
e)) After resetting (step 105),
It waits for the first pulse signal PCI to be latched by the first flip-flop circuit 27 (step 106). Below, in order to make it easier to understand how to detect and confirm the crank angle reference position, the stage variable S
Changes in the values of TG, first variable CTI, and second variable CT2 will be explained with reference to Table 1.

Table 1 shows the values of each variable when the engine is started when the pulsar 17 in Figure 1 is located opposite the second stage, and the actual engine speed is 20 Orpm or more. S.T.G., C.T.I.

It shows the change in Cr2. 1st 1st pulse signal PCI
(stage 3 signal) is the first flip-flop circuit 2
When latched at 7, the reference position is detected and confirmed as follows. First, reset the first flip-flop circuit 27 (step 107), start the Me timer 47 (step 108), wait until the first pulse signal PCI is input (step 109), and then start the next 1 pulse signal is input, the Me timer 47 is read (step 110), 'Me
After reading the timer value Tsi, the 0Me timer, which determines whether or not the Me timer 47 has overflowed, overflows at the value of Me corresponding to the rotation speed below the extremely low rotation speed. If this determination result is affirmative (Yes), the subsequent reference position detection processing is not performed and the process execution is returned to the processing position of step 102 (hereinafter referred to as rsTATIJ).0 Even if the determination result is negative (No) Next step 1
In steps 12 to 115, it is determined as follows whether the engine rotation speed Na is a predetermined low rotation speed, for example, 200 rpm+s or higher, and it is also determined whether the current pulse PCI is the first pulse that has passed through stage 4. Discern.

This determination will be explained with reference to Table 2.

In the above table, stage 4 corresponds to the missing part of the reactor as described above, and is a stage whose crank angle is equivalent to 90°. In addition, stages other than stage 4 are stages corresponding to a crank angle of 45'' at equally divided positions of the reactor.First, in step 112, the Me value is determined as the first discrimination value (for example, the engine measured at a stage other than stage 4). 37.5m5), which corresponds to a rotation speed of 20Orpm.
It is determined whether or not the value is greater than or equal to the value. This discrimination result is negative (N
o), as shown in the first column of Table 2, the engine speed Ne is determined to be at least 200 rpm or more in stage 4° or any stage other than stage 4, so in the step of determining the reference position. certain step 1
The process proceeds to step 16. If the determination result in step 112 is the process (Yes), it is further determined in step 113 whether or not the Me value is equal to or greater than a second discriminant value (for example, 75 m5) that is twice the first discriminant value. . If this determination result is affirmative (Yes), as shown in the third column of Table 2, the engine speed Ne is 200 rpm or less at stage 4° and any stage other than stage 4. In such a low rotation range, the pulse signal generation function from the pulsers 17 and 18 may be impaired and pulse signals may not be generated properly, so the process is returned to 5TATI. The determination result in step 113 is negative (
If NO), the Me value is 75■B≧Me>37.5m
In this case, as shown in Table 2, the M
Depending on the stage at which e is read, the engine rotation speed Ne may be 200 rpm or more. In other words, if the Me value is measured at a stage other than stage 4, it means that the engine speed is below 200 rpm, but if it is measured at stage 4, the engine speed is between 200 rpm and 40 rpm. Become. Therefore, in step 114, it is determined whether the value of C10 is zero or not, and after confirming that it is zero, the value of C10 is changed to The STG value (value 2) set in the previous loop is set and this value is stored (step 115).

If step 114 is executed again after this loop and it is determined that the value of C10 is a value other than zero, stage 4 corresponding to a crank angle of 90° will be activated once during one rotation of the crankshaft 14. Since its presence is only allowed, it is assumed that the actual engine speed Ne was less than 200 rpm, or that an abnormality occurred in the PCI pulse signal and the pulse that should have been generated did not occur.
Return to

Next, in step 116, when the first pulse signal PCI is latched in the first flip-flop circuit 27 as shown in FIGS. 2(Q) and (d), the Q output of the second flip-flop 28 is is zero, that is, the second pulse signal PC
2 is missing. If this determination result is negative (No), the stage variable STG is incremented by the value 1 (step 117), and the first variable value CT1
The process from step 107 is repeatedly executed while decrementing by the value 1 (step 118). During this repeated execution, if the engine speed Ne is determined to be 200 rpm+m or less, or if the engine speed Ne is 20O
The determination result when the first variable value CT1 reaches zero (step 't11g) is negative (Y
es), there is a possibility that an erroneous pulse signal was input, so the internal combustion engine is cranked and the engine is turned to 5TA.
Return processing to T1. On the other hand, if the determination result in step 116 is affirmative (Yas), step 1 determines whether or not the crank angle position at this time is the true reference position as follows.
Confirm below 19. That is, first, in step 117, it is determined whether the value of the second variable CT2 remains at the initial setting value of zero. If this determination result is affirmative (Yes), as described in the determination part of step 112, the determination result of this step 112 is negative (No), and the engine speed No. is at the stage corresponding to the crank angle 45@. After the reference position is properly detected in step 116, it is determined that the reference position has been detected, and this detected reference position is determined to be the correct reference position, and the reference stage number (see Table 1) is assigned to it. For example, the numerical value 7) is set (step 123).

On the other hand, if the determination result in step 119 is negative (NO), it is assumed that the engine speed No. is detected at a stage corresponding to a crank angle of 90'', as described in the processing portion of steps 112 to 114 above. , second variable CT2
This is the case where the value of is set to 2 (step 115) and the subsequent processing is proceeded, so as shown in Table 2, the stage set to this value of 2 will correctly set the crank angle to 90°.
Step 116
Confirm this by calculating backwards from the reference position of the stage determined in step. This confirmation will be explained with reference to the numerical sequence listed in the second column of Table 1. First, in step 120, rSTG-CT2=
Find A' J. Here, STG is a value set at the stage immediately before the stage where the reference position was found, and is 4 in the numerical example. C10 is the value of the second variable CT2 set in step 115, which is 2. By substituting this value into the above equation, 4-2=2=A' is obtained. Next, in step 121, "Find standard 5TG-A'=AJ. Standard ST
G is the value 7 from Table 1. Therefore, the above equation is 7-
2=5=A is found. In the next step 122, it is determined whether the value of A obtained as described above is 5 or not. The value of A=5 is determined by setting the interval between the two pulsers 17 and 18 as described above, and setting the first F/F=1 and the second F/F.
=O, when the crank angle position detected by the first pulser 17 is taken as the reference crank angle position, the value is 5 for any type of engine. The stamp 12
Since the value of the calculation result A of 1 is 5, in the case of the above numerical sequence, the determination result in step 122 is affirmative (Yes). If the determination result in step 122 is positive (Yes), it is determined that the reference position detected in step 116 is the correct reference position 8 in the same way as described above, and the stage at this reference position 8 is assigned a reference stage number. is set (step 123).

If the determination result in step 122 is negative, the detected stage is not the correct reference stage, and the process returns to 5TATL.

When the reference position 8 is correctly detected as described above, the Me value is calculated and the engine rotational speed Ne is determined in step 200 of FIG. 4.

This will be explained using the subroutine flowchart shown in FIG. In step 201, the first pulse signal PCI
Thus, the occurrence time interval Tsi (i=1 to 7) (Fig. 2 (
a)) is measured by a clock pulse by the 1Me timer 47, and the total time Me for one rotation is calculated.

In step 202, the crankshaft 14 moves one stage from this total time Me, in other words, the crank angle is 45''.
Average value of time required to rotate by a certain amount T s = M
e÷8 and the time required to rotate the crank angle equivalent to 1 @ ΔT='Ts÷45, and store this in RAM3.
2 to prepare for calculation processing such as ignition timing Tig, which will be described later.

Next, in each step after step 203, it is determined in what rotation speed range the current engine speed Ne is. First, in steps 203 to 206, it is determined whether the engine rotation speed Ne is in an extremely low rotation range. In step 203, the engine speed Na is set to a predetermined speed NIc at which the ignition timing control should be switched to fixed ignition control, which will be described later.
A predetermined rotation speed N1. which is lower than kc@ by a predetermined value. c*t,C
For example, if the answer is affirmative (Yes), the process proceeds to step 204, where the value of the flag N1 is set to zero, and if the answer is negative (no), the process proceeds to step 205. In step 205, the engine speed Ne
It is determined whether or not the rotational speed is equal to or higher than a predetermined rotational speed NIGC (for example, 500 ppm) which is higher than the predetermined rotational speed NlG14 by a predetermined value. If the answer is affirmative (Yes), the process proceeds to step 206 and the flag N1 is set, and if the answer is negative (No), the process proceeds to step 207. In this way, since the discrimination rotation speeds for switching the flag value N1 from zero to value 1 or from value 1 to zero are set to different values, it is possible to stabilize the ignition timing control.

Next, in steps 207 to 210, it is determined whether the engine speed Ne is in a high speed rotation range. The determination of this high-speed rotation region is also performed in steps 203 to 206 described above.
As in the case of , the discrimination value is set to a value that gives a hysteresis characteristic, and in step 207, the engine rotation speed Ne is set to a predetermined rotation speed NIGACtL (for example, 5000 rpm) that is lower than the predetermined rotation speed NIGAC1 by a predetermined value.
If it is determined that the engine rotation speed is below (the determination result in step 207 is affirmative (Yes)), the flag value N2 is set to zero (step 207), and in step 209, the engine rotation speed Ne is lower than the predetermined rotation speed NIQAC1 by a predetermined value. High predetermined rotation speed N + GAcx H (for example, 5500pp
m) If it is determined that this is the case (the determination result in step 209 is affirmative (Yes)), the flag value N2 is set to the value 1 (
Step 210), this flag N2 is used to determine whether or not acceleration correction of the ignition timing data Tig, which will be described later, may be performed when the engine suddenly accelerates, which will be described later. Number of revolutions N! When the speed is higher than GAc1, sufficient calculation processing time cannot be secured, so acceleration correction of the ignition timing data Tig is prohibited.

In steps 211 to 214, the engine rotation speed Ne is equal to or lower than the predetermined rotation speed Nl@Ac, and the predetermined rotation speed Nr
ahCz (N+ec trap<NteAcz<N+aAct
) or above. The determination of this rotation range is also set to a value that gives a hysteresis characteristic to the determination value in the same manner as described above, and in step 211, the engine rotation speed Na is set to the predetermined rotation speed NIQAC.

A predetermined rotation speed N I QAC2L (
For example, if the flag value N
3 is set to zero (step 212), and step 21
3, the engine speed Ne is the predetermined speed NIQAC.
, if it is determined that the predetermined rotational speed NIGAC,H (for example, 3000 rpm) is higher than , by a predetermined value (the determination result in step 213 is affirmative (Yes)), then the flag value N3 is set to the value 1 (step 214). ), this flag N3
is used to determine whether or not to further perform acceleration correction of the energization timing data Tcg, which will be described later, based on the ignition timing data Tig that has undergone acceleration correction, when the engine suddenly accelerates or decelerates. No is the specified rotation speed NIGA
If it is 03 or less, sufficient calculation processing time can be secured, so the energization timing data Ta is used together with the ignition timing data Tig.
Acceleration correction of g is also performed.

In the main routine, in the next step 300, advance angle data θig from the reference crank angle position q is calculated and the result of this calculation is stored. The lead angle data θig is Ne
It is calculated according to the following equation (1) from the values of the intake pipe internal pressure PR and the engine water temperature Tw detected by the intake pressure sensor 9 and the engine water temperature sensor 11, respectively.

θig=θigMAP+Δθig...(1) Here, θigMAP indicates basic advance angle data, and is a function of engine speed Ne and intake pipe pressure Pa (θigMAr
=f(Nap Pa)) and is read from the Ne-PB-θig map stored in the ROM 31. 80ig is a correction value for the advance angle data, and for example, the value is determined as a function of the engine temperature Tw (Δθig=f(Tw)) and is read from the Tw-Δθig table stored in the ROM 31. Note that the value of the advance angle data θig is specified with the value of the maximum advance angle θig' (for example, 60°) as the upper limit, and when the value obtained as above exceeds this maximum advance angle θig', −This maximum advance angle θi
It is corrected to the value of g'. The lead angle data θig obtained in this manner is stored in the RAM 32.

Next, in step 400, the energization time TOH is calculated and the result of this calculation is stored.One energization time TON is a function of only the engine speed Na, as shown in the following equation (2), and is stored in the ROM 31 in the same manner as above. N e −T
Read from the ON table.

ToN=f (Ne) - (2) The energization time data ToN thus obtained is stored in the RAM 32.

After the advance angle data θig and the energization time data TON are obtained, in step 500, ignition timing data Tig and energization timing data Tag are calculated based on these values. First, regarding the ignition timing data Tig, for each engine bank angle and each cylinder, the stage number at the position advanced by the maximum advance angle θig' from the crank angle reference position q (in the example of Fig. 2 (a), stage 6 ) and the crank angle from the start of this stage position to the maximum advance angle θig' position (hereinafter referred to as "angle data") is RO.
It is stored in M31 and displayed. CPtJ22 stores these angle data and advance angle data 01g, etc. in ROM31 and RA.
The angle DEG from the stage 6 pulse q' is calculated by the following equation (3).

DEG=θig'-〇ig ten angle data... (3) Next, from this angle DEG, ignition timing data Tig is (4
) is calculated using the formula.

Tig=ΔTXDEG−(4) where ΔT was stored in the RAM 32 at step 202 in FIG. 6 above. This is the time required for the crankshaft 14 to rotate by 16 crank angles.

Further, one energization timing data T c g is calculated by the following equation (5) from the ignition timing data Tig and the energization time data TON obtained as described above.

Tcg= l (TON-Tig) -Ts Xm
1-(5) Here, m is the number of stages (stage 2 Ta) up to the stage at which the ignition coil starts energizing before the stage advanced by the maximum advance angle θig' (stage 6 in the example shown in Fig. 2). In the illustrated example, m=1), and Ts is the average value of the time required for the crankshaft to move through a 45° crank angle determined in step 202 of FIG. Each calculation value above is R
Stored in AM32.

Next, the execution of energization and ignition will be explained with reference to the flowchart of FIG. The interrupt arithmetic processing program INT shown in FIG. 7 is executed with the highest priority every time the Q output from the first flip-flop circuit 27 is input to the CPU 22.

That is, the interrupt program INT is executed every time the first balsa 17 detects a predetermined crank angle position, and when the interrupt program INT is executed, the processing interruption position (stack point) of the program that has been executed so far is reached.
is stored in a stack register (not shown), then the arithmetic processing moves from that program to the interrupt program INT.

First, in step 601, it is determined whether the processing of the interrupt program INT, which started execution when the previous predetermined crank angle position was detected, has not yet finished, and the current interrupt processing was executed during this interrupt processing. do. This answer is negative (No)
In this case, the process proceeds to step 603, reads the measured value of the 1Me timer 47, stores it, and then resets the Me timer 47 and restarts it. Next, the process proceeds to step 604, where the STG value updated in step 615, which will be described later, of the previous loop is used.
stage). If this determination result is affirmative (Yes), the CPU 22 sends a start signal to the ignition counter circuit 36, and the ignition counter circuit 36
(step 605, FIG. 2(g)), and the process proceeds to step 606.

This starting signal is R of the ignition counter circuit 36 shown in FIG.
-S is input to the set terminal S of the flip-flop 50, and a "1" level is generated at its Q output terminal. The “1” level generated at the Q output terminal of flip-flop 50 is AN
The D circuit 49 is opened, thereby causing the first counter 3
Application of a clock signal to the clock terminal CK of 9a is started.

On the other hand, if the determination result in step 604 is negative (No), the process directly proceeds to step 606, and the CPU 22's 0N-PO
A "1" level is output to the RT terminal 22a. This 0N-
The "1" level appearing at the PORT terminal 22a is supplied to the first output circuit 24a via the energizing signal line 40a, but this first output circuit 24a is connected to the 0N-PORT terminal 22a.
It is possible to start energizing the ignition coil 45 only when the output of the ignition coil 45 is reversed from "0" to "1". Therefore, if the output level of the 0N-PORT terminal 22a is originally "1", there will be no change in the operation of the first output circuit 24a even if the "1" level is output again to it, but as will be described later. Once “0” is applied to the 0N-PORT terminal 22a.
” level is output and the standby state is set, this step 606 is executed, and the ignition coil 45 is forcibly turned on.
It is possible to start energizing.

Next, the process proceeds to step 607, and the internal counter 34, which is a one-current counter, is started (FIG. 2(g)). The energization counter 34 is started every time this interrupt processing program is executed.Next, the process proceeds to step 60g.
The engine rotation speed Ne is the predetermined extremely low rotation speed NlG37P (
For example, it is determined whether the rotational speed is 200 rpm or more.

If this answer is negative (No), proceed to step 609;
Ignition prohibition processing, which will be described later, is executed to prevent adverse effects on the engine due to faulty ignition. If the determination result in step 608 is affirmative (Yes), it is determined whether or not the fixed ignition control should be executed depending on whether the flag CRFLG value is equal to the value 1 (step 610).

If the flag value CRFLG is equal to the value 1, a fixed ignition control subroutine CRNK to be described later is executed, while if the flag value CRFLG is zero, the process proceeds to step 611, and the generation time interval (pre-stage time interval) Ts of the pulse signal PCI is executed. The stored value of (n) is updated to the measured value of the Me timer 47 read in step 603 of the current loop. The updated Ts(n) value is used for calculating the Me value executed in step 201 of FIG. 6 above.

Next, in step 612, the intake pressure value Pa and engine water temperature value T'w detected by the intake pressure sensor 9, engine water temperature sensor 11, etc., respectively, are read. In addition, step 6
At step 12, parameter values to be read for each stage are set. For example, the intake pressure value Pa is read at the #2 stage, and the engine water temperature value Tw is read at the #5 stage.

Next, in steps 613 and 650, it is determined whether the engine is overspeeding. That is, first, in step 613, it is determined whether the engine is in the fourth stage. The fourth stage is shown in Figure 2(a).
As shown in the figure, the stage where the crank angle is equivalent to 90° has an angular interval twice that of other stages, and there is no continuous execution request for the interrupt calculation processing program INT during this period, that is, the fourth stage The program processing time is twice as long as that of the other stages, and the fourth stage can process calculations that cannot be processed in other stages at high rotation speeds. This detects the crank angle position using two pulsers 17°18 and a reactor 1 protruding from a one-rotation disk 15 having one circumferentially missing part.
6a to 16g, if the determination result in step 613 is negative (No), it is assumed that the processing time required for overspeed determination cannot be secured, and the process skips the stellar 650 and proceeds to step 614. If the answer is yes, the process advances to step 650 and subroutine NECHK is executed.

FIG. 8 shows a flowchart of the subroutine NECHK, in which in step 651 the Ts and values stored in step 611 of FIG.
Since it was executed immediately after I was detected, the latest Tsn value detected in this loop is the PCI pulse generation time interval Ts in the third stage. ) is set as the variable value TNe. Determinations in steps 652 and 654, which will be described later, are performed using this variable value THe. In step 652, it is determined whether the engine has exited the overspeed state. That is, this determination is made based on whether or not the engine rotational speed Ne is less than or equal to a predetermined lower limit rotational speed, NH()OVL (for example, 15000 rpm). If this determination result is positive (Y as), flag CUT
The value 0 is set in FLG to store that the engine has left the overspeed state (step 653). If the answer is negative (No), the process proceeds to step 654, where it is determined whether the engine is in an overspeed state. That is, the engine rotation speed Ne is set to a predetermined upper limit rotation speed NIGOVH (for example).

16,000 rpm) or more, and if the result of this determination is affirmative (Yas), the value 1 is set in the flag CUTFLG.
is set to remember that the engine is in an overspeed state (step 655), and if the answer is negative (NO), the process proceeds to the next step 656. Furthermore, in steps 652 and 654, whether or not the engine is in an overspeed state is determined. The reason why different determination values of the predetermined upper limit and lower limit rotation speed are used for the determination is to stabilize engine control.

In step 656, it is determined whether the flag value N1 is equal to zero. The value of this flag N1 is set in step 204 or 206 in FIG.
If the determination result in step 6 is affirmative (Yes), it means that the engine speed Ne is in the extremely low speed range, and in such a case, the flag CRFLG is set to execute fixed ignition control, which will be described later.
to set the value to 1 (step 657), negative (NO)
In this case, the flag value CRFLG is set to the value O (step 658), and this flag value CRFLG is used for the determination in step 610 of FIG. Once the value of the flag CRFLG has been set, the execution of the subroutine NECHK ends and the process proceeds to step 614 in FIG.

In step 614, step 208 or 2 in FIG.
It is determined whether the value of flag N2 set in step 10 is 1 or not. If the result of this determination is affirmative (Yes), the process proceeds to the next step 615 without performing acceleration correction of the energization timing data Tcg and the ignition timing data Tig. On the other hand, if the determination result in step 614 is negative (No), step 6
At 70, subroutine TH8I is executed, and acceleration correction of ignition timing data Tig and energization timing data Tag is performed. The execution of this acceleration correction will be explained using the flowcharts of subroutines TH8I and TH8IA shown in FIGS. 9 and 10.

First, in step 671, it is determined whether the previous stage was stage 4 or not. This discrimination result is positive (
If Yes), the T s (n) value detected in step 603 and stored in step 611 is determined as the time required for the crankshaft to rotate by 90' crank angle in stage 4. Ts(n
) value divided by 2 is set as the T1 value (step 672)
. On the other hand, if the determination result in step 671 is negative (NO), the T s (n) value read in the previous stage is directly used as the T□ value (step 673). Next, in step 674, it is determined whether the stage before the previous one was stage 4 or not. If this determination result is positive (Yes), Ts(n-1
) The value read as the value was determined as the time required for the crankshaft to rotate through a crank angle of 90'' in stage 4, and the value obtained by dividing the Ts (nt) value by 2 is T.
On the other hand, if the determination result in step 674 is negative (No), the Ts(n-□) value read in the stage before the previous stage is used as the T2 value (step 676), and the next step is performed. In step 677, the difference ΔTs between the times T and T2 required for the crankshaft to rotate by a crank angle of 45 @ in the previous stage and the stage before the previous stage is determined, and in step 678, the absolute value 1ΔTsl of this difference is set to a predetermined value. It is determined whether the value is greater than the ΔMe value. If the result of this determination is (NO), it is determined that the acceleration or deceleration of the engine is not large, and the process proceeds directly to step 680. If the result is affirmative (Yes), the acceleration or deceleration of the engine in the previous stage is large, and the current stage However, it is determined that the acceleration or deceleration of the engine will continue to be large, and the difference Δ calculated in step 677 is added to the T1 value.
The value obtained by adding T is the latest T1 predicted at this stage.
If the value is set (step 679), the process proceeds to step 680. In step 680, the T1 value obtained as described above is
H! : W value, and time ΔT required for the crankshaft to rotate by the equivalent of 1° crank angle from the T s NtS value.
NI! Find e (step 681). .

Next, in step 682, subroutine TH8IA of FIG. 10 is executed. This subroutine TH8I
A is TSN! + Ignition timing data Tig and energization timing data Tcg based on w value and ΔT NEIJ value
First, in step 690, the ignition timing data Tig is recalculated. In this calculation, the above-mentioned ΔTNI:IJ value is applied as the Δτ value in the above formula (4) to obtain the latest Tig value. 6 Next, in step 691, it is determined whether the flag N3 is set to 1. .

If this determination result is negative (NO), that is, if the engine rotation speed Ne is equal to or less than the predetermined rotation speed N13Ac, then the ignition timing data Tig obtained by the above recalculation and the above T
s Further energization timing data Tcg based on the HHW value
Recalculation is performed using the above equation (5) used in the main routine. The determination result in step 691 is affirmative (
If Yes), the program is ended without recalculating the energization timing data Tcg, and the process proceeds to step 615 in FIG.

In step 615, the value of the variable STG representing the stage position is incremented by 1. This variable value STG corresponds to the stage number as described above, so when the value is incremented and reaches the value 8, it is updated to the value O.

This variable value STG is then used to determine the stage in the next loop.

Next, in step 616, the ignition timing data Tig stored in the RAM 32 is sent to the ignition counter circuit 36.
Set in the register. More specifically, the CPU 22 at step 616.

Ignition timing data Tig is stored in the first and second registers 38a and 38b (FIG. 3) of the counter circuit 36 as described below. First, the CPU 22 sends the upper 8 bits of the ignition timing data Tig onto the data bus 43, and then applies the latch signal AH to the pre-stage register 42 (FIG. 11). Then, the pre-stage register 42 stores the upper 8 bits of the Tig value data at the timing of applying the latch signal AH.Next, the CPU 22 sends the lower 8 bits of the Tig value data onto the data bus 43, and then outputs the latch signal AH. AL to the first and second register 3
8a and 38b at the same time (FIG. 11).

By applying this latch signal AL, the second register 38a
The lower 8 bits of the T i g value data sent out on the data bus 43 are simultaneously stored in the second register 38b, and the higher 8 bits stored in the previous register 42 are stored simultaneously. Therefore, the upper eight Tig values are stored in the second register without going through the previous stage register.
When storing the bit data and then the lower 8 bit data in the second register, the storage of the Tig value data requires at least the engine t' (11th ) was required, but if it is made to go through the pre-stage register 42 as described above, T
ig value data is stored in the register (store time t in Figure 11), and there is no need to worry about comparator malfunction during data storage.
There is no need for a program or a counter to confirm that the time t' required to rewrite the g value data is smaller than the time represented by the difference between the count value of the counter and the Tig value data already stored in the register.

In step 616 described above, the latest ignition timing data Tig, which has been accelerated and corrected by executing subroutine TH8T in step 650, is set in the ignition register unless the engine speed Ne is in the high rotation range. Also, as is clear from the above description, step 616
is always executed by executing the interrupt calculation program INT, so the Tig data is rewritten each time (FIG. 2(g)).

Step 618 of FIG. 7 is then executed. This step determines whether the flag value CUTFLG set in the above-mentioned subroutine NECHK is equal to the value 1. If the determination result is negative (No), step 619 will be described later.
The following steps are executed, but if the answer is Yes, that is, if an overspeed state of the engine is detected, the program ends without executing steps 619 and subsequent steps. Therefore, in the latter case, as will be described later, the ignition coil is no longer energized, thereby preventing ignition of the air-fuel mixture and preventing the engine from overspeeding.

In step 619, it is determined whether the current detection stage is an energized stage. This determination result is negative (No
), this interrupt processing is terminated without comparing the set value of the energization register 34a and the count value T of the energization counter 34 started in step 607, as will be described later.

Therefore, although the energization counter 34 was started in step 60, the CPU 22 at this stage
No energization signal is output to the first output circuit 24a. If the determination result in step 619 is affirmative (Yes), the process advances to step 620.

The energization timing data Tcg stored in the RAM 32 is set in the energization register 34a. And step 62
1, sets the CPU 22 to a state in which it is possible to accept re-interrupt processing, and also writes "0" to the 0N-PORT terminal 22a of the CPU 22.
” outputs the level. Since the above-described processing is essential in the interrupt processing shown in FIG. 7, even if the next interrupt request arrives during the program processing leading to step 620, it cannot be accepted. , step 62
After 0, receiving is possible. However, step 6
The execution of the program from step 01 to step 620 is executed at the next PCI even when the engine is being operated near the determination engine speed used to determine the overspeed of the engine speed Ne in steps 652 and 654 of FIG. Since the processing can be completed before a pulse is generated, a request for re-interruption processing does not normally occur during the execution of each processing in steps 601 to 620. Further, the "0" level appearing at the 0N-PORT terminal 22a of the CPU 22 puts the first output circuit 24a into a standby state via the energization signal line 40a as described above, and this standby state causes the first output circuit 24a to become in a standby state as described later. Energization to the ignition coil 45 can be started when the output of the ON-PORT terminal 22a is reversed from the "0" level to the "1" level.

Next, the process proceeds to step 622, where the count value T of the energization counter 34 is compared with the energization timing data Tcg,
Step 622 is repeatedly executed until the count value T matches the energization timing data Tcg.

That is, in the energization stage, until the energization time Tag passes, the interrupt processing program INT will not end unless there is a request for re-interrupt processing.

When the count value T exceeds the energization timing data T c g, C
The PU 22 outputs the "1" level to the 0N-PORT terminal 22a, and as described above, sends an energization signal to the first output circuit 24a to start energizing the primary coil of the first ignition coil 45 (step 623, (h) and ( in Figure 2)
i)), exit this program.

The above is the control procedure when there is no re-interrupt request after step 621, but the engine speed suddenly increases due to sudden acceleration and the next P
If a C1 pulse is generated, the process being executed is interrupted and step 601 is executed again. At this time, the determination result in step 601 becomes affirmative (Yss), and the process proceeds to step 62.

The stack point will be reset. That is, when the current re-interrupt request occurs, the stack point at the time when the re-interrupt request occurs, that is, the stack point at step 75, is stored in the stack register, but this stack point is The process is erased because it will not be executed again and there is no need to store it, and the stack point stored when the previous interrupt process request occurred is stored in the latest stack of the stack register. Therefore, when all the processing of the interrupt processing program INT executed by this re-interrupt is completed, the process will be returned to the stack point of the main program in Fig. 4 where the previous interrupt processing request occurred. .

Next, the process proceeds to step 606, where the CPU 22 is set to 0N.
- Outputs "1" level to the PORT terminal 22a and causes the first output circuit 24a to start energizing the first ignition coil 45. At this time, although the set energization timing Tcg has not yet arrived. By executing step 606, the first ignition coil 45 is forced to start being energized.

When application of a clock signal to the clock terminal GK of the first counter 39a is started in step 605 by the start signal from the CPU 22, the first counter 39a increments the count value by 1 every time a clock signal is input. The output of the most significant bit output terminal of the first counter 39a is [1
” level to the “0” level, the second
The count value of the counter 39b is incremented by one.

The first comparator 41a compares the counted value of the first counter 39a with the lower 8 bit data of the T i g value stored in the second register 38b, and when the two match, outputs a match signal to the second comparator 41b. do. on the other hand,
The second comparator 41b outputs the counted value of the second counter and the second
The upper 8 bits of the Tig value stored in the register 38b are compared, and when they match and the matching signal from the first comparator 41a is input, the power is turned on after detecting an abnormality in the output timing, which will be described later. A stop signal, ie, an ignition signal, is supplied to the first output circuit 24a, and the first
energization to the primary coil of the ignition coil 45 is stopped. As a result, a high voltage is generated in the secondary coil, spark discharge occurs in the ignition plug 10a, and ignition is performed.

The ignition signal from the second comparator 41b is also supplied to the first and second counters 39a, 39b and each reset terminal R of the R-S flip-flop 50, and the respective count values of the first and second counters 39a, 39b are supplied. is reset to zero, and the output of the Q output terminal of the flip-flop 50 is inverted to the "0" level, thereby closing the AND circuit 49. As a result, the first and second counters 39a, 39b
stops counting until the next start signal is input.

In the above embodiment, the present invention is applied to a counter circuit that counts the ignition timing data Tig, but the energization timing data Ta
An external Karatan circuit is provided for g.

The present invention may be applied to this. The registers shown in FIG. 3 are two registers 38a that process 8-bit data.
, 38b and the front-stage register 42, various modifications are possible. For example, four registers that process 4-bit data are used as the rear-stage registers, and four registers are used as the front-stage registers.
Three registers for processing bit data may be used. In this case, data divided into four bits from the most significant bit is sequentially stored in the three first-stage registers, and then the lowest four-bit data is stored in one of the second-stage registers. When the data is stored, the data stored in the three previous-stage registers are stored in the remaining subsequent-stage registers at the same timing.

Next, with reference to FIGS. 14 and 15, Il of FIG.
o - The configuration and operation of the fail-safe circuit 3o built in the LSI 21 will be explained.

In this embodiment, ignition control is performed for two systems of spark plugs 10a and 10b, but the output timing of one system of spark plugs 10a is monitored by the failsafe circuit 30, thereby controlling the output timing of the control device. An anomaly is detected.

Whether or not the output timing of the control device is abnormal is determined by the first pulse signal PC1 generated during one operation cycle, that is, one ignition cycle from consecutive ignition to ignition, in other words, the first flip-flop circuit. Pulse signal PA output from 27 (hereinafter referred to as "PA
The number of ignition pulses (referred to as "pulses") is counted three times, for example, during the current ignition, the previous ignition, and the time before the previous ignition, and when these champion count values have a predetermined numerical relationship, it is determined that there is an abnormality. If it is determined that there is an abnormality, a reset signal is output and the CPU
22 to prohibit execution of ignition. Examples of combinations of PA pulse count values when determining whether or not there is an abnormality will be explained with reference to Table 3.

First, the case where it is determined that there is no abnormality will be explained.

As shown in FIG. 1, on the circumference of the rotating disk 15,
Seven reactors 16a to 16g are arranged in one circuit, and during one ignition cycle from consecutive ignition to ignition, the first pulse signal PCI, in other words, the PA pulse, has a normal output timing and As long as the engine maintains a constant rotational speed, seven should occur. Therefore, as shown in column 4 of Table 3, the PA pulse count value is “7” at every detection.
”, it is determined that there is no abnormality in the output timing.

When the PA pulse count value is 6", the PA pulse signal generation sensation becomes narrower when the engine speed is in the high rotation range or during sudden acceleration, and the rise of the PA pulse and
There are cases where the PA pulses overlap with the counter reset signal described later due to non-synchronization, and these overlapping PA pulses are not counted. Therefore, as shown in the third column of Table 3, when the PA pulse number 6'' is counted continuously. As in the case of the PA pulse count value "7", it is determined that there is no abnormality in the output timing.

Next, a case where it is determined to be abnormal will be explained.

When the PA pulse count value is "4" or less, for example, when the engine speed Ne is extremely low, the pulsar 17
There may be an abnormal state in which a part of the pulse signal that should be induced is missing. If such a P^pulse count value is “4”
``In the following cases, the output timing is immediately determined to be abnormal as shown in the first column of Table 3.

If the PA pulse count value is 11571 or less, for example, the engine speed Ne is currently below a predetermined low speed and the ignition timing is initially locked at the TDC position.
Assume that the engine speed value Na increases until the next ignition timing, and the ignition timing of the method is at stage 6. In this manner, a state in which the PA pulse count value is "5" may occur once during control switching when the engine speed Ne increases from the angle lock state. However, considering that it is impossible for this state of PJ pulse count "5" to occur twice in a row, it is assumed that the count value of PA pulses is 1'5'' continuously as shown in the second column of Table 3. If it is detected twice, it is determined that the output timing of the control device is abnormal.

When the PA pulse count value is 11811, the 2nd ignition timing is initially at the crank angle position of stage number 6, and from this state the engine speed Ne suddenly decreases, the next stage number is 7, and the next stage is stage 1. , the number of PA pulses 118 t# may be counted twice in a row.

However, I think it is impossible for the number to be counted three times in a row. Therefore, when it is detected that the PA pulse count value is "8" three times in a row as shown in the fifth column of Table 3, it is determined that the output timing of the control device is abnormal.

When the PA pulse count value is a9#, the ignition timing is initially at the crank angle position of stage number 6, and from this state the engine speed Ne rapidly decreases and the next ignition is
Assume that the state has moved to the stage 1 position. In such a case, there may be a state where the PA pulse count value is "9" at least once. However, considering that it is impossible for the PA pulse count value 119 ## to be counted twice in a row, we confirmed that the PA pulse count value is tz 9 tp as shown in column 6 of Table 3. If it is detected twice, it is determined that the output timing is abnormal.

If the PA pulse count value is 10" or more, it is an effective determination in case of an abnormality such as when the input stage circuit has mistakenly taken in high voltage noise etc. as a pulse signal.Such a PA pulse meter If the numerical value is "10" or more, the crank angle position detection system immediately determines that there is an abnormality, as shown in column 7 of Table 3.

Next, with reference to FIG. 14, the internal configuration of the fail-safe circuit 30 that executes the above-described determination process will be explained in detail. The fail-safe circuit 30 includes a PA pulse counting function, a PA pulse counting function, and a PA pulse counting function.
A latch function that stores the pulse count value, a determination function that determines whether the three PA pulse count values are in a predetermined relationship,
Additionally, a circuit is provided which has various functions such as a function of outputting a reset signal when an abnormality is determined. That is, first, reference numeral 83 is a binary counter for counting PA pulses,
A PA pulse input line 84 is connected to the input terminal 83a. Reference numeral 85 is an input terminal for an ignition signal, 86
is an ST multiplied signal input terminal to be described later, which is inputted to the ignition signal and the ST multiplied signal OR gate 87, and the output terminal of this OR gate 87 is connected to the reset terminal R of the counter 83. A first register 88 for latching the previous PA pulse count value and a second register 88 for latching the previous PA pulse count value are connected in sequence to the four output terminals 01 to 04 of the counter 83. The first and second registers 88 and 89 have eight output terminals including a Q output terminal and a Q output terminal of a D flip-flop,
In the figure, only the output terminals with symbols Q1 to Q4 are shown.
The description of the symbols ˜C4 is omitted. The terminal between symbols 01 and 02 corresponds to Ql, and the terminal between symbols Q2 and Q3 corresponds to 2, etc., respectively. Reference numerals 90 and 91 are respective input terminals for a doubled signal for the previous PA pulse latch and a signal for the two previous PA pulse latches, which will be described later.The input terminal 90 is connected to the clock terminal GK of the first register via the two-man OR gate 82 , the input terminal 91 is connected to the clock terminal CK of the second register 89 via another two-way OR gate 81. The other input terminals of the above-mentioned two-manpower OR gates 82 and 81 are supplied with a power-on reset signal FOR1 generated immediately after the ignition switch (not shown) is turned on, and a reset signal RESET, which will be described later, and which is executed within the CPU 22. The input terminals of each signal of a watchdog timer clear signal W/TCLR for clearing the program when it runs out of control are connected through a three-way OR gate 80.

Here, the binary output values appearing at each output terminal of the counter 83 and the first and second registers 88 and 89 for the PA pulse count value are shown in Table 4.

Table 4 Then, from these output values, for the counter 83 and both the first and second registers, which output binary values as shown in the above table to each output terminal according to the PA pulse count value, Accordingly, the following circuits are provided to determine whether or not the output timing is abnormal.

First, a binary comparator 53 is connected to the output terminals 01 to 04 of the counter 83 to determine that a PA pulse of "4" or less is abnormal. AO to A3 in the comparator 53 are output terminals 01 to 04 of the counter 83, respectively.
Input terminal for PA pulse count value connected to BO-83
is the comparison setting value Ig41' setting terminal, and only the B2 terminal is
1'', rOJ is given to the other terminals, and a binary number rolooJ corresponding to 4'' is set.Input terminals AO to A
When the input value of the number of PA pulses from 3 is less than the set value PA4'', a signal ``1'' is output from the output terminal 53a.

Next, if the PA pulse count value is 5" abnormal, that is, in the case of columns 2 to 7jII of Table 3, the counter 83 and the 1. A group of ANDN-gates for decoding each binary output value of the second register (Table 4 above).
Logic circuits for comparing the outputs of the ND gates are arranged as follows.

First, the first register decodes the binary output value (Table 4) corresponding to the PA pulse count value tt 5 +t output from the counter 83 and the first register 88 and outputs "1".
, a second four-man AND gate 54,55 is provided. The (01) and (0°3) output terminals of the counter 83 are connected directly to the four input terminals of the first AND gate 54, and the (02) and (04) output terminals of the counter 83 are connected to the four input terminals through inverters 58b and 58d, respectively. and the second AND
The four input terminals of the gate 55 are supplied with ζl, Q2°Q3 . Each output terminal of Q4 is connected.

Reference numerals 56 and 57 denote third and fourth four-man-powered AND gates that decode the binary value (Table 4) corresponding to the PA pulse count value 1'91j and output "1". 3rd AN
Two of the four input terminals of the D gate 56 are connected to the (01) and (o4) output terminals of the counter 83, respectively, and the other two input terminals are connected to the (02) output terminal of the counter 83.
and (03) output terminals are inverters 58b and 58, respectively.
connected via c. Also, the fourth AND gate 5
Ql in the second register 46 is input to the 4 input terminals of 7.
,Q2゜Q3. Each output terminal of Q4 is connected.

The code 59.60.61 is a fifth unit that decodes the binary value corresponding to the PA pulse count value “6” and outputs “1”.
These are the sixth and seventh four-person AND gates. Fifth AN
Two of the four input terminals of the D gate 59 are connected to the (02) and (03) output terminals of the counter 83, respectively, and the other two input terminals are connected to the (ol) output terminals of the counter 83.
) and (04) output terminals are inverters 58a and 5, respectively.
8d. Further, the 4 input terminals of the sixth AND gate 60 are connected to the Q in the first register 88.
l, Q2. Q3. ? : Each output terminal of i4 is connected. Furthermore, the 4 input terminals of the seventh AND gate 61 have
ζ1 in second register 89. Q2゜Q3. Each output terminal of ζ4 is connected.

The code 63.64.65 is the PA pulse count value it 8
9. Decodes the binary value corresponding to n and outputs "1". These are the 10th and 11th four-person AND gates.

The (04) terminal of the counter 83 is connected to one input terminal among the four input terminals of the ninth AND gate, and the (01) (02) (03) terminal of the counter 83 is connected to the other three input terminals.
The output terminals are connected via inverters 58a, 58b and 58c, respectively. In addition, the four input terminals of the tenth AND gate 64 are connected to the Ql and ζ2 in the first register 88.
．． ζ3. Each output of Q4 is connected. Furthermore, a second register 89 is connected to the four input terminals of the eleventh AND gate 65.
Ql, Q2. Φ3. Each output terminal of ζ4 is connected. Both the tenth and eleventh AND gates 64.6
Each of the output terminals of 5 is connected to the input terminal of a 12th two-man power AND gate 66, and the surface outputs are further ANDed.

The 13th and 14th three-man-powered AND gates 67 and 68 set "1" immediately before the PA pulse count counted by the counter 83 changes from #10#j to 11'' by these two AND gates. Configure a decoder that outputs .

The (02) terminal of the counter 83 is connected to one of the three input terminals of the thirteenth AND gate 67,
The other two input terminals are (01) (0) of the counter 83.
3) The terminals are connected via inverters 58a and 58c, respectively. Furthermore, the three input terminals of the fourteenth AND gate 68 include a PA pulse input line 84 and a thirteenth AND gate.
The output terminal of the gate 67 and the (o4) output terminal of the counter 83 are connected to each other. When the PA pulse count value of the counter 83 is “10”, the fourteenth AND gate 68
The input terminals other than the terminals connected to the input line 84 of
1'' is input, and the fourteenth AND gate 68 is in a standby state.

When the eleventh pulse occurs on the input line 84, the fourteenth AND gate 68 is connected to the output terminal (0) of the counter 83.
1) Outputs "1" for a short period of time until "1" appears.

Furthermore, based on the output of each of the above AND gates, the first and second Logic circuits 69.70 are arranged. The first logic circuit 69 includes the inverter 58e and
It has an OR logic function, and similarly the second logic circuit 7
0, including the inverter 58f, has an AND-OR logic function. and 69 in the first logic circuit 69
Each input terminal of a and 69b has a second and a first AND
The output terminals of gates 55 and 54 are connected, respectively, and the output terminals of whistle 4 and third AND gate 57 and 56 are connected to input terminals of 69c and 69d, respectively.

On the other hand, the input terminal 70a in the second logic circuit 70 is grounded and receives "0" in this embodiment.
The output terminal of the fifth AND gate 59 is connected to the input terminal 78b. Further, the output terminals of the twelfth and ninth AND gates are connected to the input terminals 70c and 70d, respectively.

And furthermore, the above 1. After the second logic circuit 69.70, a three-man OR gate 71. which constitutes a reset signal output circuit. A flip-flop circuit 72, a two-man OR gate 76, etc. are sequentially arranged. The three input terminals of the OR gate 71 are connected to the output terminal 53a of the comparator 53 and both output lines of the first and second logic circuits 69 and 70 via inverters 58e and 58f, respectively. .

Further, the output terminal of the OR gate 71 is connected to the D input terminal of the flip-flop circuit 72, and the Q output terminal of this flip-flop circuit 72 is connected to the two-way OR gate 76.
is connected to one input terminal of the terminal. The output terminal of the fourteenth AND gate 68 is connected to the other input terminal of the OR gate 76. A reset signal output terminal for resetting the CPU 22 is led out from this OR gate 76. Reference numeral 73 is an input terminal for a previous OUT signal, which will be described later, and serves as a timing signal for fail detection;
Reference numeral 74 denotes an ST multiplier signal input terminal, which will be described later. Both input terminals 73 and 74 are connected to both input terminals of a fifteenth two-man power AND gate 75, and an output terminal of the fifteenth AND gate 75 is connected to the flip-flop circuit 72. clock terminal G
connected to K.

Reference numeral 78 denotes a fail reset circuit, which introduces an output signal from the Q output terminal of the flip-flop circuit 72, in other words, a reset signal when an abnormality is determined, and further outputs a predetermined number of clock pulses from the time when this reset signal is input. After the predetermined counted time has elapsed, the three-man OR gate 7
9 to send a reset signal to the flip-flop circuit 72. 3 in OR gate 79
The other two input terminals of the input terminals are connected to the input terminals of the power-on reset signal FOR and the watchdog timer clear signal W/TCLR similar to those described above.

Next, the operation of the fail-safe circuit 30 described above will be explained.

When the engine's ignition switch (not shown) is opened (turned on), power is started to be supplied to the ECU 2 shown in Fig. 1. Immediately after the start of this power supply, an ST multiplication signal at the "1" level, which will be described later, is output. When the power supply voltage reaches a predetermined level, only one pulse of the power-on reset signal FOR is output.

This ST signal 86 initializes the counter 83 and
The OR signal is applied to each CK of the first and second registers 88 and 89.
A command is input to the terminal to read the PA pulse count value, but since the counter 83 has just been reset by the g times signal as described above, the contents of the first and second registers 88 and 89 are cleared to 0. is equivalent to FOR
The signal is provided to flip-flop circuit 72 to reset it.

Next, when initialization of the CPU 22, such as clearing registers and setting initial values of variables, is completed by the above-mentioned supply, the CPU 22 outputs an ST times signal of the "1" level, but the CPU 22
Until the initialization of U22 is completed, the ST double signal rOJ is at the level, and the blue signal, which is the inverted ST double signal, is at the "1" level as described above. The two-man power AND gate 75 is held in an operation standby state by the ST multiplication signal after initialization is completed.

In this state, when a PA pulse appears on the input line 84, the counter 83 starts counting the number of PA pulses generated, and
The output terminal (0
1) to (04) are changed. The count value of the ignition counter (not shown) mentioned above is the ignition timing data Ti.
g, the synchronization pulse generation circuit (not shown) of the Ilo LSI 21 generates four synchronization pulse signals, namely the previous OUT signal (FIG. 15(e)), the two-previous PA pulse count latch signal (hereinafter referred to as the "previous PA The same figure (f) called “Latch signal”)
, the previous PA pulse count latch signal (hereinafter referred to as the "previous PA rarity signal" (1fW(g)), and the OUT signal ((h) in the same figure) are generated in this order in this order.The previous OUT signal is in a standby state. The flip-flop circuit 72 is input to the other terminal of the AND gate 75 at this input timing.
A "1" level is supplied to the clock terminal CK of the . The flip-flop circuit 72 sets "1" to its clock terminal CK.
When the terminal input is at the "0" level while the level is being input, that is, the PA pulse count values detected this time, last time, and the time before the time shown in Table 3 above are in a predetermined numerical relationship indicating an abnormality. If not, the Q output terminal is held at the rOJ level. Next, the pre-previous PA latch signal is supplied to the clock terminal CK of the second register 89 via the OR circuit 81. At the timing when this two-day-before PA latch signal ((f) in the same figure) is input to the clock terminal GK of the second register 89, the previous PA pulse count value latched in the first register 88 is transferred to the second register. The previous PA pulse count value ((k) in the same figure) is latched as the PA pulse count value from the previous time, and then the previous PA clutch number ((g) in the same figure) is input to the clock terminal CK of the first register 88, and at this timing, the counter 83 The current PA pulse count value counted in is latched in the first register 83 as the previous PA pulse count value (
Same figure (j)). The counter 83 is reset by the OUT signal ((k) in the same figure) generated immediately after the latching action on the first register 83, and the new current PA of the primary
While counting the number of pulses is started, this OUT signal causes the output circuit 24a to output the ignition signal.

On the other hand, between the count values of each PA pulse of this time, last time, and the time before last, 1. When the numerical relationships shown in the second, fifth, sixth, and seventh columns are established, for example, when the PA pulse count value in the first column of Table 3 is equal to or less than R4It, the output terminal 53a of the comparator 53 A “1” signal is output from
This is connected to the flip-flop circuit 7 via the OR gate 71.
rl'' is led to the D input terminal of 2. Furthermore, when the PA pulse count value 115 Te in the second column of Table 3 is detected twice in a row, "1" is output from both the first and second AND gates 54.55, and this logic circuit 69
input to the surface input terminals 69a and 69b, and the logic circuit 69 outputs "1" via the inverter 58e.
D of the flip-flop circuit 72 via the OR gate 71
"1" is led to the input terminal. In the case where the numerical relationships in the fifth, sixth, and seventh columns other than the first and second columns of Table 3 above are established, the D of the flip-flop circuit 72 is
"1" is led to the input terminal. Therefore, the previous OUT signal (
A "1" signal is input to the clock terminal CK of the flip-flop circuit 72 at the timing shown in FIG. 15(e)), and the Q
A "1" signal, which is an abnormality determination signal, is output from the output terminal, and based on this "1" signal, a reset signal is output from the OR gate 76, and the CPU 22 is reset.

In this way, it is accurately detected whether the output timing of the control device is abnormal or not based on the current PA pulse count value and the PA pulse count values counted before this time without misdiagnosis.

When it is determined that there is an abnormality and the CPU 22 is reset by the RESET signal, the CPU 22 outputs the ST double signal rOJ.
The double signal is inverted to "1", and the counter 83 is reset by the inverted ST double signal in the same manner as immediately after the ignition switch is opened (on). RESET signal is O
First and second registers 88.8 via R gate 80
Each of the 9 CK terminals ↓ is also supplied, and the contents of these registers are also reset to zero. After the CPU 22 etc. are reset in this way, when a predetermined period of time has elapsed, the flip-flop circuit 72 is reset by a fail reset signal from the 7-factor reset circuit 78, and the reset signal from the output terminal 77 disappears, resetting the CPU 22. is released,
It is also supplied to each reset terminal R of the R-S flip-flop 5o which has recovered to the "1" level, and resets each count value of the first and second counters 39a, 39b to zero, and also outputs the Q output terminal of the flip-flop 50. The output is inverted to OJ level and the AND circuit 49 is opened. As a result, the first and second counters 39a and 39b stop counting until the next activation signal is input.

Note that the processing of the energization timing and ignition timing for the ignition plug 10b on the other cylinder side is also substantially the same as above, except for the energization and ignition stages, so a description thereof will be omitted.

FIG. 12 shows a flowchart of a fixed ignition control subroutine CRNK according to the present invention executed in step 630 of FIG. First, in step 631 of FIG.

It is determined whether the stage of the loop this time is stage 7, and if the answer is positive (Yes), energization to the first ignition coil 45 is started (Step 632), negative (No).
), the process advances to the next step 633.

In step 633, it is determined whether the current stage is stage 1 or not. If the answer is affirmative (Yes), the energization to the first ignition coil 45 is stopped and the first spark plug 10a is ignited (step 634), that is, the first
As shown in FIG. 3(f), at the same time as the first pulse signal PCI7 (FIG. 13(a)) indicating stage 7 is detected, energization to the first ignition coil 45 is started, and the first pulse signal PCI7 indicating stage 1 is detected. At the same time as the first pulse signal PCII is detected, the current supply is stopped and the first spark plug loa is ignited.

On the other hand, if the answer to step 633 is negative (NO), the process advances to the next step 635.

In step 635, the current stage of the loop is stage 4.
If the answer is affirmative (Yes), as shown in FIG. 13(g), the second ignition coil 4
6 (step 636), and it is determined whether the time value T ve of the Me counter 47 restarted in step 603 of FIG. 7 has reached a predetermined value (for example, 50 m5ec).

If the answer is negative (No), that is, if the predetermined value has not yet been reached, the process proceeds to step 638, where the Q output (FIG. 13(d)) of the second flip-flop circuit 28 is
It is determined whether the spark plug is at the Hlj level or not, and if it is at the 11 Hu level, that is, the second spark plug 10 at stage 4
When the second pulse signal PC2M (Fig. 13(b)) generated substantially at the top dead center position of the cylinder on the b side is detected, the energization to the second ignition coil 46 is stopped and the second The spark plug 10b is ignited (step 639). In this embodiment, since the present invention is applied to an engine in which the top dead centers of the cylinders are separated by 180°, the PC2M pulse is
After the pulse is generated, the pulse is generated at a position rotated by a crank angle of approximately 45 degrees, but in an engine in which the top dead center interval is different from that of the above-mentioned embodiment, the second pulsar 18 is set to match the top dead center interval of the engine. By arranging it at a position apart from the pulsar 17, it is possible to ignite at any crank angle position that is substantially the same as the top dead center position of the cylinder corresponding to the second spark plug.

On the other hand, if the answer to step 638 is negative (No), that is, if the pulse signal PC2M has not been detected yet,
The process returns to step 637 and waits while continuing to energize the second ignition coil 46 until the pulse signal PC2M is detected. However, if the time value of the Me counter 47 reaches a predetermined value (50 m5ec) during this waiting period (the answer to step 637 is affirmative (Yes)), step 640
Proceed to.

The second ignition prohibition process inhibits the ignition of the spark plug by gradually decreasing the current in the secondary coil of the ignition coil.
ignition coil 46. The reason for this is that the time from detecting the second pulse signal PC24 (FIG. 13(b)) indicating stage 4 to detecting the pulse signal PC2M is at most 37, 5m5ec. Therefore, even after 50m5ec has elapsed, the Q output of the second flip-flop circuit 28 is
IL" level means that the pulse signal PC2M
Indicates that detection has failed. And this loss is
This occurs more easily when the engine speed Ne decreases and the output level of the pulse signal PC2M decreases. Therefore, a second pulse signal PC25 indicating stage 5 (FIG. 13(b)
) or the second pulse signal PC2 generated thereafter, the ignition prohibition process is performed in order to prevent ignition during an undesirable engine operation stroke.

Returning again to the case of the fixed ignition control on the first spark plug side executed in steps 631 to 634, the first ignition coil in step 632 is executed in response to the interrupt processing of the pulse signal PC17. If the pulse signal PCII is not detected after the start of energization of 45, the pulse signal P
The first pulse signal PC generated at or after C12
Step 6 in FIG.
If the engine speed Ne is below the predetermined speed NIGSTO (200 rpm) based on the Tsi-1 value measured in step 03, the answer to step 608 in FIG. Ignition prohibition processing is performed, and in this case as well, adverse effects on the engine due to faulty ignition are prevented.

Incidentally, when it is determined in step 610 of FIG. 7 that the CRFLG value is equal to the value 1, the ignition counter started in step 605 of FIG. 7 is subjected to a process of stopping its operation or invalidating its output signal.

The AND gate 75 is put into a standby state again by the ST multiplication signal. In addition, if it is determined that there is an abnormality after the ignition coil 21.22 is energized, the primary current of the ignition coil 21.22 is gradually reduced by a soft-off means (not shown) to reduce the induced electromotive force on the secondary side. This prevents spark discharge from the spark plugs 10a and LOb.

Note that the combination of PA pulse count values that are considered to be abnormal conditions in Table 3 can be set arbitrarily.

(Effects of the Invention) As described in detail above, according to the ignition timing control method for an internal combustion engine of the present invention, the first and second position detection means are set to substantially the top dead center of each cylinder whose ignition order is one after the other. are arranged to be separated by an angle corresponding to a crank angle between the cylinders, and when the first position detecting means detects a predetermined angular position, ignition of one of the cylinders is executed, while the first position detecting means When the second position detecting means detects the angular position after the means detects the angular position immediately before the missing portion, the other cylinder is ignited, so that each cylinder is at a predetermined crank angular position. It is possible to carry out ignition, and the first
Moreover, the present invention can be applied to various types of engines simply by separating the second position detection means by the distance between top dead centers.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of an electronic ignition control device for an internal combustion engine in which the present invention is implemented, and FIG. 2 shows pulse signals PCI, P detected by first and second position detection means (pulsar).
A timing chart showing the occurrence timing of C2, energization timing to the ignition coil, energization stop timing (ignition timing), etc., FIG. Figure 4 shows the central processing unit in Figure 1 (
FIG. 5 is a flowchart showing the crank angle reference position detection procedure immediately after starting the internal combustion engine, which is executed in step 100 of FIG. 4, and FIG. Step 2 in the diagram
FIG. 7 is a flowchart illustrating in detail the processing contents of No. 00, and FIG. 7 is a flowchart showing control procedures such as 1 energization timing, energization stop timing (ignition timing), etc., which are interruptedly executed every time a predetermined crank angle position is detected. Figure 8 shows the interrupt processing program IN'r''17 in Figure 7.
A flowchart detailing the processing content of step 650;
9 is a flowchart of the subroutine THS I that details the processing contents of step 670 of the interrupt processing program INT of FIG. 7, and FIG. 10 is a flowchart of the subroutine THSI of FIG. 9.
8I is a flowchart of subroutine TH3IA detailing the processing contents of step 682, FIG. 11 is a timing chart showing the timing at which data is stored in the register of FIG. 2, and FIG. 12 is a processing content of step 630 of FIG. 7. FIG. 13 is a timing chart showing the energization timing to the ignition coil, the energization stop timing (ignition timing), etc. when fixed ignition control is executed, and FIG. 14 is a flowchart of the subroutine CRNK explaining in detail A first circuit diagram showing an example of the fail-safe circuit 30 in further detail.
FIG. 5 is a timing chart showing each signal waveform, etc. in the above fail-safe circuit. 1... Engine, 10a, 10b... Spark plug,
14... Crankshaft, 17.18... First and second pulsers, 24... CPU, 31... ROM, 32...
...RAM.

Claims (1)

[Claims] 1. Detecting a plurality of angular positions arranged at equal intervals with one missing portion on the circumference of the output shaft of the internal combustion engine by first and second position detection means located at different circumferential positions, When the second position detecting means does not detect the angular position while the first position detecting means detects the adjacent previous angular position and subsequent angular position, the latter angular position is used as the reference crank angular position. In the ignition timing control method, in which ignition is executed when a predetermined number of angular positions are detected after the reference crank angular position is detected, the first and second position detection means are connected to the top of each of two cylinders whose ignition order is sequential. arranged at an angle corresponding to a crank angle between dead centers, and when the first position detection means detects a predetermined angular position, ignition of one of the cylinders is performed, while the first position is Ignition timing control for an internal combustion engine, characterized in that when the second position detecting means detects the angular position after the detecting means detects the angular position immediately before the cutout part, ignition of the other cylinder is performed. Method.