JPS6262091B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synthesizer receiver using a PLL as a local oscillation circuit, and in particular to a technique for making the change characteristics of the local oscillation frequency and the change characteristics of a high frequency tuning circuit have the same tendency.

In a receiver, it is necessary to change the high frequency tuning frequency with the same tendency according to the local oscillation frequency, but in conventional synthesizer receivers, the frequency determining element of the variable frequency oscillator of the local oscillator circuit, such as a variable capacitance diode, The applied DC voltage is also applied to a frequency determining element for determining the tuning frequency of the high frequency tuning circuit, such as a variable capacitance diode.

However, in this conventional configuration, it was necessary to provide a padding capacitor for frequency band correction in the high frequency tuning circuit. Furthermore, it was necessary as a precondition that the characteristics of the variable capacitance diodes in both circuits be the same.

In view of the above points, this invention does not require a padding capacitor in the high frequency tuning circuit, and
It is an object of the present invention to provide a receiver in which the tendency of frequency change of a local oscillation frequency and a high frequency tuning frequency becomes similar even if the characteristics of a frequency determining element, such as a variable capacitance diode, do not match.

Hereinafter, an example of a receiver according to the present invention will be explained with reference to the drawings.

In FIG. 1, 1 is a high frequency tuning circuit, 2 is a high frequency amplifier, 3 is a mixer circuit, 4 is a local oscillation circuit, 5 is an intermediate frequency amplifier, 6 is an AM detection circuit, and 7
is a low frequency amplifier, and 8 is a speaker.

Further, 10 indicates a PLL. That is, 11 is a reference oscillation circuit, from which a reference signal of, for example, 3.6MHz is obtained, and this signal is supplied to the frequency divider circuit 12 to form a frequency-divided signal D _S with a frequency of 9kHz. The frequency signal D _S is supplied to the phase comparator circuit 13 .

Further, in this case, the local oscillation circuit 4 is constituted by a variable frequency oscillator VCO, and the oscillation signal of this local oscillation circuit 4 is supplied to the programmable frequency divider circuit 14 and frequency-divided to 1/N frequency, and the frequency-divided signal is is supplied to the phase comparison circuit 13, and its comparison output is supplied to the variable capacitance diode of the local oscillation circuit 4 as its control voltage.

Therefore, the frequency of the output signal of the frequency dividing circuit 14 is equal to the frequency of the frequency divided signal D _S of 9kHz, so the oscillation frequency of the local oscillation circuit 4 at this time is N
×9kHz, and the broadcast wave with a frequency of N×9−450kHz is converted to an intermediate frequency of 450kHz. Therefore, the frequency division ratio N of the frequency dividing circuit 14 is N=109
If you change it by 1 between ~229, 531kHz ~ 1611k
Can receive Hz band in 9kHz steps.

20 is a channel selection control circuit for setting the frequency division ratio N of the frequency dividing circuit 14 and selecting a desired broadcast.

In this example, the channel selection control circuit 20 is configured as a microcomputer, and 21 is configured as a microcomputer.
CPU, 22 is ROM in which a program to control the operation of this receiver is written, 23 is RAM, 24
and 25 are interfaces.

Further, S _U is an up switch for scanning the received frequency in the upward direction, S _D is a down switch for scanning in the downward direction, and S ₁ to S ₈ are the first
~ Tuning switch for selecting the 8th channel, S _M
is a memory switch for storing broadcast frequency data. Note that these switches are all normally open switches, and the hot side is pulled up inside the CPU 21.

Further, numeral 9 is a detection circuit that detects and shapes the intermediate frequency signal to detect the presence or absence of broadcasting. When receiving broadcasting, this detection circuit 9 obtains an output of level "1", which is supplied to the CPU 21.

For example, when the up switch S _U is turned on, the N value information of the frequency division ratio 1/N of the frequency dividing circuit 14 from the CPU 21 increases by 1, and therefore,
The frequency division ratio also increases by one. Therefore, the receiving frequency increases one step at a time, 9kHz at a time.

If a broadcast can be received when a certain frequency _i is reached, the output of the detection circuit 9 will be "1" at that time, so the N value information from the CPU 21 will stop at that point, and from then on, the frequency The reception state at _i continues.

When receiving this, if you turn on any of the channel selection switches _S1 to _S8 while turning on the memory switch _SM , the N value information at this time will be
It is written to the corresponding memory address in RAM23.

When switch S _U is turned on again, the receiving frequency increases again by one step.

Furthermore, when the down switch S _D is turned on, the N value information decreases by 1, and therefore the frequency division ratio of the frequency dividing circuit 14 decreases by 1, and the reception frequency decreases by 1 step. If the broadcast wave can be received, the N value is fixed to the value at that time by the output of the detection circuit 9.

In this way, by operating the switches S _U and _SD , the reception frequency is scanned, a broadcast wave of an arbitrary frequency is selected, and the switch S
By the operations of _M , _S1 to _S8 , the N value information for the broadcast wave is written to the corresponding memory address of the RAM 23.

Therefore, if you turn on any of the channel selection switches S ₁ to _{S 8} after that, the RAM 23
The N-value information is read out, the frequency division ratio of the frequency divider circuit 14 is determined, and the broadcast reception state of the corresponding frequency is entered.

The above operations are performed according to the program written in the ROM 22.

In the present invention, the local oscillation frequency is determined as described above. N value information from the CPU 21 is supplied to the D/A conversion circuit 30 through the interface 25, from which a DC voltage corresponding to the N value is obtained, and this is supplied to, for example, a variable capacitance diode of the high frequency tuning circuit 1 as its control voltage. be done.

In this case, in the D/A conversion circuit 30, the N-value information is Weighting is performed during A conversion.

As described above, according to the present invention, the local oscillation circuit
Phase comparator circuit 13 that controls the frequency of VCO 14
Rather than controlling the tuning frequency of the high-frequency tuning circuit 1 by the comparative output voltage of the
Since the converted DC voltage is used for control, even if the characteristics of the variable capacitance diodes in both circuits are different, it is easy to change the high frequency tuning frequency with the same tendency according to the local oscillation frequency. Can be done.

Another advantage is that a padding capacitor becomes unnecessary.

By the way, in the case of a wideband receiver whose reception band ranges from 100kHz to 30MHz, if the local oscillation frequency is set to a high frequency as an upper heterodyne, the local oscillation frequency can cover a band of 30MHz with one variable capacitance diode and one coil. It can cover high frequency tuning frequency, i.e.
100kHz to 30MHz with one variable capacitance diode and one
It cannot be covered with one coil. Moreover, in conventional receivers, as mentioned at the beginning, both the local oscillation frequency and the high frequency tuning frequency are controlled by the comparison output of the phase comparison circuit of the PLL, so only the high frequency tuning circuit side is divided into bands. I couldn't control it.

Therefore, in the past, it was necessary to perform band division not only on the high frequency tuning circuit side but also on the local oscillation circuit side, resulting in a complicated configuration.

In contrast, in the case of the present invention, the tuning frequency of the high frequency tuning circuit and the local oscillation frequency of the local oscillation circuit are controlled by different control voltages, so the frequency determining circuit of the local oscillation circuit is divided into bands. The frequency determining circuit of the high frequency tuning circuit is composed of one variable capacitance diode and one variable capacitance diode, and the frequency determining circuit of the high frequency tuning circuit is composed of multiple coils corresponding to the number of band divisions and one variable capacitance diode. Configure it to switch to . Therefore, the configuration of the receiver can be simplified.
In this case, the reception band is, for example, ₁ to ₂ , ₂
~ ₃ , ₃ ~ ₄ , ₄ ~ ₅ , ₅ ~ ₆ ,
When there are 6 bands from ₆ to ₇ , the ratio of the lowest frequency _nio to the highest frequency _nax of each band is constant, that is, _nax / _nio = ₂ / ₁ = ₃ / ₂ = ₄ /
Frequencies ₁ to ₇ are selected so that ₃ = ₅ / ₄ = ₆ / ₅ = ₇ / ₆ = constant.

Then, in the D/A conversion circuit, calculation processing is performed so that the DC output voltage value at the N value for the lowest frequency of each band and the DC output voltage value at the N value for the highest frequency become the same value in each band. Make it. Alternatively, the information supplied from the CPU 21 to the D/A conversion circuit 30 is already standardized for each band as described above.

In this way, the output of the D/A conversion circuit supplied to the high frequency tuning circuit will be ₁ to 2, ₂ to ₂ in each band, as shown in FIG.
_{3 , 3-4 , 4-5} , _{5-6 , 6}
~ ₇ , the DC voltage has the same characteristics.

Therefore, when changing the band by switching the coil of the high frequency tuning circuit, the output of the D/A converter circuit increases or decreases at the same rate as the N value increases or decreases in each band, so the local Even if the oscillation circuit side is not divided into bands and is composed of one variable capacitance diode and one coil, the local oscillation frequency and the high frequency tuning frequency follow and change in each band.

Of course, the characteristics of the variable capacitance diode used in the high frequency tuning circuit are taken into consideration when weighting is performed in the D/A conversion circuit.

In this case, the band switching may be done manually, or it may be done automatically by dividing the N value according to the band and obtaining a signal from the CPU 21 to switch the coils accordingly.

In addition, in the case of wideband reception, a double superheterodyne system is usually adopted, but if both the first and second local oscillation circuits have a PLL configuration, the frequency division ratio N The value information includes N ₁ , the frequency division ratio of the first PLL, and
Needless to say, both the frequency division ratio _N2 of the PLL must be taken into consideration.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of an example of a receiver according to the present invention, and FIG. 2 is a diagram for explaining the configuration of main parts of another example of the invention. 1 is a high frequency tuning circuit, 4 is a local oscillation circuit, 10
is a PLL, 14 is a programmable frequency divider circuit, and 21 is a PLL.
The CPU 30 is a D/A conversion circuit.

Claims (1)

[Scope of Claims] 1 a. A local oscillation circuit composed of a PLL including a variable frequency oscillator having one variable capacitance diode and one coil as a frequency determining element and a programmable frequency divider; b. means for supplying the frequency divider with an N value that determines its frequency division ratio of 1/N; c a D/A that converts the N value from this means;
a conversion means; d one variable capacitance diode to which the N-value D/A conversion output is supplied; and a plurality of coils for the number of bands that together with this variable capacitance diode determine the tuning frequency and are switched in response to band switching; and a high frequency tuning circuit comprising e a constant ratio between the highest frequency and the lowest frequency of each of the divided bands, and f a direct current voltage having the same characteristics in each band from the D/A conversion means. A receiver made so that it can be obtained.