JPS6260846B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog signal amplification circuit suitable for use as an interface between an analog signal circuit and a digital signal circuit, and particularly to a circuit that reduces the influence of noise in the amplification circuit.

Since analog signal amplification circuits generally generate noise during operation, signals below the noise level cannot be amplified with a good signal-to-noise ratio. However, when this is limited to circuits used for the interface between analog signal circuits and digital signal circuits, the following phenomenon occurs. That is, since the noise component of the analog signal amplification circuit is inversely proportional to the frequency, when the amplifier circuit starts operating, the high frequency component appears for the first time, and then the low frequency component appears.

The present invention focuses on the fact that the SN ratio can be further improved regarding these noises. That is, the present invention provides an analog signal amplification circuit.
The purpose is to improve the signal-to-noise ratio.

The present invention includes an impedance control circuit whose impedance changes in order to change the magnitude of the voltage gain of the amplifier in parallel with the output load of the amplifier, and which controls the impedance control circuit by a pulse signal synchronized with an input signal. The output circuit operates to obtain a low-noise output immediately after changing the impedance from low impedance to high impedance and increasing the gain of the amplifier.

This will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of a circuit according to an embodiment of the present invention. In this example, the present invention is implemented in a circuit that compares a periodically changing analog signal voltage Va with a reference voltage V _REF and outputs the magnitude relationship as a binary signal.

An analog signal Va is periodically sent out from a signal source 1 and is coupled to one input of a differential amplifier 2 . A reference voltage V _REF is applied to the other input of the differential amplifier 2 . Further, the output of this differential amplifier 2 is given to a level conversion circuit 3 and branched, and an impedance control circuit 4
guided by. This impedance control circuit 4
As will be described later, the impedance value seen at both ends of the circuit changes in a switch-like manner.
The output of the level conversion circuit 3 is led to an output terminal via a latch circuit 5. Here, the signal source 1, level conversion circuit 3, impedance control circuit 4 and latch circuit 5 are all supplied with synchronized clock signals. Flip-flop 6 is a circuit for adjusting the delay time and pulse width of this clock signal.

The operation of the circuit configured in this way will be explained.
Differential amplifier 2 has a large gain, and the input analog signal
Let us consider the case where Va is weak and close to the noise level generated by the differential amplifier 2.

FIG. 2a shows the waveform of the input analog signal Va, which is a voltage signal that changes at regular intervals with respect to the reference voltage V _REF . The period from t ₀ to _{t 2} of the input analog signal in FIG. 2a will be explained in detail below using an enlarged diagram.

FIG. 2b shows the output response waveform of the differential amplifier 2 when the differential amplifier 2 is ideal and does not generate noise. At t ₁ the input signal changes, and at t ₂ it has been amplified to a voltage value sufficient to operate the level conversion circuit.

However, in reality, the differential amplifier circuit 2 generates noise, so in the case of a conventional circuit without the impedance control circuit 4, as shown in FIG.
The response waveform is a waveform with noise superimposed on it. As in the case of FIG. 2c, if the difference between the input signal voltage Va and V _REF is small, it becomes impossible to determine the magnitude of the amplified response waveform with respect to V _REF .

On the other hand, when there is no voltage difference between the inputs of the differential amplifier 2, the impedance control circuit 4 changes from low impedance to high impedance at time _t1 ,
The noise waveform immediately after the differential amplifier 2 increases the gain is as shown in FIG. 2d. This is because, as is well known, the noise generated by the amplifier is a noise whose component is inversely proportional to the frequency, so that low frequency components with a large amount of noise rise slowly.

In other words, by focusing on the fact that the rising speed of the noise component is slower than the response speed of the differential amplifier 2 to the input voltage, noise can be avoided. Figure 2 e
is the response waveform of the differential amplifier circuit 2 when the delay time of the flip-flop 6 is zero and when the impedance control circuit 4 is made high impedance at time _t1 and the input signal changes at the same time. In this response waveform, before the noise component rises significantly,
By operating the level conversion circuit 3 at time _t1 , the output of the differential amplifier 2 can be detected with less noise. When looking at the rise time of this noise for a general analog differential amplifier, it is 100 μS.
~1 mS, and the response speed to the input signal is about 100 nS with a relatively high-speed differential amplifier.

Figures 2f and 2g show the voltage waveforms of the input signal Va and the output of the differential amplifier 2 when there is a delay in the flip-flop 6 (Figure f' is an enlarged view of Figure f).
Even if the time t _H at which the impedance control circuit 4 becomes high impedance is later than t ₁ , it operates in the same way. However, g is twice as large as e.

FIG. 3 shows an example of the configuration of the impedance control circuit. FIG. 3a shows a P-channel MIS type field effect transistor. The impedance between the source and drain can be controlled by a lock control signal applied to the gate terminal.

Figure 3b shows one P-channel MIS field effect transistor connected in series with the source
Another P channel shorted between drains
This is an example configured with MIS type field effect transistors. This is the circuit shown in Figure 3a, which is constructed to prevent the clock control signal from leaking to the amplifier output. That is, a clock signal of an opposite phase is applied to the gate of a field effect transistor whose source and drain are short-circuited, thereby canceling out the leaking clock signal.

The same applies to FIG. 3c, which is configured to provide an opposite phase clock signal via a capacitor C corresponding to the gate capacitance of the field effect transistor.

The example shown in FIG. 3d uses so-called complementary MIS field effect transistors, and leakage of the clock control signal is canceled out.

In addition, the impedance control circuit can be configured in various ways using N-channel field effect transistors, bipolar transistors, etc., and the present invention can also be implemented using these.

In the above example, the analog signal voltage is compared with the reference signal voltage and a binary signal is obtained as the output. However, in addition to the above example, the present invention can be implemented in an interface between an analog signal circuit and a digital signal. Can be done. Furthermore, in the above example, the input signal is periodic and the control is performed in synchronization with the clock signal, but the input signal does not necessarily have to be periodic, and if a control signal synchronized with this input signal can be obtained, The invention can be implemented in a similar manner.

As described above, according to the present invention, a circuit that can effectively improve the SN ratio of an analog signal amplification circuit can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining operation, and FIG. 3 is a configuration example diagram of an impedance control circuit. DESCRIPTION OF SYMBOLS 1... Signal source, 2... Differential amplifier, 3... Level converter, 4... Impedance control circuit, 5...
...Latch circuit, 6...Flip-flop.

Claims (1)

[Claims] 1. An analog amplifier, an impedance control circuit connected to the output of this amplifier in parallel with a load, and whose impedance changes in a switch-like manner in order to change the magnitude of the voltage gain of this amplifier by a control signal synchronized with the input signal of this amplifier; and an output circuit for extracting an output signal of the amplifier immediately after the impedance control circuit changes from low impedance to high impedance.