JPS6259556B2 - - Google Patents
Info
- Publication number
- JPS6259556B2 JPS6259556B2 JP57151402A JP15140282A JPS6259556B2 JP S6259556 B2 JPS6259556 B2 JP S6259556B2 JP 57151402 A JP57151402 A JP 57151402A JP 15140282 A JP15140282 A JP 15140282A JP S6259556 B2 JPS6259556 B2 JP S6259556B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- bias
- current
- absolute value
- abnormal operation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 22
- 230000002159 abnormal effect Effects 0.000 claims description 11
- 230000005856 abnormality Effects 0.000 description 11
- 239000003638 chemical reducing agent Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P5/00—Arrangements specially adapted for regulating or controlling the speed or torque of two or more electric motors
- H02P5/46—Arrangements specially adapted for regulating or controlling the speed or torque of two or more electric motors for speed regulation of two or more dynamo-electric motors in relation to one another
Description
【発明の詳細な説明】
本発明な二系統の駆動制御系を並列に駆動する
場合の異常動作検出方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an abnormal operation detection method when two drive control systems are driven in parallel.
従来から電動機と、クラツチと、減速機と、ピ
ニオンとから構成された駆動制御系を二系統使用
し、それらを並列駆動することにより可動部材を
回転駆動制御するサーボ系駆動装置の異常動作を
検知する方式としては二系統より成る駆動制御系
の各電動機に流れる電流を検出し、その値により
直接的に判定を行なつていた。しかし、電動機の
駆動回路における素子の短路等で二系統の駆動回
路のうちの一方に電流が一方向に流れたままの状
態となつた時には、いま一方の駆動回路には上記
回転方向を打ち消す方向に電流が流れるように制
御される。その際、各駆動制御系の機械的な結合
を与えるクラツチがすべりを起している場合には
各駆動制御系における電動機の電流を検出するだ
けではクラツチのすべりを検知できず、クラツチ
面の摩耗の二次障害を防ぐことができないという
欠点があつた。 Conventionally, two systems of drive control systems are used, each consisting of an electric motor, clutch, speed reducer, and pinion. By driving these systems in parallel, abnormal operation of the servo drive system that controls the rotation of movable members is detected. The method used to do this was to detect the current flowing through each motor in the drive control system, which consists of two systems, and directly make decisions based on the detected values. However, if the current remains flowing in one direction in one of the two drive circuits due to a short circuit in an element in the motor drive circuit, etc., the other drive circuit will flow in a direction that cancels out the rotation direction. The current is controlled so that it flows. At that time, if the clutch that mechanically connects each drive control system is slipping, it will not be possible to detect the clutch slip by simply detecting the electric current of the electric motor in each drive control system, and the clutch surface will wear out. The drawback was that it was not possible to prevent secondary failures.
本発明の目的は二系統の駆動制御系の出力電流
を検出して両者の差を求め、さらに減速機とピニ
オンとによるバツクラツシユを電気的に減少させ
るように、互いに逆方向の駆動トルクを加えるア
ンチバツクラツシユ方式を採用している場合に
は、これらのバイアス電流分を上記差電流から差
引き、この演算結果の絶対値を積分し、積分出力
が大きいときに異常と判定することができる並列
駆動制御系の異常動作検出方式を提供することに
ある。 The purpose of the present invention is to detect the output currents of the two drive control systems, find the difference between the two, and furthermore, to electrically reduce the backlash caused by the reducer and pinion, an anti-static system that applies drive torques in opposite directions to each other is provided. If the batch method is adopted, these bias currents are subtracted from the above difference current, the absolute value of this calculation result is integrated, and when the integrated output is large, it can be determined that there is an abnormality. An object of the present invention is to provide a method for detecting abnormal operation of a drive control system.
本発明による異常動作検出方式は二系統の第１
および第２の電動機と、第１および第２のクラツ
チと、第１および第２の減速機と、第１および第
２のピニオンとを具備し、可動部材を回転駆動制
御するための並列駆動制御系に含まれたものであ
る。 The abnormal operation detection method according to the present invention has two systems:
and a second electric motor, first and second clutches, first and second reduction gears, and first and second pinions, and parallel drive control for controlling the rotational drive of the movable member. It is included in the system.
異常動作検出方式は異常検出部により実現さ
れ、異常検出部は演算手段と、絶対値回路と、積
分回路と、比較回路と、アラーム設定器と、
ANDゲートとを具備したものである。異常検出
部においては二系統の第１および第２の電動機の
電流差から第１および第２の減速機のバツクラツ
シユを減少させるために可動部材へ互いに逆方向
に加えてあるトルクバイアス成分の影響を除去す
る目的で最初に演算手段を使つて上記電流差から
あらかじめ設定したバイアス電流の２倍を減じ
る、次に、この値の絶対値を絶対値回路により求
め、この絶対値を積分回路により積分する、積分
回路の出力の大きさがアラーム設定器に設定され
た閾値を越えたときには異常動作を比較器により
検出し検出された信号はANDゲートにより外部
駆動信号との間で論理積をとつて出力される。 The abnormal operation detection method is realized by an abnormality detection section, and the abnormality detection section includes a calculation means, an absolute value circuit, an integration circuit, a comparison circuit, an alarm setting device,
It is equipped with an AND gate. In the abnormality detection section, the influence of torque bias components applied in opposite directions to the movable member in order to reduce backlash of the first and second reduction gears is calculated from the current difference between the first and second electric motors of the two systems. For the purpose of removal, first subtract twice the preset bias current from the current difference using an arithmetic means, then calculate the absolute value of this value using an absolute value circuit, and integrate this absolute value using an integrating circuit. When the magnitude of the output of the integration circuit exceeds the threshold set in the alarm setting device, the comparator detects abnormal operation, and the detected signal is ANDed with the external drive signal by an AND gate and output. be done.
以下、本発明を実施例について図面を参照して
説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例を実現する構成を示
すブロツク図である。第１図において、１は速度
指令設定器、２は速度偏差増幅器、３は第１の電
流増幅器、４は第１のサイリスタ装置、５は第１
の電動機、６は第１の速度発電機、７は第１のク
ラツチ、８は第１の減速機、９は第１のピニオ
ン、１０は第１の過電流検出回路、１１は旋回
台、１２は反転増幅器、１３は第２の電流増幅
器、１４は第２のサイリスタ装置、１５は第２の
電動機、１６は第２の速度発電機、１７は第２の
クラツチ、１８は第２の減速機、１９は第２のピ
ニオン、２０は第２の過電流検出回路、２１は可
動部材、２２はトルクバイアス設定器、２３〜２
５は第１〜第３の係数器、２６は絶対値回路、２
７は積分回路、２８は比較回路、２９はANDゲ
ート、３０は異常検出部、３１はアラーム設定器
である。第１図は速度指令設定器１によつて設定
した目標速度で可動部材２１を駆動するための速
度制御系を示すものである。可動部材２１に取付
けられた歯車付きの旋回台１１には、第１および
第２の電動機５，１５と、第１および第２のクラ
ツチ７，１７と、第１および第２の減速機８，１
８と、第１および第２のピニオン９，１９とより
成る第１および第２の駆動制御系が結合されてい
る。第１および第２の電動機５，１５の回転は、
第１および第２のクラツチ７，１７、第１および
第２の減速機８，１８、第１および第２のピニオ
ン９，１９の順に旋回台１１に伝達される。最初
に、速度指令設定器１によつて設定された目標速
度と、それぞれ第１および第２の速度発電機６，
１６によつて検出された第１および第２の電動機
５，１５の速度のそれぞれの平均値とを比較す
る。そのうち、速度偏差増幅器２の出力にはトル
クバイアス設定器２２の改系統に出力が逆極性で
加算され、それぞれの系統の電流指令値となる。
第１および第２の電流増幅器３，１３によつて指
示された電流指令値は、各系統ごとに出力電流と
比較され、その差電流が零となるようにそれぞれ
第１および第２のサイリスタ装置４，１４を制御
して、それぞれ第１および第２の電動機５，１５
を駆動制御する。第１および第２の減速機８，１
８や、第１および第２のピニオン９，１９の歯車
系にバツクラツシユがあると、制御ループが不安
定となる。これを減少させるためには、二つの駆
動制御系に互いに逆方向の駆動トルクをわずかに
加えるアンチバツクラツシユ方式が一般に採用さ
れている。このバイアス量を設定するのがトルク
バイアス設定器２２である。従来の異常検出法に
おいては、各系統の出力電流を各々第１および第
２の過電流検出回路１０，２０によつて監視し、
過電流が流れたときに警報を発生するものが代表
的なものであつた。これを補う目的で付加した異
常検出部３０が本発明を特徴づけるものである。
以下に異常検出部３０の動作を詳述する。第１の
電動機５および第２の電動機１５の出力電流をそ
れぞれI1，I2とし、トルクバイアス設定器２２に
よつて設定されるバイアス電流値をＩBIASとする
と、本発明の異常検出部３０では（I1−I2−
2IBIAS）の演算が実行され、その絶対値を積分す
る積分回路２７の出力がアラーム設定器３１の出
力と比較される。積分回路２７の出力が設定レベ
ルＳnを越えると、比較回路２８の出力が高レベ
ル、すなわち論理値１となり、ANDゲート２９
により駆動信号との論理積がとられて警報信号を
発生する。この構成において正常な駆動が行われ
ているときの電流指令値、すなわち速度偏差増幅
器２の出力をＩaとすると、
I1≒Ｉa＋ＩBIAS
I2≒Ｉa−ＩBIAS
となる。したがつて、異常検出部３０の出力Ｓは
｜Ｓ｜≒（Ｉa＋ＩBIAS）−（Ｉa−ＩBIAS）
−2IBIAS｜＝０＜Ｓn
となる。よつて、比較回路２８の出力は低レベ
ル、すなわち論理値０となり、警報は出力されな
い。次に速度指令０の状態において、第２のサイ
リスタ装置１４や第２の電流増幅器１３が故障
し、第２の駆動系の出力電圧が最大電圧になりつ
ぱなしとなつたとき、I2＝Ｉn2と仮定すると、｜
Ｉn2＞｜ＩBIAS｜となり、速度偏差増幅器２の出
力を通してこの電流I2を打ち消す極性の電流
I1＝−Ｉn1＋ＩBIAS（ただしＩn1・Ｉn2＞０）
が流れる。このとき、
｜Ｓ｜＝｜（−Ｉn1＋ＩBIAS）−Ｉn2
−2IBIAS｜＝｜Ｉn1＋Ｉn2
＋ＩBIASＳn
となつて警報が出力される。 FIG. 1 is a block diagram showing a configuration for realizing an embodiment of the present invention. In FIG. 1, 1 is a speed command setter, 2 is a speed deviation amplifier, 3 is a first current amplifier, 4 is a first thyristor device, and 5 is a first
, 6 is a first speed generator, 7 is a first clutch, 8 is a first reduction gear, 9 is a first pinion, 10 is a first overcurrent detection circuit, 11 is a swivel base, 12 is an inverting amplifier, 13 is a second current amplifier, 14 is a second thyristor device, 15 is a second electric motor, 16 is a second speed generator, 17 is a second clutch, and 18 is a second speed reducer. , 19 is a second pinion, 20 is a second overcurrent detection circuit, 21 is a movable member, 22 is a torque bias setting device, 23 to 2
5 is the first to third coefficient multiplier, 26 is an absolute value circuit, 2
7 is an integration circuit, 28 is a comparison circuit, 29 is an AND gate, 30 is an abnormality detection section, and 31 is an alarm setting device. FIG. 1 shows a speed control system for driving the movable member 21 at a target speed set by the speed command setting device 1. As shown in FIG. The rotating base 11 with gears attached to the movable member 21 includes first and second electric motors 5, 15, first and second clutches 7, 17, first and second reducers 8, 1
8 and first and second pinions 9 and 19 are connected to each other. The rotation of the first and second electric motors 5, 15 is
The signal is transmitted to the swivel base 11 in the order of the first and second clutches 7, 17, the first and second reduction gears 8, 18, and the first and second pinions 9, 19. First, the target speed set by the speed command setting device 1 and the first and second speed generators 6,
16 are compared with the respective average values of the speeds of the first and second electric motors 5 and 15 detected by the motor 16. Among them, the output of the speed deviation amplifier 2 is added to the modified system of the torque bias setter 22 with the opposite polarity, and becomes a current command value for each system.
The current command values instructed by the first and second current amplifiers 3 and 13 are compared with the output current for each system, and the first and second thyristor devices are adjusted so that the difference current becomes zero. 4 and 14 to respectively control the first and second electric motors 5 and 15.
to drive and control. First and second reducer 8,1
If there is a backlash in the gear system of the pinion 8 or the first and second pinions 9 and 19, the control loop becomes unstable. In order to reduce this, an anti-backlash method is generally adopted in which drive torques are slightly applied in opposite directions to the two drive control systems. The torque bias setting device 22 sets this bias amount. In the conventional abnormality detection method, the output current of each system is monitored by the first and second overcurrent detection circuits 10 and 20, respectively.
A typical example is one that generates an alarm when an overcurrent flows. The present invention is characterized by the abnormality detection section 30 added for the purpose of compensating for this.
The operation of the abnormality detection section 30 will be described in detail below. If the output currents of the first electric motor 5 and the second electric motor 15 are respectively I 1 and I 2 and the bias current value set by the torque bias setting device 22 is I BIAS , then the abnormality detection unit 30 of the present invention Then (I 1 −I 2 −
2I BIAS ) is executed, and the output of the integrating circuit 27 that integrates the absolute value is compared with the output of the alarm setting device 31. When the output of the integrating circuit 27 exceeds the set level S n , the output of the comparing circuit 28 becomes a high level, that is, a logical value of 1, and the AND gate 29
is logically ANDed with the drive signal to generate an alarm signal. If the current command value when normal driving is performed in this configuration, that is, the output of the speed deviation amplifier 2, is Ia , then I1≈Ia + IBIAS I2≈Ia −IBIAS . Therefore, the output S of the abnormality detection unit 30 is |S|≒(I a +I BIAS )−(I a −I BIAS )−2I BIAS |=0<S n . Therefore, the output of the comparison circuit 28 is at a low level, that is, the logical value is 0, and no alarm is output. Next, in a state where the speed command is 0, when the second thyristor device 14 or the second current amplifier 13 fails and the output voltage of the second drive system remains at the maximum voltage, I 2 = I Assuming n2 , |
I n2 >|I BIAS |, and a polar current I 1 =-I n1 +I BIAS (where I n1 ·I n2 >0) flows through the output of the speed deviation amplifier 2 to cancel this current I 2 . At this time, |S|=|(−I n1 +I BIAS )−I n2 −2I BIAS |=|I n1 +I n2 +I BIAS S n and an alarm is output.
同様に第１の駆動系の出力電圧が最大電圧にな
りつぱなしとなつたときは、I1＝Ｉn1とすると｜
Ｉn1｜＞｜ＩBIAS｜となり、I1を打ち消す極性の
電流
I2＝−Ｉn2−ＩBIAS（ただしＩn1・Ｉn2＞０）
が流れ、このとき、
｜Ｓ｜＝｜Ｉn1−（−Ｉn2−ＩBIAS）
−2IBIAS｜｜Ｉn1＋Ｉn2
−ＩBIAS｜Ｓn
となり警報が出力される。 Similarly, when the output voltage of the first drive system remains at the maximum voltage, let I 1 = I n1 |
I n1 |> | I BIAS |, and a polar current I 2 = −I n2 − I BIAS (where I n1・I n2 >0) that cancels I 1 flows, and at this time, |S|=|I n1 − (−I n2 −I BIAS ) −2I BIAS ||I n1 +I n2 −I BIAS |S n and an alarm is output.
以上説明したように、本発明による異常動作検
出方式を付加することにより、従来の各駆動制御
系ごとの過電流検出回路だけでは検出が困難であ
つたような駆動制御系を構成する素子の短絡障害
等にともなうものであつて、かつ二系統の駆動系
が互いに逆方向に回転されようとした際に起こる
ことがあるクラツチ、減速機等の機械的な駆動部
の障害を未然に防止することが可能となるという
効果がある。 As explained above, by adding the abnormal operation detection method according to the present invention, it is possible to detect short-circuits in elements constituting the drive control system, which was difficult to detect using only the conventional overcurrent detection circuit for each drive control system. To prevent failures of mechanical drive parts such as clutches and reducers that may occur when two drive systems are rotated in opposite directions due to failures, etc. This has the effect of making it possible.
第１図は本発明による並列駆動制御系の異常動
作検出方式を含む構成の一実施例を示すブロツク
図である。
１……速度指令設定器、２……速度偏差増幅
器、３，１３……電流増幅器、４，１４……サイ
リスタ装置、５，１５……電動機、６，１６……
速度発電機、７，１７……クラツチ、８，１８…
…減速機、９，１９……ピニオン、１０，２０…
…過電流検出回路、１１……旋回台、１２……反
転増幅器、２１……可動部材、２２……トルクバ
イアス設定器、２３，２４，２５……係数器、２
６……絶対値回路、２７……積分回路、２８……
比較回路、２９……AND回路、３０……異常検
出部、３１……アラーム設定器。
FIG. 1 is a block diagram showing an embodiment of a configuration including an abnormal operation detection method for a parallel drive control system according to the present invention. 1... Speed command setter, 2... Speed deviation amplifier, 3, 13... Current amplifier, 4, 14... Thyristor device, 5, 15... Electric motor, 6, 16...
Speed generator, 7, 17...Clutch, 8, 18...
...Reducer, 9,19...Pinion, 10,20...
... Overcurrent detection circuit, 11 ... Swivel base, 12 ... Inverting amplifier, 21 ... Movable member, 22 ... Torque bias setting device, 23, 24, 25 ... Coefficient unit, 2
6...Absolute value circuit, 27...Integrator circuit, 28...
Comparison circuit, 29...AND circuit, 30...Abnormality detection section, 31...Alarm setting device.
Claims (1)
よび第２のクラツチと、第１および第２の減速機
と、第１および第２のピニオンとを具備し、可動
部材を回転駆動制御するための並列駆動制御系に
含まれた異常動作検出方式であつて、演算手段
と、絶対値回路と、積分回路と、比較回路と、ア
ラーム設定器と、ANDゲートとを具備した異常
検出部によつて、前記二系統の第１および第２の
電動機の電流差から前記第１および第２の減速機
のバツクラツシユを減少させるための逆方向のト
ルクを前記可動部材に加えてある系では、それら
のバイアス電流分の影響を除外するため、前記演
算手段により前記電流差からあらかじめ設定した
バイアス電流の２倍を減じ、この値の絶対値を前
記絶対値回路により求め、前記絶対値を積分する
ための前記積分回路の出力の大きさが前記アラー
ム設定器に設定された閾値を越えたときに異常動
作を前記比較器により検出し、さらに前記AND
ゲートにより外部駆動信号と前記比較器の出力と
をANDゲート出力することを特徴とした並列駆
動制御系の異常動作検出方式。1 Comprising two systems of first and second electric motors, first and second clutches, first and second reduction gears, and first and second pinions, the movable member is rotationally driven and controlled. An abnormal operation detection method included in a parallel drive control system for the purpose of According to the system, torques in opposite directions are applied to the movable member from the current difference between the first and second electric motors of the two systems to reduce the backlash of the first and second reduction gears, In order to exclude the influence of those bias currents, the calculation means subtracts twice the preset bias current from the current difference, the absolute value of this value is determined by the absolute value circuit, and the absolute value is integrated. Abnormal operation is detected by the comparator when the magnitude of the output of the integrating circuit exceeds a threshold set in the alarm setting device, and
An abnormal operation detection method for a parallel drive control system, characterized in that an external drive signal and the output of the comparator are outputted from a gate using an AND gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57151402A JPS5941192A (en) | 1982-08-31 | 1982-08-31 | Malfunction operation detecting system for parallel drive control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57151402A JPS5941192A (en) | 1982-08-31 | 1982-08-31 | Malfunction operation detecting system for parallel drive control system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5941192A JPS5941192A (en) | 1984-03-07 |
| JPS6259556B2 true JPS6259556B2 (en) | 1987-12-11 |
Family
ID=15517802
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57151402A Granted JPS5941192A (en) | 1982-08-31 | 1982-08-31 | Malfunction operation detecting system for parallel drive control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5941192A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63194056U (en) * | 1987-05-31 | 1988-12-14 | ||
| JPH01149854U (en) * | 1988-04-09 | 1989-10-17 |
-
1982
- 1982-08-31 JP JP57151402A patent/JPS5941192A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63194056U (en) * | 1987-05-31 | 1988-12-14 | ||
| JPH01149854U (en) * | 1988-04-09 | 1989-10-17 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5941192A (en) | 1984-03-07 |
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