JPS6259399B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a novel shift register configuration,
In particular, the present invention provides a shift register that is small in size, has low power consumption, and is suitable for on-chip use in two-dimensional imaging devices and the like.

Recently, MOS arrays, charge injection devices (Charge
Injection Device: (hereinafter abbreviated as CID) etc. 2
Dimensional sensors are being actively put into practical use, but in order to satisfy practical TV scanning specifications, the MOS arrays, CIDs, etc. mentioned above require a large number of pixels, and as a result, the number of pixels of the above semiconductor devices is increasing. It has become necessary to use a multi-stage shift register to drive the shift register.

However, on the other hand, the chip size constituting the above-mentioned semiconductor device must be reduced, and for this purpose, the pixel pitch must be reduced, and accordingly, the shift register used must also be reduced in size. A normal shift register has 6 MOS
Since one stage is composed of transistors (hereinafter abbreviated as MOST), it is difficult to achieve miniaturization and low power consumption.

To solve this problem, IEEE developed a shift register that consisted of one stage using four MOSTs.
Solid State Circuits, vol.sc-13, No.1p.5-10, this method uses feedback between stages, which increases the degree of coupling between stages, especially during high-speed operation. This has the disadvantage that it may cause malfunction.

The present invention has been developed in view of these drawbacks, and uses only 2 to 3 MOSTs per stage without using feedback between stages, which allows for small and stable operation.
Furthermore, the present invention aims to provide a shift register with low power consumption, and will be explained in detail below with reference to the drawings.

FIG. 1 is a circuit diagram representing the basic idea of a novel shift register according to the present invention.

First, in Figure 1, the 1st stage, 2nd stage, 3rd stage...
Each unit stage, shown as
One end of S ₂ is applied with, for example, one of three-phase pulsed transfer voltages Φ ₁ , Φ ₂ , Φ ₃ , that is, Φ ₂ , and another pulse voltage, such as Φ ₃ , is applied. Thus, the reset element _S1 is controlled. The other end of the switch element _S2 is connected via a one-way conduction element _D1 to a charge holding capacitor _C2 that holds transmission information in the second stage.

Now, from the terminal 11, in the timing chart of FIG. 2 drawn with time t as the horizontal axis, t=
Assume that an input signal voltage pulse V _IN , which is information to be transmitted by the shift register, enters at a high level at time _t11 . Pulse transfer voltage Φ
₁ is at a high level between times _t12 and _t13 , so switch _S0 is closed during this period. As a result, the charge holding capacitor C ₁ is charged by the input signal voltage pulse V _IN at time t ₁₂ , so the node
As shown in FIG. 2, the potential V _N1 of N ₁ becomes high level from time t ₁₂ and maintains that value. This potential V _N1 closes the switch element S ₂ , but t ₁₅ ~
During the period _t16 , a pulse voltage _Φ2 having a value of, for example, 5V is applied to one end of the switch element _S2 , so the potential V _O1 at the node O1 rises to 5V during the period _t15 to _t16 . This potential V _O1 generates a current flowing in the forward direction through the one-way conduction element D ₁ and charges the capacitor C ₂ , so that the node N ₂ connected to the capacitor C ₂
The potential V _N2 becomes a high level of 5 V from time t ₁₅ , but the pulse voltage Φ ₂ becomes low level at time t ₁₆ , so even if the switch S ₂ is opened at the same time, the voltage at the above node The potential V _N2 of N ₂ maintains a value of 5V. The switch _S4 is closed due to the potential _VN2 at the node _N2 .

Then, at the time t ₁₇ to _{t 18} , the pulse voltage Φ ₃
When the level reaches a high level of 5V, the reset element _S1 closes, and the charge in the capacitor _C1 in the first stage is discharged, so that the voltage _VN1 at the node _N1 becomes
Returns to low level at time t ₁₇ . However, on the other hand, since the pulse voltage Φ ₃ is also applied to one end of the switch element S ₄ , the potential V _O2 at the node O2 connected to the switch element S ₄ reaches a high value of 5 V between t ₁₇ and t ₁₈ . level, but the potential V _O2 causes a current to flow in the forward direction through the unidirectional conduction element D ₂ in the second stage, charging the capacitor C ₃ , and for this purpose, the node N connected to the capacitor C ₃ The potential V _N3 of ₃ is from the time t ₁₇
It becomes a high level of 5V, and the pulse voltage Φ ₃ becomes
It maintains its value even if it drops to a low level at time t ₁₈ .

Since the switch _S6 is in a closed state due to this maintained voltage _VN3 , if the pulse voltage _Φ1 again reaches a high level of 5V during the time from _t19 to _t20 . , the potential V _O3 at the node O3 connected to the other end of the switch _S6 also rises to a high level of 5V at the same time, as seen in FIG.
The potential V _O3 causes a current to flow in the forward direction through the one-way conduction element D ₃ to charge the capacitor C ₄ in the third stage.

In this way, the potential V _N4 (not shown) at the node N ₄ connected to the capacitor C ₄ becomes a high level of 5V and maintains that value even if the pulse voltage Φ ₁ becomes a low level at t ₂₀ .

By the way, the above pulse voltage _Φ1 is the reset element _S3
Therefore, at time _t19 when the voltage _Φ1 is applied, the potential _VN2 of the node _N2 becomes the second
It drops to a low level as seen in the figure.

Then, when the pulse voltage _Φ2 reaches a high level of 5V at time _t21 , the reset element _S5 is controlled by the voltage _Φ2 , so the switch element _S5 becomes closed. As a result, the charge in the charge storage capacitor _C3 that holds information is discharged,
Therefore, the potential V _N3 at node N ₃ drops to a low level at time t ₂₁ as seen in FIG.

Similar phenomena occur in the fourth and fifth stages (not shown)...
This also occurs for nodes O1, O
If we pay attention to 2, O3......, we can see that the parallel output potentials V _O1 , V _O2 , V _O3 ,... at these nodes are sequentially increased to a high level and then dropped to a low level, which is a sequential switching process. Become. Therefore, if terminals are drawn out from the nodes O1, O2, O3, . . . , operation as a shift register can be obtained here.

Figure 3 shows each reset element S ₁ , S ₃ , S ₅ , S ₇ and each switch element based on the configuration of Figure 1 above.
S ₀ , S ₂ , S ₄ , S ₆ , S ₈ and unidirectional conduction elements D ₁ ~
This is a circuit configuration diagram of a shift register according to the present invention in which D ₃ is configured with an enhancement-type MOST, and where the first stage, second stage, third stage, etc. are located is shown in the figure. They are shown separated by dotted lines.

MOST・T ₀ and T ₁ play the roles of switches S ₀ and S ₁ in FIG. 1, respectively,
T ₂ , T ₅ , T ₈ , and T ₁₁ serve as switch elements S ₂ , S ₄ , S ₆ , and S ₈ in FIG. 1, respectively. The gates of T ₃ , T ₆ , T ₉ , and T ₁₂ are electrically connected to the diffusion layer of either the source or the drain, and therefore the MOST/T ₃ , T ₆ , T ₉ , and T ₁₂ exhibit unidirectional conductivity like the unidirectional conductive elements D ₁ , D ₂ , and D ₃ shown in FIG. Further, T ₁ , T ₄ , T ₇ , and T ₁₀ are respectively reset elements S ₁ , S ₃ , S ₅ , and S ₇ in FIG.
It corresponds to

Although the charge holding capacitors C ₁ , C ₂ , C ₃ , and C ₄ shown in FIG. 1 are not shown in FIG. 3,
The capacity is determined by the nodes N ₁ , N ₂ , N ₃ , N ₄ . . . in Fig. 3.
The capacitive component that occurs between the gate or source/drain junction of the MOST connected to each of the substrate semiconductors and the capacitive component in each stage (i.e.,
C ₁₁ for the second step, C ₁₂ for the second step, C 12 for the third step
It is formed by the sum of C ₁₃ and C ₁₄ in the fourth stage. And the nodes N ₁ , N ₂ , N ₃ , N ₄ ,... in each stage
..., O1, O2, O3, O4... are shown in Figures 1 and 3.
Both figures correspond. Needless to say, the shift registers shown in FIG. 3 are constructed on the same semiconductor substrate, and the terminal 15 is a ground terminal (GND).

Here, MOST・T ₂ , T ₅ , T ₈ , T ₁₁ ... in Figure 3
Between each of the source points 22, 24, 26, ₂₈ , .
C ₁₂ , C ₁₃ , C ₁₄ ... are connected, and other roles of these capacitors will be described below.

Now, the input terminal 11 shown in Fig. 3 is connected to the input terminal 11 shown in Fig. 4.
Even if the input signal voltage pulse V _1N enters at a high level from time t ₃₁ to _{t 34} , the switch
Unless T ₀ is closed, the pulse V _1N is at node N ₁
I can't tell you. However, in the period t ₃₂ to _{t 33} , the transfer pulse voltage Φ ₁ becomes high level, and therefore the switch MOST・T ₀ is closed, so that the node N ₁
In other words, the input signal voltage pulse V _1N , that is, the information to be transmitted, is transmitted to the gate of MOST T ₂ for the switch, and the information is transmitted as described above.
The gate capacitance of MOST・T ₂ and the junction capacitance between the diffusion layer and the substrate at point 21 of MOST・T ₀ and
Charge the charge holding capacitor formed by _C11 . Therefore, the potential V ₁ at the node N ₁ rises to a high level, but its value does not reach the value of the input signal voltage pulse V _1N , as shown in the period from t ₃₂ to _{t 35} in FIG. As such, the potential V _N1 remains at, for example, 80% of V _1N . This phenomenon is not limited to MOST・T ₁ , but also MOST・T ₂ , T ₄ , T ₆ , T ₈ ,
………or MOST・T ₃ , T ₆ , T ₉ , T ₁₂ ………
The reason for this is that these MOST boards are fixed at ground potential, while each
This is due to the increase in the source potential of MOST.

It is well known that the saturation current I _DS of the MOST is generally expressed as I _DS =K(V _G −V _T ) ² (1a) with respect to the gate voltage and its threshold voltage V _T . Since the gate voltage V _G is V _GS −V _SS here, it can also be expressed as I _DS =K(V _GS −V _SS −V _T ) ² (1b). However, K is a constant.

By the way, the MOST substrate has a current control function like an insulated gate. Here, if the source potential V _SS rises while the substrate is grounded as above, the corresponding
Negative bias voltage α on the MOST substrate
The result is the same as when √ _SS is added, and equation (1b) can be expressed in the form I _DS = K [V _GS − (V _SS + V _T + α√ _SS )] ² ...(2) So, the source potential V _SS
When the voltage rises, I _DS becomes saturated at a certain value of V _SS , so that the source potential V _SS remains at a value below the gate potential V _G . This phenomenon is well known as the backgate effect. However, α is a constant determined by the impurity concentration of the substrate and other factors.

The capacitors C ₁₁ to _{C 14} in FIG _. 3 described above are inserted to prevent the information voltage to be transmitted one after another from gradually decreasing due to the back gate _effect. If it does not exist, the following will happen:

Now, as mentioned above, if the value of the potential applied as V _1N at time T ₃₁ is 5V, then T ₃₂
The node N ₁ which has a high level at ~T ₃₃ , i.e.
Due to the above-mentioned reason, that is, the back gate effect, the value of the source voltage V _SS of MOST・T ₀ does not reach the value of the gate voltage V _G of MOST・T ₀ , that is, the transfer voltage Φ ₁ = 5V, and for example, 80% of Φ ₁ , or 4V. Stay in.

MOST・T ₂ for the switch is the node of this value of 4V
The voltage V _N2 at N ₂ causes it to close after T ₃₂ . At this time, MOST・T ₂ is in the closed state, so
A voltage of the same value as the drain voltage of Φ ₂ = 5V applied between t ₃₅ and t ₃₆ also appears at the source terminal (node 22) of MOST・T ₂ , so that the voltage V O1 at node _O1 becomes 5V. It seems to me. However, the source voltage V _S at point 22 of MOST・T ₂
In reality, _S does not rise to the gate voltage of MOST・_T2 , that is, V _N1, due to the backgate effect described above, and for example, when the gate voltage V _N1 = 4V,
It stays at 80% value or 3.2V. Therefore, the voltage V _O1 at the node O1 is 3.2V.

The voltage V _O1 at the node O1, which has increased to 3.2V, is transferred to the _second
The charge holding capacitor of the second stage (not shown) determined by the capacitance C ₂ of the stage, the gate capacitance of MOST・T ₅ , and the drain junction capacitance of MOST・T ₃ is charged, and the charge holding capacitor of the fourth stage is charged.
As shown in the figure, at t= _t35 , the voltage V _N2 at the node _N2 is set to a high level. However, the source potential V _SS at point 23 of MOST・T ₃ , which has this unidirectional conductivity, is also caused by the backgate effect, causing the above V SS
_O1 does not exceed 80% of 3.2V, so the voltage V _N2 becomes 2.56V.

At t=t ₃₆ , the transfer voltage Φ ₂ is at a low level as shown in Figure 4, but the capacitance C ₁₂ and MOST
The charge holding capacitance (not shown) determined by the gate capacitance of T ₅ and the source junction capacitance of MOST T ₃ maintains the above voltage V _N2 for a while, so MOST
The above voltage V _N2 of 2.56V is applied to the gate of _T5 . On the other hand, at t= _t37 , the transfer voltage _Φ3 turns to a high level. Since MOST T ₅ is closed by the gate voltage V _N2 , the potential V _SS of its source terminal 24 increases, but the source potential is also 80% of the gate voltage, that is, V _N2 due to the back gate effect. In other words, it only rises to 2.48V. Therefore, the node O that increases from zero level
The maximum value of voltage 2 is 2.48V.

Therefore, due to the same backgate effect as above, the voltage V _N3 increases at t= _t37 at node _N3 .
is 80% of the above 2.48V, or 1.6384V, and furthermore, the potential V _O3 , which becomes high level during the period from t ₃₉ to _{t 40} at node O3, is 80% of the above 1.6384V, or
It becomes 1.311V. Then, the value of the voltage V _N4 at the node N ₄ that rises to a high level from time t ₃₉ is the above V _O3 =
This is 80% of 1.311V, or 1.0488V, and therefore the value of voltage V _O4 which becomes high level as voltage Φ ₂ rises at source terminal 28 of MOST T ₁₁ , that is, node O4, is equal to the above V _N4 = 1.0488V. 80% value,
In other words, it becomes 0.83904V.

Since the backgate effect exists in this way, the voltage V _O1 to V O from node O1 to _node O4
₄ , or the voltage at each stage after node O4 is
An inconvenient phenomenon occurs in which the amount gradually decreases.

However, if the capacitors C ₁₁ to C ₁₄ are connected between the gate and source of each switch MOST, the above-mentioned inconvenience can be prevented. Let me briefly explain this only for the first few stages.

That is, the high level potential at the source terminal of MOST T ₂ is 4V as described above. However, there is a capacitance between the source and gate of MOST・T ₂ .
C ₁₁ is inserted. And a node of 4V applied to the gate of MOST・T ₂ via MOST・T ₀
The capacitor C ₁₁ is charged by the voltage V _N1 of N ₁ . Therefore, at time t ₃₅ , Φ ₂ becomes high level, and the source voltage V _SS of MOST・T ₂ increases from zero to 4 V, as shown in FIG. 4, at t = t. This is superimposed on the voltage of 4V across the charge storage capacitor that has been maintained since time _t32 , and the total value from _t35 to _t36 reaches 8V.

If we return to equation (2) above, the voltage in parentheses in the equation has negative polarity. The third term among the three terms having negative polarity, ie, _α√SS , increases due to the rise in _VSS , causing the current control phenomenon as described above, resulting in the backgate effect. Therefore, the additional gate voltage △V _{G of positive polarity, which is a value sufficiently exceeding the absolute value of the third term having negative polarity, is expressed as V G in} the second equation.
In addition, if I _DS =K [V _G +△V _G -(V _SS +V _T +α√ _SS )]...(3), then the first with positive polarity in the above equation (3) and the sum of the second term is the third term with negative polarity.
(the three terms in parentheses), therefore saturation does not occur in the current value I _DS , and for this reason the source potential V _SS can become equal to the drain applied voltage V _G . Therefore, the value of voltage V _O1 at node O1 is the transfer voltage Φ
The voltage will be 5V, which is the same as ₂ . Here, the additional gate voltage △V _G
It goes without saying that the capacity equivalent to
This is the voltage developed across C ₁₁ .

By the way, at t= _t36 , the transfer voltage _Φ2 drops to a low level, so the voltage across the first stage charge storage capacitor, that is, _VN1 , drops to a value of 4V again at time _t36 .

Here, the voltage V _O1 at the node O1, which has reached a high level of 5 V at T ₃₅ to T ₃₆ , causes a current to flow in the forward direction through the MOST T ₃ having one-way conductivity, and causes the capacitance C ₁₁ and the aforementioned The second stage charge holding capacitor formed by the surrounding capacitors is charged, but the voltage V _N2 at the source terminal of MOST T ₃ , that is, the point 23, is due to the back gate effect.
The voltage remains at 4V at node _N2 .

Therefore, the voltage V _N2 at node N ₂ , in other words
Gate capacitance of MOST・T ₅ and point 23 of MOST・T ₃
The voltage across the second stage charge storage capacitor, which is determined by the sum of the junction capacitance at and the capacitance C ₁₂ , maintains a value of 4V after time t ₃₅ as shown in FIG. 4. However, as mentioned above, the transfer voltage Φ ₃ becomes high level from t ₃₇ to _{t 38} , so the source voltage V _SS of MOST T ₅ with the voltage Φ ₃ as the drain voltage becomes 4V due to the back gate effect. Become. This source voltage V _SS =4V is from t ₃₇ to _{t 38}
During this period, the voltage is superimposed on the voltage of 4V across the charge storage capacitor of the second stage, so the total becomes 8V as seen in the voltage waveform _VN2 in FIG.

As mentioned above, the second stage charge storage capacitor is used for switching as well as the first stage charge storage capacitor.
Since it includes a capacitor (C 12 in the second stage) connected between the gate and source of the MOST (T ₅ in the second stage), a voltage of 4V is maintained across the capacitor _{C 12 .} Therefore, the voltage across this capacitor _C12 (equal to the voltage across the charge retention capacitor of the second stage) becomes the additional gate voltage △V _G mentioned above,
Therefore, the voltage at the source point 24 of MOST T ₅ has a value of 5V, which is the same as the transfer voltage Φ ₃ . This result is nothing but setting the voltage V _O2 at the node O2 to 5V, which is the same value as the voltage V _O1 at the node O1.

In addition, the source voltage of MOST T ₅ , which is 4V, is V _S
The transfer voltage Φ ₃ , which reaches a high level between T ₃₇ and _{T 38} that caused _S , opens MOST・T ₁ , so that
As described above, since the voltage across the first stage charge storage capacitor, in other words, the voltage across the capacitor _C11 , is reset, V _N1 returns to the low level at t= _t37 , as seen in FIG.

By the way, the voltage at node O2, which has reached the value of 5V as mentioned above, causes a current to flow in the forward direction through MOST _T6 , which has unidirectional conductivity due to the connection between the gate and source, and around node _N3 . However, since there is a backgate effect in MOST T ₆ , the above charging voltage is not 5V, but 4V at 80% of the value. The third stage node remains lowered to
It costs _N3 .

Therefore, the voltage V _N3 at node N ₃ , in other words
Gate capacitance of MOST・T ₃ and point 25 of MOST・T ₆
The voltage across the charge holding capacitor of the third stage, which is determined by the sum of the junction capacitance at and the capacitance _C13 , maintains a value of 4V after time _t37 , as shown in FIG. However, from t ₃₉ to _{t 40} , the transfer voltage Φ ₁ becomes high level, so the source voltage V _SS of MOST・T ₅ with the voltage Φ ₃ as the drain voltage
becomes a value of 4V due to the backgate effect.
This source voltage V _SS =4V is superimposed on the voltage of 4V across the second stage charge storage capacitor during the period from _t39 to _t40 , so the total is _VN3 in FIG.
As seen in the voltage waveform, the voltage is 8V.

As mentioned above, the charge holding capacitor in the third stage is used for switching as well as the charge holding capacitor in the second stage.
Since it includes a capacitor (C 13 in the third stage) connected between the gate and source of the MOST (T ₃ in the third stage), a voltage of 4V is maintained across _{the capacitor C 13 .} Therefore, the voltage across this capacitor _C13 (equal to the voltage across the charge retention capacitor of the third stage) becomes the additional gate voltage △V _G mentioned above,
Therefore, the voltage at the source point 26 of MOST・T ₃ is
It has a value of 5V, which is the same as the transfer voltage _Φ1 , which has a value of 5V. This result is nothing but setting the voltage V _O3 at the node O3 to 5V, which is the same value as the voltage at the node O2.

Also, the source voltage of MOST T ₈ , which is 4V, is V _S
The transfer voltage Φ ₁ which reaches a high level between t ₃₉ and t ₄₀ when _S occurs is the voltage across the charge storage capacitor of the second stage as described above, in other words, in order to open MOST・T ₁ . By resetting the voltage across capacitor C ₁₂ , V _N2 returns to a low level at t=t ₃₉ , as seen in FIG. In addition, 1 in Figure 3
2, 13, and 14 are terminals for supplying transfer voltages Φ ₁ , Φ ₂ , and Φ ₃ .

Hereinafter, the same process described for the first stage and the third stage can similarly occur in the third stage, the fourth stage, or each stage after the fifth stage (not shown in FIG. 3). Therefore, due to the transfer voltage Φ ₂ which becomes high level between t ₄₁ and _{t 42} , the low source voltage V _SS of MOST・T ₁₁ which remains at the value of 4V in the fourth stage is due to the additional voltage generated across the capacitance C ₁₄ . Gate voltage △V _G
is corrected in the period t ₄₁ to t ₄₂ by
The gate voltage of _T11 is increased to 8V to bring the source voltage V _SS and hence the voltage at node O4 to 5V. At the same time, the transfer voltage Φ ₂ opens the reset MOST T ₇ , so that the node N ₃
The voltage V _N3 becomes low level at time t=t ₄₁ .

Similarly, due to the transfer voltage Φ ₃ applied between t ₄₃ and t ₄₄ , it remains at the lower value of the fifth stage (not shown).
The value of the MOST source voltage V _SS depends on the voltage across the capacitance connecting the gate and source of the MOST.
During the period from _t43 to _t44 , the gate voltage of the MOST is increased, so that the voltage at the node connected to the source terminal of the MOST is set to 5V, and at the same time, the third stage reset MOST _T10 is opened and the voltage _VN4 at node _N4 is returned to a low level at time t= _t43 .

In this way, each node O1, O2, O3, O
The voltages of 4, . . . can all be set to a value of 5V.

If the connections shown by the dotted lines A, B, C, D, . . . in FIG. The reason is that the MOST for reset T ₁ , T ₄ ,
T ₇ , T ₁₀ , ...... act on each node N ₁ , N ₂ , N ₃ ,
As can be seen from the timing chart in Figure 4, at the timing when the potential of N ₄ , ...... should be lowered to a low level (ground potential), Φ ₁ , Φ ₂ , Φ
₃ , Φ ₁ , ...... are derived from the fact that they have each fallen to a low level.

By the way, elements with unidirectional conductivity and
Other elements may be used as long as they have equivalent functions for each of the capacitors connecting the gate and source of the MOST.

According to the shift register according to the present invention described above, the number of MOSTs constituting one stage is only three, and since feedback between each stage is not used, stable switching operation is possible. This can be expected to have great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the basic idea of the shift register according to the present invention, FIG. 2 is a timing chart showing the operation of the shift register shown in the circuit diagram, and FIG. 3 is a circuit diagram of the shift register according to the present invention. FIG. 4 is a timing chart showing the operation of the shift register shown in the circuit diagram. O1, O2, O3, O4, ..., N ₁ , N ₂ ,
N ₃ , N ₄ ...: Node, 11: Input terminal, 12, 1
3, 14: Input terminal of transfer voltage _Φ1 , _Φ2 , _Φ3 , 15: Ground terminal, _T1 ~ _T11 : MOST, _C11 ~
_C14 : Capacity.

Claims (1)

[Scope of Claims] 1. A memory circuit consisting of a capacitor that holds information, a reset element that erases the information by shorting both ends of the capacitor, a switch element that is controlled by a voltage across the memory circuit, and a switch element that is controlled by a voltage across the memory circuit. An information transmission circuit consisting of a one-way conduction element connected to one end of a switch element and transmitting information to the next stage storage circuit is used as a unit circuit, and this unit circuit is connected in multiple stages, and each of the above-mentioned switch elements of each unit circuit is By sequentially applying a three-phase pulsed transfer voltage to each other end to which the unidirectional conduction element is not connected, the information applied to the input terminal of the information circuit is sequentially transmitted. A shift register characterized by: 2. The shift register according to claim 1, wherein MOS transistors are used as the switch element, the reset element, and the one-way conduction element. 3 Claims characterized in that by connecting a capacitor between the gate and source of the MOS transistor serving as the switch element, the substantially parallel output voltage of the subsequent stage is prevented from decreasing. Shift register according to item 2.