JPS6258498A - Inspecting device for ic - Google Patents

Abstract

PURPOSE:To improve the using efficiency of a fail memory and the cost performance of a device by ORing respective decided results of data of plural bits, which is simultaneously read out, and making said logic sum into information to be stored in the fail memory. CONSTITUTION:Deciding signals J1-J4 of four bits outputted from an deciding part are inputted to a multiinput OR gate Go, and ORed. The output signal from the OR gate Go is supplied to the fail memory 6, and if any of all the deciding signals J1-J4 is at a high level, data '1' is written in the address of the fail memory 6 corresponding to the address of the head. As a result, even if there is only one defective bit among 4-bit data RD1-RD4 simultaneously read from an IC memory 10, a bit '1' is stored, which indicates that the defective bit is included at the corresponding position in the fail memory 6. In this way, the fail information on 4-bit data read from the IC memory 10 is compressed at the OR gate Go and stored in the fail memory 6.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a technique particularly effective when applied to a semiconductor integrated circuit testing technique and a storage method for test results, such as a semiconductor memory device (hereinafter referred to as an IC memory). The present invention relates to a technique effective for use in a storage method for test results in a test device.

[Background Art] Conventionally, an apparatus as shown in FIG. 2 has been provided as an IC memory inspection apparatus.

That is, in this testing device, the function test controller 3 performs the tests necessary for testing the IC memory based on the test pattern TP supplied from the pattern generator 1 and the timing clock OK supplied from the timing generator 2. Test data DAT such as write data
A and a timing signal TMG such as an address signal, a chip select signal, and a write enable signal.

These data DATA and timing signal TMG are applied to the IC memory 10 via the application section 4, and are applied to the IC memory 10 via the application section 4.
The data read from the memory 10 is compared in the determination section 5 with the expected value E also supplied from the controller 3 in synchronization with the determination strobe signal DS supplied from the controller 3. As a result, defective bits within the IC memory are detected.

The position of the detected defective bit is determined by the I
In the fail memory 6 which has the same capacity as the C memory 10,
It is stored bitwise. In other words, by writing "1" to the same address in the fail memory 6 as the address of the defective bit in the IC memory 10, the status of the bit as good or defective is stored. Note that the position of the defective bit stored in the fail memory 6 (hereinafter referred to as fail information) is used when replacing a memory column or memory row containing a defective bit with a spare column or row in a memory having a redundant configuration. Ru.

In the memory test device as described above, when the capacity of the IC memory 10 to be tested increases, the fail memory 6 must also use a memory with the same capacity or a larger capacity. First, there is a problem that the memory usage efficiency is poor.

[Object of the Invention] An object of the present invention is to provide a fail information storage method that can improve the cost performance of the device by increasing the usage efficiency of the fail memory that stores test results in a memory test device. .

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

In other words, the IC memory has an N word x 4 bit configuration or an N word x 4 bit configuration.
There is a word x 8 bit configuration in which multiple bits of data are read in parallel using the same address signal, in which case if any one of the multiple bits read at the same time is defective, all the bits are read out. In some cases, a spare column or row is substituted for a spare column or a spare row. Focusing on this, the present invention attempts to compress fail information by calculating the logical sum of the judgment results of multiple bits of data read simultaneously and using it as information to be stored in the fail memory. This achieves the above-mentioned objective of improving the cost performance of the device by increasing the usage efficiency of fail memory.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to an IC memory testing device.

The IC memory 10 inspected by the inspection apparatus of this embodiment is as follows:
The following explanation will be given assuming that the data has an N word x 4 bit configuration. Note that a memory with an N word x 4 bit configuration is divided into four mats M1 to M1 as shown in FIG.
It can be constructed by dividing the memory into M4 mats, setting the same address for each mat, and reading out data bit by bit from mutually corresponding addresses in each mat.

The inspection apparatus of this embodiment has a main body composed of a pattern generator 1, a timing generator 2, and a function test controller 3, similar to the conventional inspection apparatus shown in FIG.

Corresponding to the bit configuration of the IC memory 10 to be tested, the function test controller 3 sends 4-bit test data DATA and 4-bit expected values E1 to 4 to the application section 4 and determination section 5. E4 is supplied.

The IC memory 1o is accessed by the signal from the application section 4, and the 4-bit data (words) RDI to RD4 read out from the memory 10 as a result are supplied to the 1 determination section 5, and the above-mentioned 4-bit expected values E1 to Each is compared with E4. The determination result is determined by the determination signals J1 to J4 for each bit.
It is output from the determination unit 5 as .

In this embodiment, the 4-bit judgment signals J1 to J4 outputted from the judgment section are input to a multi-input OR gate Go, and their logical sum is calculated. And this OR gate G.

The output signal of is supplied to the fail memory 6 and the 1 judgment signal J
When any one of 1 to J4 is at a high level, II 1 tr is written to the address in the fail memory 6 corresponding to the address of that head.

As a result, if even one bit of the 4-bit data RDI to RD4 read simultaneously from the IC memory 10 is defective, a bit "" indicating that the corresponding position in the fail memory 6 contains a defective bit is detected. 1” is stored.

As described above, in this embodiment, the fail information regarding the 4-bit data read from the IC memory lO is
It is compressed at the gate Go and stored in the fail memory 6. In contrast, in conventional memory test systems, I
All fail information regarding the 4-bit data read from the C memory 10 is bit-based and stored in the fail memory 6.
It is stored internally. Therefore, according to this embodiment, the capacity of the fail memory 6 is 4
It will only cost 1/100%.

Furthermore, even if the fail memory information is compressed and stored in this manner, no inconvenience occurs when using the fail information. In other words, when the IC memory 10 has a redundant configuration in which if even one bit out of four bits of data is defective, the memory column or memory row containing that bit is replaced with a spare column or row for all four bits. There is. In that case, the identification information indicating that any bit of the 4-bit data is defective has no meaning. Therefore, even if the fail information is compressed as in the above embodiment, no problem will occur due to the redundant structure of the memory. However, depending on the memory, it may be possible to adopt a redundant configuration in which, for example, 2 bits of 4 bits of data that are read simultaneously are replaced with spare columns or rows. In that case, an OR gate Go shown in Figure 1 can be provided for each two bits that are replaced simultaneously in the redundant configuration, and the fail information regarding the 4-bit data can be compressed into 2 bits instead of 1 bit. good.

Furthermore, if the IC memory to be inspected has an N word x 8 bit configuration, the fail information regarding 8 bit data should be compressed to 1/8 or 1/4/1/2, etc. , the capacity of the fail memory 6 can be reduced.

[Effects] Since the logical sum of the judgment results of multiple bits of data simultaneously read from the IC memory to be inspected is used as the information to be stored in the fail memory, By compressing the information contained in the memory, the capacity of the fail memory can be reduced, which has the effect of improving the cost performance of the memory test device.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, fail information is compressed in the data width direction, but it is also possible to compress it in the address direction. In other words, if there is one defective bit in the same column or row in memory, the entire column or row is replaced with a spare column or row, so one piece of fail information is added for each memory column or row.
It is also possible to reduce the capacity of fail memory by allocating bits.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to the field of application for IC memory, which is the background of the invention. It can be used for testing other LSIs in general.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention applied to an IC memory testing device, and FIG. 2 is a block diagram showing a conventional IC memory testing device.
FIG. 1 is a block diagram showing an example of a memory testing device. 1... Pattern generator, 2... Timing generator, 3... Function test controller, 4... Application section, 5... Judgment section, 6 Storage device (
Fail memory), 10...Object to be measured (IC memory). Figure 1 2mc Office

Claims (1)

[Claims] 1. Supplying test data to the object to be measured, comparing the signal output from the object to an expected value to determine whether there is a defect, and storing the determination result in a storage device. I was made to
C. The inspection device is characterized in that it is configured to perform a logical sum of signals indicating judgment results regarding a plurality of signals simultaneously output from the object to be measured, and to store the result in the storage device. IC inspection equipment. 2. The device under test is a semiconductor memory device capable of reading and writing multiple bits of data in parallel, and the storage device that stores the determination results has an address correspondence with the semiconductor storage device as the device under test. An IC testing device according to claim 1, characterized in that: