JPS6258333A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To obtain the nth root with a simple constitution at a high speed by changing the coefficient of a noticed position according to the result of comparison between the nth power value of the approximate value of the nth root and the input numerical data. CONSTITUTION:The n-root C 108 of (k) figures is obtained for input numerical data A 107 of (nXk) figures which is shown in the binary numbers. In such a case, the coefficients are successively decided from the highest position of n-power figure C 108 and therefore the approximate value X 110 of the n-root C 110 is stored in an approximate value register 102. Then the approximate value X 110 is supplied to an nth power arithmetic part 101 and the nth power value B 109. A comparing part 100 compares the value B 109 with the input numerical data 107. While a noticed position designating part 104 designates successively each position (noticed position 111) of an approximate value register 102 from the highest position. Then, a coefficient setting part 103 sets the coefficient of the position 111 at the prescribed value every time the position 111 is designated. A coefficient changing part 105 changes the coefficient of the position 111 to the appropriate value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic device for calculating the n-th root of numerical data.

[Prior Art] Conventional n-th root arithmetic devices combine adders, multipliers, etc., and use Taylor expansion polynomials, recurrence formulas, etc., which is very time consuming and requires complicated circuits. Ta.

There is also a method of storing the n-th root value in a ROM and inputting the input numerical data as an address of the ROM. However, in an arithmetic device, it is usually necessary to calculate not only the n-th root but also the power, so for such cases, it is necessary to store not only the ROM for the n-th root but also the ROM that stores the multiplicative value. This is uneconomical, and the circuit size also naturally increases.

[Problems to be Solved by the Invention] The present invention has been made in view of the problems of the conventional example described above, and its purpose is to propose an arithmetic device that obtains the n-th root at high speed with a simple configuration.

[Means for Solving the Problems] In order to achieve the above-mentioned problems, for example, the arithmetic device of the embodiment shown in FIG. When determining the root ClO3, in order to determine the coefficients sequentially from the most significant value of the nth root ClO3, the approximation register 102 that stores the approximate value Xll0 of the nth root Cl0B and the approximate value xito are input to determine the nth power value B
The n-th power calculation unit 101 outputs 109, the comparison unit 100 determines the magnitude relationship between the input numerical data 107 and the n-th power value B109, and each position (attention position 111) of the approximate value register 102 is specified in descending order from the highest value. an attention point designation unit 104 to
A coefficient setting unit 10 that sets the coefficient of the attention point 111 to a predetermined value each time the attention point designation unit 104 designates the attention point 111.
3, and according to the determination result of the comparison unit 100, the CCl rank 111
and a coefficient changing unit 105 that changes the coefficients of .

[Operation] In the above configuration, the approximate value If the coefficient at position 112 is known,
The coefficient setting unit 103 sets the coefficient at the position of interest 111 to be 1°°.If the approximate value is always n-th power value B109>numerical data A10
7, and conversely, when it should be °1''', the n-th power value B1
09≦numerical data A107. Therefore, based on the magnitude determination result 106, the coefficient changing unit 105 can uniquely determine the coefficient to be ``1'' or 0''.

[Embodiments] Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings.

First, in the example shown in FIG.
It will be explained below that the coefficient of the attention point Ill is uniquely determined based on 06.

Principle of Coefficient Determination> To simplify the explanation, the explanation will be limited to the case of finding the square root. Input numerical data 107 to A
and let C be the square root. That is, C2=A.

A = -122 to C2 -1 + C2b -227 -
2+ , , , + aO. However, 8
2 to -1” 1.

Due to the circuit scale, the output 109 of the n-th power calculation unit 101 is 2
This is limited to digits. Therefore, approximation register 10
The significant figures of 2 are at most digits. Therefore, the square root C to be found (although it is actually an approximation value ignoring the decimal point) is an order of magnitude at most, and C=Ck+2 -1+ Cb-22 -2+ , , + C.

It is expressed as

First, it is shown that the coefficients in digit positions beyond the most significant (k+1 digits or more) are always "0". Now, the attention rank 111 is +1
Digit number. Then, the numerical value X set in the approximate value register 102 will be X=2 since all the lower coefficients are "011".Therefore, the quality of X=22, and on the other hand, A=C2=(ck -12 to -1+Ck-22 to -2+,,,,+
Co)? = (Cb-+2 + 20b-+Ck-2
) 22 to one 2 ÷ (Ck-+Ck-3+ Gk-2ck-
2) 22 to -3+ (Ck-22 〇 to -20 to -3+
Ck-ack-1)2 becomes 1'+...Takashi+CO2. Ok-+, Ck-2, -Go are all” 1
”, (Ck-+2+ 20
niichi+fll:ni-z) is “3” te, squirrel, matata (Ck-
+Ck-3+ Ck-2ck-2) 1fII 2 I
+......, and 22k never appears in the term C2. Therefore, C x x is obtained. By the way, if the number of significant figures is set to 1 (ignoring the decimal places), the minimum number with maximum precision is l"'.

C≦X-'1 =2 to -1=2 to -1+ ...+ 1
becomes. In other words, if we can distinguish the magnitude of A and the square value B=X2, the +1st digit coefficient of square root C is °°O°
It's time to understand that it has to be °.

In other words, by repeating the above operation, the most significant coefficient of the square root C can be determined including the position of that order.

When the most significant (k-th digit) coefficient Ck-1 is determined in this way, the approximate value X is set to X = C1, -12 to -1+ 2 to -2, focusing on the 11th digit.
>(Ch-+2'-1) 2 , the comparison unit 100 determines the magnitude relationship between A and B (=X2).
In other words, when A > B (= Since (
It can be determined that the coefficient Ck-2 of order k-1) is 0''.

If such an operation is applied to all ranks, the coefficients from the highest rank to the lowest rank are determined, and eventually the coefficients are stored in the approximate value register 102.
Find the square root of .

(Approximate Value Determination Operation) FIG. 2 is a circuit diagram of an embodiment in which the approximate value register 102 and the like in the embodiment of FIG. 1 are changed to more specific ones.

The comparator 1 corresponds to the comparing section 100 in FIG. 1, and outputs an A>B output 106 and an A=B output lO.

The n-th power ROM 2 corresponds to the n-th power calculation unit 101 in FIG.

A k-1 to AO are input as the address input, and an nXk bit value B109 to the power of n is output as data.

The approximation value setting section 102 in FIG. The nth root storage register 3 is Qk”Q+
It consists of a number of flip-flops and outputs the n-th root of a number of digits. The point-of-interest designation shift register 4 consists of a number of flip-flops of Ph''P+, which are set one by one in order from Pk - PI to designate the point of interest.

Flip-flop Pk of attention point designation shift register 4
The clock of P+ is the clock 6 of the arithmetic unit. on the other hand,
Each clock input of a flip-flop Qk"Q+ is an output change (set→reset) of the corresponding flip-flop Pk/-PI, that is, when trying to move the attention point from one place to the next. , the flip-flow of the n-th root storage register 3 corresponding to the current position of interest changes in accordance with the (A>B) output 106. These correspond to the coefficient changing unit 103 of the embodiment shown in FIG. Furthermore, the flip-flop Pl output ready (READY) signal of the attention point designating shift register 4 is a signal that indicates to the external CPU that the calculation of the approximate value has been completed.

To explain the operation step by step, a signal start pulse 5 for starting calculation is sent from an external control device such as a CPU (not shown).
When , the start pulse 5 resets all the flip-flops of the n-th root storage register 3, sets only the flip-flop Pk (top) of the attention point specification shift register 4, and sets the other flip-flops P by -1. ””P.I.
is reset. That is, the attention point specification shift register 4
focused on the top. Then, the approximate value Xll0 becomes (
With the value of 10...0)8 (B represents a binary value), the address Ak of the n-th power ROM2 is determined via the OR gate.
-+-Input to An. The n-th power ROM2 has an approximate value x11
Input 0 to the address input and set the nXk bits to the power of B
109 is output to the converter l. Here, the cycle of the clock 6 is longer than the cycle time of the n-th power ROM 2, and is synchronized. That is, the next clock 6 is input after the output of the comparator 1 is determined, and the point of interest is shifted to the next one.

Comparator l is numerical data A107 and n-th power value B109
are compared, and their size determination results (A=B) 10 and (A>B) 106 are output.

Now, suppose that the approximate value Xi l O (10...-0) s is larger than the n-th power value B109. Then, (A>B)
106 is "°O°", the flip-flop Qk of the nth root storage register 3 is about to be reset (as mentioned above, the only flip-flop that is energized is the flip-flop corresponding to the position of interest). When the clock 6 is input, the attention point designation shift register 4 shifts by one.In other words, by catching the change in this PK pointing to the next attention point (corresponding to the flip-flop PK-1), the flip-flop Qk Reset.

The next approximate value is (oio...0)B. Through the same operation as described above, the size determination result is output to the comparator 2, but this time let us assume that A>B. Then, (A>B) 106 becomes "1", and only -1 is set in the flip-flop Q, which is energized by the flip-flop PK-1, when the next position of interest is shifted. In this way, the approximate value (010
...O)B has been stored.

By repeating the above operations, the nth root coefficients are determined in order from the highest order. FIG. 3 shows a timing chart of the above operation.

Here, the signal ready 115 will be explained.

As mentioned above, since the flip-flop P1 is the final stage of the attention point designation shift register 4, the signal ready 115
is "1", which indicates the end of the calculation operation.The CPU etc. know the completion of the calculation by looking at this signal ready 115, and take in the output of each stage of the n-th root storage register 3 as the n-th root. When (A=B) 10 of comparator 1 becomes 1', the n-th root has been found, so the operation ends in the same way.Therefore, (A=B) 10 is forcibly connected to the flip-flop PI. In this way, the calculation result can be obtained quickly without having to wait for the calculation to finish up to the final stage.

<Extension of Example> The above explanation was given for the case of square root, but generally n
It is easily understood that this can also be applied to root roots. in this case,
The above explanation is based on the highest level of input numerical data A (Most 51
gn1ficant Bit) is at the nXk position, but when this is not the case (for example, the topmost bit is (
nXk+ 1) etc.), for example, the highest coefficient is
If you increase the number of digits as O゛ and perform the above operation, there will be no problem.

Generally, within an arithmetic device, when handling numerical data and performing arithmetic operations, processing for the significant figure part and processing for the decimal point position are often performed separately. This is because the decimal point position can basically be handled by shifting, but
This is because the calculation itself must be performed for the significant figure part. From this point of view, Figures 1 and 2
The arithmetic device shown in the figure focuses on processing the significant figures, and does not care about the position of the decimal point.

Therefore, in the embodiment of FIG. 1 or 2, the general theory of how to handle the number of digits of the input numerical data A107 is that if the number of significant digits of the n-th root is calculated in digits, then , the number of digits of the input numerical data 107, its MSH
Regardless of the digit position, add "o" to the top and make nX
It is sufficient to process it as k digits.

A method to uniformly handle such cases is to introduce floating point numbers. Therefore, an example for calculating the n-th root of floating point data will be described below.

Floating point data> Figure 4 shows the floating point display of numerical data inside the arithmetic unit.
It is l bit long, and the mantissa part 60 is -1 to n in m2.

2 is the bit length. There are usually two ways to display the mantissa part 60: a case where the decimal point is placed on the leftmost side, and a case where the decimal point is placed on the rightmost side. In this embodiment, the case where the decimal point is placed on the rightmost side will be explained first, and then the case where the decimal point will be placed on the leftmost side will be explained.

(Example for processing floating point data) To simplify the explanation, the case of square roots will be explained. In the embodiment shown in FIG. 5, numerical data in which the exponent input 29 is 81-1 to eo and the mantissa input A21 is 1 to 1 to m2 is input, and the exponent output 28 is e)-2 to eo. , mantissa output 13
Find the square root where is mk-1''mO.

In the figure, 27 is a latch that stores the exponent part, and 20 is a comparator that compares the magnitude of the mantissa input 21 and the output 22 of the square ROM 30, which corresponds to the comparison section 100 in FIG. 3
0 is a ROM that squares the approximate value 31 from the n-th root storage register 3, and corresponds to the n-th power calculation unit 101 in FIG. This ROM 30 is basically the same as the ROM 2 shown in FIG. 2. Since the n East root storage register 3 and the attention point designation shift register 4 are the same as in the embodiment shown in FIG. The same is true for .

The explanation thereof will be omitted, and the processing of the exponent part 30 will be explained here.

<Processing of exponent part) When the decimal point is on the rightmost side, the basic operating principle of exponent part processing is as follows.

Generally, floating point display data Y with a mantissa part and an exponent part is Y=aX20. ,,,,,,,,,,,,,,,,,,,(
Considering the case where the index is an even number (b=2+s) (m is a positive integer), equation (1) becomes =aX22-
becomes. Therefore, to find the square root of Y, the exponent part only needs to be shifted one bit to the right, and the mantissa part can be quickly expressed as a floating point value by storing only the square root of a in the square ROM 30. Easily find the square root of the data. For example, when the exponent part is latched into the latch 27, it is shifted by one bit and latched.

However, when the lowest pix of the exponent part 30) eo is °"1" (
That is, when the exponent part is an odd number), if the exponent part is shifted, valid data of the exponent will be lost, so the following procedure is performed. If b is an odd number, that is, b = 2 m + 1 (m is a positive integer), then use formula (1) as =+=aX2X22m =2
aX221. ．． ．． ．． ．． ．． ．． If you transform it into (2), there is no problem even if you shift the exponent part without losing the significant digits, so,
The lowest eO of the exponents eI-1 to eo is input to the hump parator 20 via the signal line 25. In this case, mantissa human power A
If the entire 21 is shifted one bit to the left, the mantissa will be doubled, which is convenient. Also, even if the exponent is an even number, even if the lowest eo is input to the comparator 20 in this way, it will be 0'', so there is no need to shift it.In this way, when the decimal point is at the rightmost position, This can be easily obtained using the example shown in FIG.

(Example in which the decimal point is on the leftmost side) In this example, placing the decimal point on the leftmost side means placing the decimal point on the leftmost side in the mantissa, and the most significant bit is always “1”.
Normalize it so that °゛ is 0, for example °”1
1.0O101X 23"is' 1.IQOlolX
24”, and in this case of normalization, naturally the squared RO
The data stored in M30 must also be normalized.

However, for example, the number (1,1)e)2 is ((1,1)
)a)z=((1,5)o)2=((2,25)o)
= ((10,01)a), and the decimal point position shifts to the right (O means decimal), which practically cannot be compared by the comparator 20. Furthermore, as mentioned above, when the exponent part is an odd number, if the lowest eQ of the exponent part is inputted to the comparator 20 via the signal line 25 in FIG. The decimal point will be shifted and comparisons will not be possible.

In order to eliminate such inconveniences, this embodiment adds two features to the embodiment shown in FIG. 5. One of them is to connect the comparator 20 to a 1-bit register 4 as shown in FIG.
It consists of a register 41 for 0 and 2 bits, a comparator 42 for (2k+1) bits, a register 44 for 1 bit, a register 43 for 2 bits, and the like. The mantissa 21 is input to the 2-bit register 41. The lowest exponent eQ is input to the register 40. Note that the decimal point position of the mantissa 21 remains unchanged.

The second idea is to configure the ROM 30 as shown in FIG. The ROM in Figure 7 is
- As an example, an 11-bit input and 22-bit output is shown. The ROM7 address input means the input numerical value to be squared, and the ROM output is the squared numerical value. In particular, the decimal point position is between r21 and r2G, and the bit of r22 is a bit indicating that the result of squaring overflowed "l". It is known in advance what numerical value should be input to generate the r72 bit. In order to make the explanation concrete, "1.4150390825" (each J-
The case where 2) is input will be explained. ""10110101001°" is input to the ROM 30. At this time, the mantissa outputs r21 to ro of the ROM 30 are °' 1
000000000100110010001" is output. Bit r22 also becomes "1'".

These (2+1) bits r2k"ro are input to the registers 43 and 44, respectively, as shown in FIG. It is also possible to determine the magnitude relationship by comparison.In particular, if such normalization is used, compared to the normalization method described above in which the decimal point position is set to the rightmost side, the time required for shifting is not required, and the speed is further increased.

As explained above, it has been demonstrated that the square root can be easily obtained even for floating point data using any normalization method.

<Considerations on Modifications> The embodiments shown in FIGS. 5 and 6 are for finding square roots. For the n-th root of input numerical data of integer type, Figure 1,
The configuration shown in FIG. 2 can be used as is.

On the other hand, referring to the method of finding the nth root of Y=aX2b (where n=21.j is an integer) for floating point numbers, for the exponent part, as with the square root, shift the focus by j and perform exponent operation. Just enter it in the section, %. R of the mantissa
The data in OM is as follows. The exponent data lost due to shifting j bits is 1, 2, . ...
, n-1. Therefore, (a)', (2a
)n, (3a) n,...

((n-1)a)l/n is previously stored in the ROM, and one of these is stored as the lower bit e of the exponent.
It can be selected depending on the value of n-1 to eQ. In this way, n
It can also perform high-speed calculations on roots.

By the way, in the floating point display above, the topmost value is always 61.
Therefore, in order to reduce the capacity of the ROM, it is possible to consider a method in which data is not directly input into the ROM.

<Effects of the Embodiment> From the embodiment described above, (1): The n-th root of an input numerical value of an integer type or a floating point type can be determined at high speed. In this case, the required number of clocks is half the number of bits of the input numerical value (the mantissa part in the case of floating point), and the clock time is only the ROM access time and comparator delay time. be.

■: During the calculation process, when the = output of the comparator becomes °“l”, the n-th root is obtained at that point, and further speeding up can be achieved.

(2): The circuit configuration is well-organized, highly expandable, and therefore easy to integrate into an LSI.

■: As before, two ROMs for n-th root and n-th root
This eliminates the need to separately provide a separate circuit, making it suitable for circuit miniaturization.

[Effects of the Invention] As explained above, according to the arithmetic device of the present invention, the n-th root of any type of numerical value can be obtained at high speed.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of the embodiment, FIG. 2 is a circuit diagram of another embodiment, and FIG. 3 is a timing chart of operations for determining coefficients in the embodiment of FIG. Fig. 4 is a diagram explaining the structure of floating point data, Fig. 5 is a circuit diagram of an arithmetic unit for obtaining the nth root of floating point data, and Fig. 6 is a detail of the comparison section of Fig. 6 in a modified example. FIG. 7 is a block diagram showing an example of the contents of a square ROM when calculating a square root. In the figure, 1.20... comparator, 2... nth power ROM, 3
... nth root storage register, 4 ... point of interest specification shift register, 5 ... start pulse, 6 ... clock, 21 ... mantissa human power A, 22 ... square value, 10.2
3...A=B, 24,106...A>B, 25...
・Signal line, 26...Exponent input (el-+ ~ e+)
, 27... Latch, 28-... Exponential output (el-2~
e+, ), 30-square ROM, 31, 110
...Approximate value X, 40, 41.43, 44. ...Register, 42...Comparator, 100...Comparison unit, 101
. . . n-th power operation unit, 102 . . . Approximate value register, 10
3...Coefficient setting section, 104...Attention point specification section, 10
5...Coefficient change unit, 108...n-th root C, 109.
... n power value B, 111 ... attention level, 112 ... higher than the attention position, 113 ... lower than the attention position, 115.
...Signal ready.

Claims (5)

[Claims] (1) An arithmetic device that calculates the nth root of input numerical data includes an approximate value storage section that stores an approximate value of the nth root, and calculates the nth power value of the approximate value stored in the approximate value storage section. an n-th power calculation unit, a comparison unit that compares the input numerical data and the n-th power value and outputs a result of size determination, and a focused position of the approximate value to determine a coefficient for each position of the approximate value. an attention point specifying section that specifies the attention point in a predetermined order; a coefficient setting section that sets a coefficient of the attention point to a first predetermined value each time the attention point specification section specifies the attention point; and a coefficient changing unit that changes the coefficient of the attention position to a second predetermined value according to a result of size determination. (2) The predetermined order in which the attention point designation section specifies the attention points is a descending order from the highest approximate value, and all coefficients higher than the attention point are known in the approximate value storage section. , the coefficients in the lower digits are all “0”, and the first predetermined value is “1”
The second predetermined value is "0" when the approximation value is set so that the n-th power value is larger than the input numerical data. The computing device according to scope 1. (3) When the attention point specification section specifies all the approximate values, or when the comparison section determines that the size determination results are equal, use the n-th root to find the approximate value in the approximate value storage section. An arithmetic device according to claim 1 or 2, characterized in that: (4) The arithmetic device according to any one of claims 1 to 3, wherein the input numerical data is numerical data expressed as a floating point number. (5) The arithmetic device according to any one of claims 1 to 4, wherein the n-th power arithmetic unit is constituted by a ROM.