JPS625754A - Stabilizing device for reproducing operation - Google Patents

Abstract

PURPOSE:To stabilize an operation by providing a means that keeps correcting voltage constant at transition time such as power-on when a channel is switched and performing the cancel of the fixed value corresponding to the reducing time of the number of BCH pulses, in a case that the frequency control voltage of a PLL circuit is corrected according to the correcting number of the BCH. CONSTITUTION:When the channel is selected at a channel data generating part 44, a switch SW2 is controlled and the output of a fixed counter 55 is supplied to an updown counter 48 and the output pulse width of a PWM circuit 53 is fixed at a fixed level. When the counting value of the BCH pulse of a counter 40 is reduced under a fixed value, by stabilizing the PLL circuit in a carrier reproducing part, the content of the counter 40 is decided by a defeat circuit 43 and the switch SW2 is controlled with the decided result. At such a time, the output of the fixed counter 55 is made as off and the upper limit/ lower limit detection operation of lead-in frequency is started.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a receiving operation stabilizing device used, for example, in a PCM audio receiver.

[Technical background of the invention and its problems]

In recent years, with the development of broadcast media, multi-channel audio broadcasts, teletext, facsimile broadcasts, still image broadcasts, high-definition television screen broadcasts, satellite broadcasts, etc. are being carried out. In these broadcasting formats, multi-channel transmission is often performed using r-sotaru code transmission in order to use lines efficiently.9 For example, in satellite broadcasting, in order to ensure the transmission of television soyon signals, the number of channels is divided into 100-odd bits every 6 MHz. Ten channel groups are set up to relay GHz band signals from the earth to the satellite.
We are now broadcasting again to a large number of receiving stations around the globe.

Furthermore, when transmitting audio signals using such channel groups, the 6 MHz band is
For example, the signals of the first channel of the audio service to the fifth channel of the audio service are divided into five and transmitted. Note that one of such audio signal transmission methods is a phase shift key ink (PSK) modulation method. This phase shift key ink modulation changes the phase of a carrier wave depending on a code, determines the basic phase of the carrier wave, and transmits by assigning a phase change with respect to this phase to a code. On the receiving side, the carrier is regenerated based on the baseband signal, signal processing is performed, and the audio signal is demodulated.

Such phase shift key ink modulation is preferable because it has good efficiency and can increase the carrier power to noise power (C/N) ratio. In particular, 4-phase PSK modulation has high frequency utilization efficiency.
It is also an excellent transmission system in that bit errors can be easily corrected.

In this 4-phase PSK modulation, the phase of the carrier wave for the audio signal is changed to 4 phases (O', 900.1800.270017), and then a summation operation is performed to convert the data into gray. In the Gray code obtained in this way, when consecutive numbers are expressed in binary, the distance between each piece of information (Hamming distance) is 1, so it is easy to correct bit errors.

On the receiving side, a PLL including a voltage controlled oscillator (VCO)
The circuit performs pace pan P switching, selects a desired channel group, selects an arbitrary channel from the selected channel group, and performs four-phase phase demodulation of the audio signal.

In order to reproduce the 4-phase PSK signal used for transmitting such audio data, the carrier wave is regenerated, the phase is determined, and the data is demodulated. However, if the carrier wave, which is the reproduced carrier, is not regenerated correctly, the reproduced signal will not be reproduced. Bit errors occur, making it difficult to reproduce correct data. Therefore, in order to enjoy the characteristics of 4-phase PSK transmission, which has a high CA ratio and excellent bit error characteristics, it is necessary to suppress frequency fluctuations as much as possible in the frequency conversion leading to carrier wave regeneration. . In order to further reduce the bit error υ of the reproduced data, 4-phase PS
The voltage controlled oscillator (VCO) of the PSK demodulator that reproduces the K carrier wave must have as little frequency fluctuation as possible.

In other words, if frequency fluctuations occur in the frequency conversion means for obtaining the baseband signal, and if the pull-in frequency of the voltage-controlled oscillator that reproduces the carrier wave is not appropriate, bit errors will occur, and if the data is audio, produces a so-called click noise.

Furthermore, when data is demodulated by synchronous detection of a 4-phase PSK signal, the data error rate Pa is calculated by subtracting Φ(z) from the following (1
), it is given by the following equation (2).

Pe=2(1-Φ(7 possible balls)) −・−
-(2) And the larger the CA ratio, the lower the error rate. Therefore, in order to lower the error rate, frequency conversion to obtain a baseband signal and voltage controlled oscillator in carrier wave regeneration are necessary. It is necessary to properly adjust the pull-in frequency and reproduce a carrier wave with accurate pull-in frequency and phase.

[Purpose of the invention]

This invention was made to deal with the above circumstances,
The BCH code of the reproduced data is used to sweep the oscillation frequency of the oscillator looped by the carrier regeneration circuit that demodulates the signal, and to obtain a stable point of the frequency pull-in state of the phase-locked loop using this oscillator. The range of the pull-in frequency is determined from the value of the number of error detections.

Next, the present invention utilizes the detection data indicating the above-mentioned pull-in frequency range to calculate optimal data for determining the oscillation frequency of the voltage-controlled oscillator of the above-mentioned phase-locked loop circuit, and demodulates the received or schemed signal. Detect the stable point of the system.

As described above, the present invention detects error conditions in reproduced data by varying the oscillation frequency of the voltage controlled oscillator, but in order to prevent erroneous detection from occurring in the detection aj operation itself, In particular, it is an object of the present invention to provide a reproduction operation stabilizing device that can arbitrarily vary the defeat period of the above-mentioned sweep 7° operation by effectively utilizing the outputs of the defeat circuit and the BCH correction circuit during transitions such as when switching channels. do.

[Summary of the invention]

For example, as shown in FIG. 2 and FIG.
The present invention is characterized by means for controlling the oscillation frequency of the voltage controlled oscillator 19 forming a phase-locked loop within the SK demodulator 17. In particular, when switching channels, it is necessary to wait until the oscillation operation of the voltage controlled oscillator 19 stabilizes. This is realized by the fixed counter 55, upgrade counter 48, and PvVM circuit 53 shown in FIG.

During normal operation, the frequency of the voltage controlled oscillator 19 is
Fine adjustment is made according to the number of BCH/f pulses (data error bits), and the start point of the adjustment operation is determined by setting the time when the number of BCH4 pulses has decreased.

[Embodiments of the invention]

An embodiment of the present invention will be described in detail below with reference to the drawings.

In the phase modulation method, a signal is sent out based on a predetermined phase of a carrier wave, and the amount of phase change corresponds to a code, and the receiving side regenerates the carrier wave from the received signal and demodulates the transmitted data. It has the advantage of a good ratio. and P
Four-phase PSK is one of the SK transmission means. 4
Phase PSK has higher transmission efficiency than 2-phase PSK, and
Compared to phase PSK, the structure of the modulation/demodulation circuit is simpler, and bit error correction can be easily performed.

In this 4-phase PSK for satellite broadcasting (SHF broadcasting), the audio signal is converted into a 2.04 Mbit/s digital signal, and then the 5.73 MHz subcarrier is subjected to 4-phase PSK processing using this digital signal for transmission. Let's do it. and 5,73 M
The phase of the Hz subcarrier is changed to 4 phases, and the quantization is changed to 14
It is transmitted in 10 bits using companding at the time of punishment. A BCI (error check code) is added to the audio data to be transmitted in order to improve bit errors during reception.
It performs digital signals such as /S conversion and sends them out in the form of an interleaver.

On the receiver side, which receives and reproduces the transmitted data, the frequency is converted to a predetermined frequency according to the selected station, and then a PSK demodulator reproduces a subcarrier of, for example, 6.4 MHz to demodulate the data. Let's do it.

FIG. 1 is a schematic diagram showing an example of a carrier wave recovery circuit for PSK signals according to the present invention. The signal input to the input terminal 1 is converted to a predetermined frequency by the frequency conversion means 2,
Input to carrier wave regeneration circuit 3. The output of carrier wave regeneration circuit 3 is applied to data processing circuit 4 and phase comparator 5. The output of the phase comparator 5 is applied to a voltage controlled oscillator 7 via an adder 6 to control the phase of its oscillation output. Then, the output of the voltage controlled oscillator 7 is sent to the frequency conversion means 2 and the carrier regeneration circuit 3.

′! ! In response to the detection of the error rate of the demodulated data of the data demodulation circuit 4, the adder 6 adds the correction data generated by the frequency correction data generating section 8 to the output of the phase comparator 5 and supplies the added data to the voltage controlled oscillator 7. Demodulated data is then obtained from the data demodulation circuit 4.

FIG. 2 is a block diagram showing one embodiment of the present invention, in which the received RF signal input to the input terminal 10 is input to the first mixer 1
1 and a first frequency converter 13 consisting of a first oscillator I2.
and a second frequency converter 16 consisting of a second mixer 14 and a second oscillator 15, for example, 6.4 MH
Convert the frequency to the baseband frequency of z. If frequency fluctuations are not sufficiently suppressed during this frequency conversion, the carrier wave will not be accurately regenerated later when the carrier wave is regenerated by a carrier wave regeneration circuit, resulting in bit errors.

Therefore, the human RF multiplied signal frequency fay, the frequency of the second oscillator 15 of the second frequency converter 16 fo s C2
It is necessary to suppress frequency fluctuations such as these as much as possible.

As shown in equation (2) above, the deterioration of C has a large effect on bit errors, so unless frequency fluctuations accompanying frequency conversion are sufficiently suppressed, it is not possible to obtain a proper baseband ° signal. .

In the embodiment shown in FIG.
I'm trying to return to.

The influence of the frequency fluctuation of the input RF signal and the fluctuation of the oscillation frequency of the second oscillator 15 is reduced. The input RF signal input to the input terminal 10 is The oscillation frequency fosc1 of the oscillator 12 is converted into fly, which is the difference. fly f
″j is given by the following equation (3).

f1y=fo8c fRv=・
(31 and the output frequency f of the first frequency converter 13
1r is connected to the second oscillator 15 by the second frequency converter 16.
The oscillation frequency foac2 is converted to this difference frequency fo. fo is given by the following equation (4).

fo-foac2J'IF mocking=
-(41 and the output of the second frequency converter 16 is PSK
Input to demodulator 17. The carrier regeneration circuit 18 of this PSK demodulator 17 regenerates the carrier wave, but in order to prevent the frequency fluctuation, the oscillation output of the voltage controlled oscillator 19 and the output of the carrier regeneration circuit 18 are combined in phase with the phase comparator 20 of @l. voltage controlled oscillator 19 via adder 21.
A phase opening and a croup are configured to stabilize the frequency.

In addition, the output frequency of the voltage controlled oscillator 19 is multiplied by the frequency divider 22.
This frequency-divided signal f is applied to one input of the second phase comparator 23.

On the other hand, the output frequency fotzc1 of the first oscillator 12 is set to ν
The frequency is divided by the frequency divider 24, and this frequency divided signal foac1A/i
is applied to the other input of the second phase comparator 23. Then, the comparison output of the second phase comparator 23 is applied to the first oscillator 12 via the low/yas filter 25 to control the phase of the oscillation output.

Therefore, the following equation (5) holds true during the frequency conversion process.

Here, due to the PLI and operation of the PSK demodulator 17, if the input frequency fo and the output frequency f of the voltage controlled oscillator 19 are equal, the following equation (6) holds true.

However, Equation (6) where K=I indicates that the influence of any fluctuation in the frequency of the input RF signal and the oscillation frequency fosc2 of the second oscillator 15 is reduced by 1/(1+K) times. Express it. Therefore, frequency fluctuations of the input signal to the carrier regeneration circuit 18 can be suppressed.

By stabilizing the output frequency fo of the second frequency converter 16 in this way, it is possible to reduce bit errors in the demodulated signal. When r changes to the frequency of the input RF signal, the pull-in frequency of the voltage controlled oscillator 19 itself is ±200 to 300 Hz, but with the configuration shown in FIG. 2, M frequency division and N frequency division are performed. Therefore, by following equation (6), the pull-in range can be set to approximately ±5 kHz.

In the PSK demodulator 17, the purpose of widening the pull-in range as described above is when the carrier regenerator 18 regenerates the carrier according to the detection result.In the frequency pull-in critical region, the detection output becomes inappropriate and the phase of the reproduced carrier changes. It is possible to prevent an incorrect phase. That is, the carrier regenerator 18 uses a detector (not shown) to determine the carrier corresponding to the incoming data from among the four carrier phases at 6.4 MHz, and in response to this result, the voltage controlled oscillator 1
Control the oscillation phase of 9 @In this case, voltage controlled oscillator 1
If the pull-in range of 9 is narrow, the detection output as oscillation phase control information becomes small, making it impossible to control the oscillation phase of the voltage controlled oscillator to an appropriate phase among the four phases.

As a result, the reproduced carrier has an incorrect phase, and if the transmitted data is demodulated in this state, a bit error will occur.

Therefore, with the configuration shown in FIG. 2, it is possible to suppress frequency fluctuations when converting the input RF signal to the input frequency fO for the PSK demodulator 17, and to widen the pull-in lens of the voltage-controlled oscillator 19 of the PSK demodulator 17. , input RF
It is possible to convert the signal to baseband ° frequency.

Furthermore, in order to correctly demodulate the transmitted data, the pull-in frequency itself for the voltage controlled oscillator 19 needs to be set to an appropriate value. For this purpose, control is performed by adding correction data obtained by detecting the error rate of demodulated data to the control voltage applied to the voltage controlled oscillator 19.

A configuration for optimizing the pull-in frequency of the voltage controlled oscillator 19 will be described below. That is, correction data calculated from the error rate of data obtained by demodulating transmission data is added to the output of the phase comparator 20 as control information.

Therefore, by the PLL method of base pan P switching, P
The signal obtained at the output of the SK demodulator 17 is applied to a data processing circuit 26, and subjected to digital signal processing such as Gray conversion, differential calculation, and parallel-to-serial conversion to obtain serial PCM data. Then, this PCM data is input to the PGM data processing circuit 26, and first, the PCM data is input to the frame synchronization circuit 27.
Perform frame synchronization on data. In addition, the 28 timing circuits provide control clocks necessary for PCM data processing.
Synchronize with CM data.

Further, the deinterleaving circuit 29 temporarily stores the data transmitted by interleaving in the random access memory 30 to prevent the generation of first-order noise, and deinterleaves the data. Then, the original data of the audio data to be reproduced is obtained. Furthermore, the control bit correction circuit 3 checks whether or not there is an error in the control signal included in the transmission frame.
It is detected and corrected.

On the other hand, vengeance! To detect false seconds on data, the output of the deinterleave circuit 29 is input to the BCH correction circuit 32, and double error detection is performed on the BCH code. In this case, data is corrected as well as error detection. After error correction is performed on the Lenz data portion of the audio data in the corrected PCM data in the UBcH code correction circuit 33, Lenz error interpolation is performed on the Lenz error interpolation circuit 34,
This data is sent to the high-order bit majority protection circuit 35.If an error occurs in the high-order bits of the data on the transmission path, a majority vote is taken between the high-order bits of the frame, and the result is transferred to the high-order bit data. This protects against errors. Also, the expansion circuit 36
performs reverse expansion processing on the compressed data, and correction information for the above-mentioned errors, including this expanded data, is sent to the reproduced data generation circuit 37, and then to the D/A converter 3.
8 to perform analog conversion to obtain an analog audio signal.

The quality of the demodulated signal obtained by such a method depends on the stability of the reproduced carrier in the carrier recovery circuit 18, so the number of errors detected by the BCH correction circuit 32 of the PCM data processing section is added to the control voltage for the voltage controlled oscillator 19. The correction data referenced is added to stabilize the pull-in frequency.

That is, by stabilizing the pull-in frequency according to the error detection result for the reproduced PCM data, the carrier wave reproduced by the PSK demodulator 17 is controlled to an appropriate value, thereby reducing bit errors in the reproduced data with respect to the transmitted data. .

The voltage controlled oscillator 19 is then controlled based on the demodulated data by the reproduced carrier wave, and the control information at this time is obtained from the error detection result by the BCH correction circuit 32. Based on this detection result, that is, information corresponding to the number of errors, the frequency correction data generation section 39 generates correction data, and this voltage is superimposed on the output voltage of the phase comparator 20 by the voltage superimposition means, that is, the adder 21. The sum is added and applied to the voltage controlled oscillator 19 to stabilize the frequency of the reproduced carrier wave.

The frequency correction data generation section 39 uses a counter 40 to
The number of errors detected in the correction circuit 32 is counted, and this count value is given to the Menls width modulation section 41. The Noyals width modulation section 41 performs pulse width modulation according to the count value of the counter 40 and supplies this output to the adder 2 via the filter 42.

Note that the voltage of the correction data applied from the frequency correction data generating section 39 to the adder 2 is determined as follows. When the BCH correction circuit 32 detects an error, in response to the fact that the oscillation frequency of the voltage controlled oscillator 19 deviates from its pull-in range, it sweeps the frequency from a frequency lower than the lower limit of the pull-in range to a higher oscillation frequency. Then, the lower limit frequency that falls within the pull-in range is obtained, and the upper limit frequency that falls within the pull-in range is obtained by sweeping the frequency so that the oscillation frequency is lowered from the upper frequency range than the upper limit of the pull-in range. Then, the appropriate pull-in frequency is calculated from these two values. The voltage corresponding to this appropriate pull-in frequency and the output pulse width of the pulse width modulation section 4 becomes the voltage of the correction data.

When detecting the critical frequency of the pull-in range, if the voltage-controlled oscillator 19 oscillates at a frequency within the pull-in range, pull-in may not occur and the upper and lower limit frequencies may not be detected correctly. For this reason, a defeat circuit 43 is provided, and when the channel data generating section 44 selects a station, turns on the power, etc.,
An operation is performed to forcibly remove the oscillation frequency of the voltage controlled oscillator 19 from the pull-in range.

TA775 is an integrated circuit element for QPSK Ol tuning.
1P (model number, manufactured by Toshiba Corporation) is available. This integrated circuit has built-in AGC circuits, phase-locked detection circuits for QPSK demodulation, clock recovery PLL circuits, etc., as well as differential calculations and PLL circuits.
- Performs digital processing such as s conversion.

FIG. 3 is a circuit diagram showing details of the correction data generating section 39. That is, when the channel data generation section 44 is operated to select a channel, the defeat circuit 43 first outputs a defeat signal. This defeat/arm pulse resets the counter 40 that counts the BCH/4 pulse.

Thereafter, the up/down counter 45 is used to set allowable counting values of the counter 40 corresponding to the upper and lower limit frequencies of the pull-in range of the voltage controlled oscillator 19. In this way, the count tolerance value of the counter 40 is set.

FIG. 3 is a circuit showing the details of the correction data generation section 39 in FIG. 2 above, and corresponding functional parts are given the same reference numerals. Demodulator 17
It has a function of correcting the control voltage that controls the oscillation frequency for the voltage controlled oscillator 19 that constitutes the oscillator 19 to prevent malfunction of PSK demodulation. The voltage value to be added is controlled depending on the degree of data error in the data demodulated by the PCM data processing section in FIG. This is based on the fact that if the oscillation frequency of the voltage controlled oscillator 19 of the PSK demodulator 17 deviates from a normal value, data errors will occur in the data demodulated by the PCM data processing section.

That is, if the voltage to be added to the adder 21 is controlled according to the number of data errors detected by the BC'H correction circuit 32 of the PCM data processing section, the voltage controlled oscillator 19
oscillates at a predetermined frequency. As a result, II) a carrier wave having a predetermined phase for PSK demodulation is regenerated.

In this way, the correction data generating section 39 shown in FIG.
Occurs as waves.

The number of errors in the demodulated data is detected by counting the output pulses of the BCH correction circuit 32 with a counter 40. Depending on the number of pulses counted by the counter 40,
A PWM wave is generated by a correction data generating section 39. This operation will be explained below.

First, when a channel is selected by operating the channel data generating section 44, a defeat pulse is generated from the defeat circuit 43 at the initial stage of channel selection. This defeat pulse resets the counter 40 that counts the BO (pulses).

Thereafter, the up/down counter 45 is used to set the count tolerance value of the counter 40 corresponding to the upper and lower limit frequencies of the frequency pull-in of the voltage controlled oscillator 19. this is,
Even though the number of errors in the demodulated data is small, if the voltage controlled oscillator 19 is controlled, the PLL including the voltage controlled oscillator 19 becomes unstable. When controlled, vC
o This is done in order to prevent the absolute value of the control voltage from becoming an excessive voltage, affecting the stability of the system, and furthermore, preventing the problem of being drawn into a frequency corresponding to a station different from the current station.

When a defeat pulse is generated in the defeat circuit 43 during channel selection, a predetermined value N is read out from the RAM 47 and preset in the up/down counter 45 via the CPU 47. In this state, the next data packet arrives, the reset of the counter 40 is released, and the BC
A count of H pulses is made. The output of the counter 40 is C
The CPU 47 adds, to the up/down counter 45, 4 pulses corresponding to the 7 pulses of error detection counted by the counter 40.

In this case, the up/down counter 45 performs an up-counting operation, and an image signal having an arm width corresponding to the count value is obtained at the output of the PWM circuit 53. When the up/down counter I450 count value increases, PWM circuit 5
The voltage obtained by smoothing the signal obtained from the output of adder 2 increases, and the voltage value added to adder 2 increases. For this reason, the oscillation frequency of the voltage-controlled oscillator 19 is initially forcibly set lower than the lower limit frequency of the frequency pull-in range, and is set outside the pull-in range, and the voltage-controlled oscillator 19 is moved into the pull-in range. At this time, the count value (Nl +NL, ) of the up/down counter 45 is made to correspond to the lower limit frequency of the pull-in.

Next, do the same for the incoming data packet,
Reset counter 40 L,! The pressure controlled oscillator 19 is brought into a state where the frequency exceeds the upper limit frequency, and the frequency is removed from the state where the frequency is pulled. At this time, the value N stored in the RAM is
7 to the hour 2 down counter 45. From this preset value N, the up/down counter 45 performs a down-count operation according to the number of erroneous data counted by the counter 40. As the down count progresses, the PWM circuit 53 is activated by the CPU 47.
When the voltage generated at decreases, the voltage controlled oscillator 19 becomes
This becomes the upper limit frequency of the frequency pull-in range, and the state is in the frequency pull-in range of 19 voltage controlled oscillators. The value of the up/down counter 45 at this time is (N, -NU), and this value is written into the RAM 46K.

In this way, at the initial stage of channel selection, A receives the above upper limit count value (hh NU) and lower limit count value (Nl +NL).
are written into RAM 46, respectively.

Further, the upper and lower limit values are set as regulation data for the up/down counter 48.

That is, the counting range of the up/down counter 45 is (N1+
It is set between (NL) and (N, + NU).

The average value of the upper and lower limit values written in the RAM 46 is calculated by the CPU 47, and the value of the up/down counter 48 is set as the average value.

From the next data packet, an up/down counter 48 is started depending on the number of data errors detected by the counter 4o.
is controlled, and a bacterial solution with a pulse width corresponding to the BCH"e pulse is obtained at the output of the percentage circuit 53. This operation is performed as follows.

The output of the counter 40 that counts BCI (/f pulses) generated in response to data errors is applied to a control pulse generator 49.
It has a function to store the output of 0 for every data/4 bits,
Previous data iQke.

A value corresponding to the t4 pulse number is generated according to this difference. At this time, if the count value of the current data packet is smaller than the count value corresponding to the previous data packet, a negative signal is generated according to the difference.

The above control) SW connected to the 9th pulse generator 49, the slave control circuit 5oVi, the above control/4th pulse generated in the 49th pulse depending on whether it is a positive or negative shift.
I@- to control.

In other words, when the control /4' pulse generator 49 generates a positive pulse, the /4' pulse is supplied to the increment 51 via the terminal Tl, and conversely, the control /4' pulse generator 4
If the 7f pulse generated at 9 is negative, the terminal T!・The mother rus is supplied to the decrement 52 via.

The count value of the up/down counter 48 is controlled around the above-mentioned nine average value in accordance with the increase/decrease in the number of BCH/# pulses for each data/mother packet. And p corresponding to the count value of the up/down counter 48
A PWM wave with a width of 4 pulses is obtained at the output of the PWM circuit 53. The output of this PWM circuit 53 is supplied to the adder 2 as a correction control voltage for the voltage controlled oscillator 19.

As a result, this up-down counter 4 is within the upper and lower limit range of the de-down counter 48 set at the initial stage of channel selection.
8 a, de down count value, detected BCH/
By controlling according to the number of base pulses, voltage controlled oscillator 1
When the oscillation frequency of 9 is PSK demodulated and further PCM decoded, the frequency can be controlled to the optimum frequency so that the number of data errors is minimized.

In this way, in the operation of correcting the control voltage for the voltage controlled oscillator 19, setting the control range so that the system does not become unstable presets the limit on the count value for the up/down counter 48. It is done by In addition, BcH counted by counter 4o
If the number of nodes is abnormally large, the voltage controlled oscillator 19
Frequency control becomes difficult. Therefore, when the number of BCHIQ pulses counted by the counter 4o reaches a predetermined number, the defeat circuit 43 detects this, resets and tosses the counter 4o, and applies a control voltage to the control voltage superimposing means. Stop superimposing.

Furthermore, in the present invention, it takes a certain amount of time until the control voltage V〒 of the voltage controlled oscillator 19 becomes stable when switching channels, turning on the power, and the like. (See vT in Figure 4) Therefore, at such times, for example, the period (TA
), the control voltage V? The period of instability becomes longer.

Therefore, in order to solve this problem, in the present invention, when a channel is selected in the channel data generating section 44, the switch SW2 is controlled and the fixed counter 5 is
5 is supplied to the up/down counter 48, and the PWM
The output pulse width of the circuit 53 is fixed constant.

For example, the voltage SW superimposed on adder 2 at this time
E (see FIG. 4) is set to a fixed value so as to be a predetermined center voltage. As a result, a frequency pull-in operation of the PLL circuit constituted by the voltage controlled oscillator 19 is obtained.

Next, when BCH pulses are counted in this state, the number of pulses is reduced because the corrected control voltage is the originally expected value. (Period TB in Figure 4).

This pulse counting is performed by a counter 40 which is reset at regular intervals. Therefore, if the counted value of the counter 40 is less than a certain value, it means that the PLL circuit of the previous stage, that is, the carrier regeneration section, has become stable, so the contents of the counter 40 are judged by the defeat circuit 43, and the switch is switched based on the judgment result. It is designed to control SW2. At this time, the output of the fixed counter 55 is turned off, and the above-described operation for detecting the upper and lower limits of the pull-in frequency begins.

(See period TC in Figure 4).

That is, once the frequency pulled in by the voltage controlled oscillator 19 is set lower than the lower limit of the pull-in range, the superimposed voltage is gradually increased and the lower limit is detected while counting %BCH/#rus. Further, when detecting the upper limit, the process opposite to that when detecting the lower limit is performed. and,
upper limit.

Find the average value using the lower limit value and use the up/down counter 4
The setting to 8 is as described above.

As described above, the so-called sweep operation for determining the upper and lower limits is in a standby state until the PLL circuit is stabilized and the first defeat pulse is obtained from channel selection. Therefore, even if the time for the control voltage V〒 of the PLL circuit to stabilize during channel selection differs between channels or between #'i devices, the start point of the sweep operation is
The time it takes for it to stabilize is the time you have secured, and you can follow it freely. Furthermore, in the defeat circuit 43, if the control and normality for returning the switch SW2 cannot be obtained for a long time, this can be used to determine the presence or absence of a broadcast signal and can be displayed on the display. be.

〔Effect of the invention〕

As explained above, according to the present invention, when correcting the frequency control voltage of the PLL circuit according to the number of BCH corrections,
During a transition such as when switching channels or turning on the power, there is a means for keeping the correction voltage constant, and the constant value is released in response to a decrease in the number of BCH pulses, thereby stabilizing the operation. In addition, it is possible to provide a reproduction operation stabilizing device that can prevent the correction voltage from being used at an unnecessary timing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a PSK receiver according to the present invention, FIG. 2 is a detailed diagram showing the receiver of FIG. 1, FIG. 3 is a circuit diagram showing main parts of the invention, and FIG. The figure is a signal waveform diagram showing the operation timing of the device of this invention. 17... PSK demodulator, 18... Carrier regeneration circuit, 19... Voltage controlled oscillator, 20... Comparator, 21
...Adder, 39...Frequency correction data generation section, 4
0... Counter, 43... Defeat circuit, 44
...Channel data generation section, 47...CPU, 4
．． ! ? ...Aggdown counter, 53...PWM
Circuit, 55...Fixed counter. Applicant's attorney Takehiko E 2-A! liquid count Hisho 8-dan 3-R, a') raw rgJ well 4-11 Tetsume Δ King! ■Voice 5--Ichiai phase, 1llt, approximately Fig. 1 W2 Fig. 3

Claims (1)

[Claims] A phase comparator that compares the phase of the reproduced carrier of the phase shift key ink signal and the output of the voltage controlled oscillator, and a voltage controlled by adding a voltage corresponding to the output of the phase comparator and a correction voltage to generate the voltage controlled oscillator. correction information superimposition means for applying to a frequency control terminal of the voltage controlled oscillator, means for reproducing the carrier to which the output of the voltage controlled oscillator and the phase shift key ink signal are supplied, and demodulating the data of the phase shift key ink signal using the carrier. means for extracting a check code for data error correction from the demodulated data and counting the number of error bits in the data packet; correction data generating means for varying the correction voltage, and fixing the correction voltage to a constant value in response to at least a signal obtained when selecting a channel, and responsive to the count value of the counting means decreasing to a predetermined value or less. A reproduction operation stabilizing device comprising means for allowing variation of the correction voltage.