JPS6257324A - Trnsmission-reception changeover device - Google Patents
Trnsmission-reception changeover deviceInfo
- Publication number
- JPS6257324A JPS6257324A JP19580485A JP19580485A JPS6257324A JP S6257324 A JPS6257324 A JP S6257324A JP 19580485 A JP19580485 A JP 19580485A JP 19580485 A JP19580485 A JP 19580485A JP S6257324 A JPS6257324 A JP S6257324A
- Authority
- JP
- Japan
- Prior art keywords
- transmission
- circuit
- reception
- switching
- receiving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Transceivers (AREA)
- Bidirectional Digital Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は送受信切替装置に係り７．％にディジタルコー
ドで送受信する送受信装置において送信より受信への切
替時に好適な送受信切替装置に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a transmission/reception switching device.7. The present invention relates to a transmitting/receiving switching device suitable for switching from transmitting to receiving in a transmitting/receiving device that transmits and receives digital codes.
送受信装置で、ディジタルコードを使用して交信を行な
う場合、送信状態より受信状態に切替操作した時、送信
波形はすぐには遮断されず自然減衰しながら尾を引き、
それが受信回路へ入力されるので、受信回路系に入力さ
れるディジタルコードが判別できなくなり１次段に誤っ
た結果を送出してしまう。When communicating using a digital code with a transmitting/receiving device, when switching from the transmitting state to the receiving state, the transmitted waveform is not immediately cut off, but naturally attenuates and trails off.
Since this is input to the receiving circuit, the digital code input to the receiving circuit system cannot be discriminated, and an erroneous result is sent to the primary stage.
なお、この種の装置として関連するものには特開昭５９
−１６０３３０号が挙げられる。Additionally, related devices of this type include Japanese Patent Application Laid-open No. 59
-160330 is mentioned.
本発明の目的は、送信から後信への切替え時に送信信号
が受信回路系に伝達されるのを防ぐ送受信切替装置を提
供することにある。An object of the present invention is to provide a transmission/reception switching device that prevents a transmission signal from being transmitted to a reception circuit system when switching from transmission to subsequent transmission.
送受信装置が送信した波形を自身の受信回路で、受信し
ない様に、送信から受信状態に切替えた時受信状態にす
るタイミングを遅らせると共に、送信した時点から送信
が終了後例えば数ｍ５ｅｔ程度の間 受信回路の利得を
下げて実質的に次段に信号が伝達されないようにしたこ
とにある。In order to avoid receiving the waveform transmitted by the transmitting/receiving device in its own receiving circuit, when switching from transmitting to receiving state, the timing of switching to receiving state is delayed, and reception is performed for a period of, for example, several meters from the time of transmission until the end of transmission. The reason is that the gain of the circuit is lowered to substantially prevent the signal from being transmitted to the next stage.
第１図、第２図によυ本発明の一実施例を説明する。送
信回路１で作られた送信信号は、アンテナ回路２を介し
て、相手方の送受信機へ信号として送信するが、送信か
ら受信状態に切替えた時、その送信出力が、受信回路３
へも入力してしまう。通常その時間は切替後２ｍ秒以内
である。そこで本発明は、受信回路３と増幅回路４にス
イッチング回路５，６を設けて、これをマイクロコンピ
ュータ−７の出力端子７Ａ、７Ｂに接続する。マイクロ
コンピュータ−７Ａの出力は、送信時より送信終了後２
ｍ秒の聞出力し。An embodiment of the present invention will be described with reference to FIGS. 1 and 2. The transmission signal generated by the transmission circuit 1 is transmitted as a signal to the other party's transceiver via the antenna circuit 2, but when switching from transmission to reception state, the transmission output is transmitted to the reception circuit 3.
I also enter it into . Usually, the time is within 2 msec after switching. Therefore, in the present invention, switching circuits 5 and 6 are provided in the receiving circuit 3 and the amplifier circuit 4, and these are connected to the output terminals 7A and 7B of the microcomputer 7. The output of microcomputer 7A is 2 times after transmission is completed.
Outputs m seconds.
スイッチング回路５のトランジスタを導通して増幅回路
４の利得を下げて実質的に０とし、又マイクロコンピー
−ターフの出カフＢは、送信時より送信終了後４ｍ秒の
聞出力し、スイッチング回路６を介して、受信回路３の
信号ラインをアースに落す。具体的にはマイクロコンピ
ュータ−７は、第２図に示すフローチャート図に従って
処理する。The transistor of the switching circuit 5 is made conductive to reduce the gain of the amplifier circuit 4 to substantially 0, and the output cuff B of the microcomputer is output from the time of transmission until 4 msec after the end of transmission, and the gain of the amplifier circuit 4 is reduced to substantially 0. The signal line of the receiving circuit 3 is grounded through the ground. Specifically, the microcomputer 7 processes according to the flowchart shown in FIG.
本実施例によれば、送信から受信への切替操作時に増幅
回路４の利得が実質的に０に下げられ次段への送信信号
の伝達を阻止し、しかる後送信から受信状態に受信回路
を切替える。According to this embodiment, when switching from transmission to reception, the gain of the amplifier circuit 4 is reduced to substantially 0 to prevent transmission of the transmission signal to the next stage, and then the reception circuit changes from the transmission to reception state. Switch.
本発明によれば、送信から受信切替時、受信状態になる
タイミングを遅らせることにより。According to the present invention, when switching from transmission to reception, the timing of entering the reception state is delayed.
正確なディジタルコードを取り出せる様になるので、誤
動作をなくすことが出来る効果がある。Since it becomes possible to extract accurate digital codes, it has the effect of eliminating malfunctions.
第１図は本発明の一実施例のブロック図、第２図は第１
図のマイクロコンピュータ−動作のフローチャート図で
ある。
１・・・・・・・・・・・・・・・・・・送信回路２・
・・・・・・・・・・・・・・・・・アンテナ回路３・
・・・・・・・・・・・・・・・・・受信回路４・・・
・・・・・・・・・・・・・・・増幅回路５．６・・・
・・・・・・・・・スイッチング回路７・・・・・・・
・・・・・・・・・・・マイクロコンピュータ−７Ａ、
７Ｂ・・−・・マイクロコンピュータ−出力゛・、
代理人弁理士 小 川 勝 男゛
蔦 １ 図
！
鴛２回FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 2 is a flowchart diagram of the operation of the microcomputer shown in FIG. 1・・・・・・・・・・・・・・・・・・Transmission circuit 2・
・・・・・・・・・・・・・・・・Antenna circuit 3・
・・・・・・・・・・・・・・・・・・Reception circuit 4...
・・・・・・・・・・・・・・・Amplification circuit 5.6...
......Switching circuit 7...
・・・・・・・・・・・・Microcomputer-7A,
7B...Microcomputer output゛・, Attorney Katsutoshi Ogawa 1 Figure! 2 times
Claims (1)
信より受信への切替時受信状態にするタイミングを遅ら
せる第１回路と、切替時受信回路の増幅回路を送信信号
が次段に伝達されるのを阻止するようその利得を下げる
第２回路を設けたことを特徴とする送受信切替装置。In a transmitting/receiving device that communicates using a digital code, a first circuit that delays the timing of entering a receiving state when switching from transmitting to receiving, and an amplifier circuit of the receiving circuit when switching are used to prevent transmitting signals from being transmitted to the next stage. A transmitting/receiving switching device characterized in that a second circuit for lowering the gain of the filter is provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19580485A JPS6257324A (en) | 1985-09-06 | 1985-09-06 | Trnsmission-reception changeover device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19580485A JPS6257324A (en) | 1985-09-06 | 1985-09-06 | Trnsmission-reception changeover device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6257324A true JPS6257324A (en) | 1987-03-13 |
Family
ID=16347253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19580485A Pending JPS6257324A (en) | 1985-09-06 | 1985-09-06 | Trnsmission-reception changeover device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6257324A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0226835U (en) * | 1988-08-05 | 1990-02-21 |
-
1985
- 1985-09-06 JP JP19580485A patent/JPS6257324A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0226835U (en) * | 1988-08-05 | 1990-02-21 |
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